绝缘层/有源层界面修饰及对有机薄膜晶体管性能的影响

制备了具有修饰层的有机薄膜场效应晶体管,采用高掺杂Si作为栅极,传统的无机绝缘材料SiO2作为栅绝缘层,有机绝缘材料PMMA或OTS作为修饰层,CuPc作为有源层,Au作为源、漏极.测试结果表明,采用经过修饰的栅绝缘层SiO2/OTS和SiO2/PMMA的两种器件的开关电流比最高可达8×104,迁移率最高为1.22×10-3cm2/(V·s),而漏电流仅为10-10A,总体性能优于单层SiO2器件.     

A new metal-ferroelectric (PbZr/sub 0.53/Ti/sub 0.47/O/sub 3/)-insulator (Dy/sub 2/O/sub 3/)-semiconductor (MFIS) FET for nonvolatile memory applications

Metal-ferroelectric-insulator-semiconductor (MFIS) field-effect transistors with Pb(Zr/sub 0.53/,Ti/sub 0.47/)O/sub 3/ ferroelectric layer and dysprosium oxide Dy/sub 2/O/sub 3/ insulator layer were fabricated. The out-diffusion of atoms between Dy/sub 2/O/sub 3/ and silicon was examined by secondary ion mass spectrometry profiles. The size of the memory windows was investigated. The memory windows measured from capacitance-voltage curves of MFIS capacitors and I/sub DS/-V/sub GS/ curves of MFIS transistors are consistent. The nonvolatile operation of MFIS transistors was demonstrated by applying positive/negative writing pulses. A high driving current of 9 /spl mu/A//spl mu/m was obtained even for long-channel devices with a channel length of 20 /spl mu/m. The electron mobility is 181 cm/sup 2//V/spl middot/s. The retention properties of MFIS transistors were also measured.     

Electrical and reliability characteristics of an ultrathin TaO/sub x/N/sub y/ gate dielectric prepared by ND/sub 3/ annealing of Ta/sub 2/O/sub 5/

This letter describes a unique process for the preparation of high quality tantalum oxynitride (TaO/sub x/N/sub y/) via the ND/sub 3/ annealing of Ta/sub 2/O/sub 5/, for use in gate dielectric applications. Compared with tantalum oxide (Ta/sub 2/O/sub 5/), a significant improvement in the dielectric constant was obtained by the ammonia treatment followed by light reoxidation in a wet ambient. We were able to confirm nitrogen incorporation in the tantalum oxynitride (TaO/sub x/N/sub y/) by Auger electron spectroscopy. Compared with NH/sub 3/ nitridation, tantalum oxynitride prepared by nitridation in ND/sub 3/ shows less charge trapping and larger charge-to-breakdown characteristics.     

Low-Temperature Materials and Thin Film Transistors for Flexible Electronics

This paper addresses the low-temperature deposition processes and electronic properties of silicon based thin film semiconductors and dielectrics to enable the fabrication of mechanically flexible electronic devices on plastic substrates. Device quality amorphous hydrogenated silicon (a-Si:H), nanocrystalline silicon (nc-Si), and amorphous silicon nitride (a-SiN/sub x/) films and thin film transistors (TFTs) were made using existing industrial plasma deposition equipment at the process temperatures as low as 75/spl deg/C and 120/spl deg/C. The a-Si:H TFTs fabricated at 120/spl deg/C demonstrate performance similar to their high-temperature counterparts, including the field effect mobility (/spl mu//sub FE/) of 0.8 cm/sup 2/V/sup -1/s/sup -1/, the threshold voltage (V/sub T/) of 4.5 V, and the subthreshold slope of 0.5 V/dec, and can be used in active matrix (AM) displays including organic light emitting diode (OLED) displays. The a-Si:H TFTs fabricated at 75/spl deg/C exhibit /spl mu//sub FE/ of 0.6 cm/sup 2/V/sup -1/s/sup -1/, and V/sub T/ of 4 V. It is shown that further improvement in TFT performance can be achieved by using n/sup +/ nc-Si contact layers and plasma treatments of the interface between the gate dielectric and the channel layer. The results demonstrate that with appropriate process optimization, the large area thin film Si technology suits well the fabrication of electronic devices on low-cost plastic substrates.     

A novel MONOS-type nonvolatile memory using high-/spl kappa/ dielectrics for improved data retention and programming speed

This paper presents a novel metal-oxide-nitride-oxide-silicon (MONOS)-type nonvolatile memory structure using hafnium oxide (HfO/sub 2/) as tunneling and blocking layer and tantalum pentoxide (Ta/sub 2/O/sub 5/) as the charge trapping layer. The superiorities of such devices to traditional SiO/sub 2/-Si/sub 3/N/sub 4/-SiO/sub 2/ stack devices in obtaining a better tradeoff between faster programming and better retention are illustrated based on a band engineering analysis. The experimental results demonstrate that the fabricated devices can be programmed as fast as 1 /spl mu/s and erased from 10 ns at an 8-V gate bias. The retention decay rate of this device is improved by a factor more than three as compared to the conventional MONOS/SONOS type devices. Excellent endurance and read disturb performance are also demonstrated.     

Air-gap polycrystalline silicon thin-film transistors for fully integrated sensors

Air gap thin-film transistors (TFTs) were fabricated using a solid phase crystallization process. Undoped polycrystalline silicon (polysilicon) was used as the active layer and a highly doped polysilicon bridge was used as the gate, which promotes the air gap. These TFTs have comparable threshold voltage (V/sub T/) and subthreshold slope characteristics to TFTs fabricated using pulsed laser crystallization, and using silicon dioxide as gate insulator. The low value of V/sub T/ is very important for low power consumption. Moreover, the air-gap TFT fabrication process is compatible with low-temperature glass substrate technology, which allows the integration of sensors and electronics circuits.     

AMOLED panel driven by OTFTs on polyethylene fabric substrate

In this study, AMOLED display panel was fabricated on polyethylene (PET) fabric substrate. By considering flexibility of the PET fabric, organic thin film transistors (OTFTs), which used TIPS-pentacene as the active layer material, were adopted as the driving devices for the OLEDs. A standard pixel circuit was employed using two OTFTs and one capacitor and one OLED. The panel specifications were as follows; a pixel pitch of 1.5 × 1.5 mm, a resolution of 32 × 32, an aperture ratio of 22%, and a diagonal length of 2.7 inches. The large surface roughness of the PET fabric could be reduced down to 0.3 μm from the initial roughness of 10 μm by coating polyurethane and photo-acrylic with a two-step process. On the smoothened fabric, the OTFTs and OLEDs were integrated into the pixel array through the key processes, the self-patterning of the gate dielectric of the OTFTs and the patterning of the TIPS-pentacene layer. The mobility of two OTFTs was 0.23 and 0.34 cm²/V∙sec in the pixel array, respectively, and the luminance of the OLED was 64,459 cd/m². The AMOLED panel successfully operated to vary the luminance of each pixel according to the applied voltages.     

Mobility enhancement in TaN metal-gate MOSFETs using tantalum incorporated HfO/sub 2/ gate dielectric

TaN metal-gate nMOSFETs using HfTaO gate dielectrics have been investigated for the first time. Compared to pure HfO/sub 2/, a reduction of one order of magnitude in interface state density (D/sub it/) was observed in HfTaO film. This may be attributed to a high atomic percentage of Si-O bonds in the interfacial layer between HfTaO and Si. It also suggests a chemical similarity of the HfTaO-Si interface to the high-quality SiO/sub 2/-Si interface. In addition, a charge trapping-induced threshold voltage (V/sub th/) shift in HfTaO film with constant voltage stress was 20 times lower than that of HfO/sub 2/. This indicates that the HfTaO film has fewer charged traps compared to HfO/sub 2/ film. The electron mobility in nMOSFETs with HfO/sub 2/ gate dielectric was significantly enhanced by incorporating Ta.     

A novel high-/spl kappa/ SONOS memory using TaN/Al/sub 2/O/sub 3//Ta/sub 2/O/sub 5//HfO/sub 2//Si structure for fast speed and long retention operation

A novel high-/spl kappa/ silicon-oxide-nitride-oxide-silicon (SONOS)-type memory using TaN/Al/sub 2/O/sub 3//Ta/sub 2/O/sub 5//HfO/sub 2//Si (MATHS) structure is reported for the first time. Such MATHS devices can keep the advantages of our previously reported TaN/HfO/sub 2//Ta/sub 2/O/sub 5//HfO/sub 2//Si device structure to obtain a better tradeoff between long retention and fast programming as compared to traditional SONOS devices. While at the same time by replacing hafnium oxide (HfO/sub 2/) with aluminum oxide (Al/sub 2/O/sub 3/) for the top blocking layer, better blocking efficiency can be achieved due to Al/sub 2/O/sub 3/'s much larger barrier height, resulting in greatly improved memory window and faster programming. The fabricated devices exhibit a fast program and erase speed, excellent ten-year retention and superior endurance up to 10/sup 5/ stress cycles at a tunnel oxide of only 9.5 /spl Aring/ equivalent oxide thickness.     

具有双绝缘层的有机薄膜晶体管

为了提高SiO2单绝缘层器件的性能,在SiO2绝缘层的表面用旋涂的方法制备一层大约50 nm厚度的PMMA.实验结果表明用无机/有机双绝缘层可以有效的提高器件的性能同时降低器件的漏电流.计算出了载流子迁移率和开关电流比,基于PMMA/SiO2双绝缘层器件的载流子迁移率和开关电流比分别是4.0×10-3cm2/Vs和104.     

易于集成的有机薄膜场效应晶体管的制备

用有机半导体并五苯作为有源层,聚四氟乙烯作为绝缘层,采用全蒸镀方式在真空室一次性制备了正装结构的有机薄膜场效应晶体管(OTFT)。薄的有机绝缘层使得器件工作在低电压下,有机薄膜场效应晶体管易于与显示像素(有机发光二极管(OLED))集成在同一个透明的刚性或者柔性衬底上。研究了有机薄膜场效应晶体管的源漏接触电阻和沟道电阻对器件性能的影响,结果表明接触电阻是影响器件性能的主要因素。在透明的玻璃衬底上实现了有机薄膜场效应晶体管对同一衬底上100μm×200μm红色有机发光二极管的驱动。     

Transistor action of metal (CoSi/sub 2/)/insulator (CaF/sub 2/) hot electron transistor structure

The first transistor action of tunnelling hot electron transistors with single-crystalline metal (CoSi/sub 2/)/insulator (CaF/sub 2/) has been achieved. This device consists of CoSi/sub 2//CaF/sub 2/ heterojunctions grown on n-Si     

Hydrogenated amorphous silicon thin-film transistor on plastic with an organic gate insulator

We developed a high-performance, hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) on plastic substrate using an organic gate insulator. The TFT with a silicon-nitride (SiN/sub x/) gate insulator exhibited a field-effect mobility of 0.3 cm/sup 2//Vs and a threshold voltage of 5 V. On the other hand, an a-Si:H TFT with an organic gate insulator of BCB (benzocyclobutene) has a field-effect mobility of 0.4 cm/sup 2//Vs and a threshold voltage of 0.7 V. The leakage currents through the gate insulator of an a-Si:H TFT with an organic gate insulator is about two orders of magnitude lower than that of an a-Si:H TFT with a SiN/sub x/ gate insulator.     

Triacetate cellulose gate dielectric organic thin-film transistors

Here, we report on the performance and the characterization of all solution-processable top-contact organic thin-film transistors (OTFTs) consisting of a natural-resourced triacetate cellulose gate dielectric and a representative hole-transport poly[2,5-bis(3-dodecylthiophen-2-yl)thieno[3,2-b]thiophene] (pBTTT) semiconductor layer on rigid or flexible substrates. The bio-based triacetate cellulose layer has an important role in the OTFT fabrication because it provides the pBTTT semiconducting polymer with highly suitable gate dielectric properties including a low surface roughness, hydrophobic surface, appropriate dielectric constant, and low leakage current. The triacetate cellulose gate dielectric-based pBTTT OTFTs exhibit an average filed-effect mobility of 0.031 cm²/Vs similar to that obtained from a SiO₂ gate dielectric-based OTFT device in ambient conditions. Even after a bending stimulation of 100 times and in an outward bending state, the flexible triacetate cellulose gate pBTTT OTFT device still showed excellent electrical device performance without any hysteresis.     

High-performance Pt/SrBi/sub 2/Ta/sub 2/O/sub 9//HfO/sub 2//Si structure for nondestructive readout memory

Metal-ferroelectric-insulator-semiconductor (MFIS) capacitors with 390-nm-thick SrBi/sub 2/Ta/sub 2/O/sub 9/ (SBT) ferroelectric film and 8-nm-thick hafnium oxide (HfO/sub 2/) layer on silicon substrate have been fabricated and characterized. It is demonstrated for the first time that the MFIS stack exhibits a large memory window of around 1.08 V at an operation voltage of 3.5 V. Moreover, the MFIS memory structure suffers only 18% degradation in the memory window after 10/sup 9/ switching cycles. The excellent performance is attributed to the formation of well-crystallized SBT perovskite thin film on top of the HfO/sub 2/ buffer layer, as evidenced by the distinctive sharp peaks in X-ray diffraction (XRD) spectra. In addition to its relatively high /spl kappa/ value, HfO/sub 2/ also serves as a good seed layer for SBT crystallization, making the proposed Pt/SrBi/sub 2/Ta/sub 2/O/sub 9//HfO/sub 2//Si structure ideally suitable for low-voltage and high-performance ferroelectric memories.     

One-pot surface modification of poly(ethylene-alt-maleic anhydride) gate insulators for low-voltage DNTT thin-film transistors

This study investigates the one-pot surface modification of poly(ethylene-alt-maleic anhydride) (PEMA) gate insulators crosslinked with 1,5-naphthalenediamine (1,5-NDA) for enhancing the device performance of low-voltage dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene (DNTT) organic thin-film transistors (OTFTs). Surface properties of the PEMA gate insulator could be easily modified by adding poly(maleic anhydride-alt-1-octadecene) (PMAO) to the coating solution. The surface energy of the gate insulator is strongly correlated with the growth of organic semiconductors and the charge carrier transport at the interface between the semiconductor and gate insulator. The results indicate that the device performance of low-voltage DNTT OTFTs can be improved by one-pot surface modification of the PEMA gate insulator.     

An Organic Thin‐Film Transistor with a Photoinitiator‐Free Photosensitive Polyimide as Gate Insulator

This investigation deals with the synthesis and detailed study of a photoinitiator‐free photosensitive polyimide gate insulator for organic thin‐film transistors (OTFTs), one of the most important components of active‐matrix displays on plastic substrates. The photosensitive polyimide precursor poly(amic acid) is prepared from the aromatic dianhydride 3,3′,4,4′‐benzophenone tetracarboxylic dianhydride (BTDA) and the novel aromatic diamine 7‐(3,5‐diaminobenzoyloxy)coumarine (DACM). The photosensitivity of the poly(amic acid) film is investigated using a high‐pressure mercury lamp at 280–310 nm. The pattern resolution of the photocured film was about 50 μm. The surface morphology of the films before and after the photopatterning process is also investigated. In addition, we have fabricated pentacene OTFTs with the photoinitiator‐free photosensitive polyimide as gate insulator. The OTFT characteristics are discussed in more detail with respect to the electrical properties of the photosensitive polyimide thin film.     

Organic thin film transistors with PMMA modified insulator

A double insulation layer structure organic thin films transistor (OTFT) was investigated for improving the performance of the SiO2 gate insulator. A 50 nm PMMA layer was coated on top of the SiO2 gate insulator as the organic insulator layer. The results demonstrated that using inorganic/organic compound insulator as the gate dielectric layer is an effective method to fabricate OTFTs with improved electric characteristics and decreased leakage current. Electrical parameters of carrier mobility and on/off ratio were calculated. OTFT based on Si substrate with a field-effect mobility of 4.0 × 10-3cm2/Vs and on/off ratio of 104 was obtained.     

Arbitrary Density of States in an Organic Thin-Film Field-Effect Transistor Model and Application to Pentacene Devices

We present a modular numerical model for organic thin-film field-effect transistors (OTFTs) that allows for an arbitrary density of states to be independently defined for the semiconductor bulk and the semiconductor surface next to the gate insulator. We can derive the surface charge density dependence on the interface field as well as the space-charge-limited current characteristics. Together with a model of the contacts, we arrive at a physical model that is applied to a series of OTFTs in staggered inverted (top contact) geometry with various gate insulator treatments     

547-GHz f/sub t/ In/sub 0.7/Ga/sub 0.3/As-In/sub 0.52/Al/sub 0.48/As HEMTs with reduced source and drain resistance

We fabricated 30-nm gate pseudomorphic channel In/sub 0.7/Ga/sub 0.3/As-In/sub 0.52/Al/sub 0.48/As high electron mobility transistors (HEMTs) with reduced source and drain parasitic resistances. A multilayer cap structure consisting of Si highly doped n/sup +/-InGaAs and n/sup +/-InP layers was used to reduce these resistances while enabling reproducible 30-nm gate process. The HEMTs also had a laterally scaled gate-recess that effectively enhanced electron velocity, and an adequately long gate-channel distance of 12nm to suppress gate leakage current. The transconductance (g/sub m/) reached 1.5 S/mm, and the off-state breakdown voltage (BV/sub gd/) defined at a gate current of -1 mA/mm was -3.0 V. An extremely high current gain cutoff frequency (f/sub t/) of 547 GHz and a simultaneous maximum oscillation frequency (f/sub max/) of 400 GHz were achieved: the best performance yet reported for any transistor.