Reliability results of HBTs with an InGaP emitter

Accelerated lifetest results are presented on HBTs with InGaP emitters. An Arrhenius plot indicates the existence of a temperature dependent activation energy, E_a. A low E_a mechanism dominates above T_j 380 °C and a high E_a mechanism dominates at lower temperature. The critical transition temperature between regimes is determined using the method of maximum likelihood. The difference in E_a’s between low and high temperature regimes is statistically significant.A comparison is made between lifetimes determined from at temperature vs. 40 °C data. No significant difference is observed indicating that beta degradation can be monitored at temperature only and cooling to low temperature is not necessary. Other comparisons indicate that junction temperatures up to 367 °C can still provide good estimates of lower temperature behavior.By the method of maximum likelihood, the predicted MTTF at T_j = 125 °C is 7.6 × 10⁹ h with 95% CBs of [6.4 × 10⁸, 8.9 × 10¹⁰]. Given the typical industry standard of 1 × 10⁶ h, the reliability requirements are easily met.It is suggested that the standard of 1 × 10⁶ h does not adequately capture failure time variation and that a better specification is in terms of fails in time (FITs). The 10 year average FIT rate at 125 °C is found to be negligible. Assuming a much higher junction temperature of 210 °C, the average failure rate climbs to 5 FITs with an upper 95% confidence bound of 40 FITs.     

Electrical and structural properties of hafnium silicate thin films

Thin (4 nm) hafnium silicate (HfO₂)_x(SiO₂)_1−x/SiO₂ gate stacks (0 < x < 1) grown by metal organic chemical vapour deposition (MOCVD) are investigated in this study. The focus is on extracting the optical constants, and hence bandgaps as well as dielectric constants. The VUV (vacuum ultraviolet) spectroscopic ellipsometry (VUV-SE) technique in the spectral range 140–1700 nm, together with current–voltage and capacitance–voltage techniques were used for studying the optical and electrical properties of the layers, respectively. The bandgap was found to increase from 5.24 eV for HfO₂ to 6 eV for Hf-silicate with 30% Hf. The permittivity was reduced from 21 for HfO₂ layers to 8 for Hf-silicate with x = 0.3. The results suggest that the optimal Hf content is above 0.6, for which the permittivity higher than 10 can be achieved.     

Etching characteristics of ZnO thin films in chlorine-containing inductively coupled plasmas

This study examined the plasma etching characteristics of ZnO thin films etched in BCl₃/Ar, BCl₃/Cl₂/Ar and Cl₂/Ar plasmas with a positive photoresist mask. The ZnO etch rates were increased in a limited way by increasing the gas flow ratio of the main etch gases in the BCl₃/Ar, BCl₃/Cl₂/Ar and Cl₂/Ar plasmas at a fixed dc self-bias voltage (V_dc). However, the ZnO etch rate was increased more effectively by increasing the V_dc. Optical emission spectroscopy (OES) and X-ray photoelectron spectroscopy (XPS) analyses of the ZnO surfaces etched at various Cl₂/(Cl₂ + Ar) mixing ratios revealed the formation of the ZnO_xCl_y reaction by-products as a result of the increased etch rate with increasing Cl₂ addition, compared with 100% Ar⁺ sputter etching. This suggests that at Cl₂/Ar flow ratios ⩾20%, the ZnO etch process is controlled by an ion-assisted removal mechanism where the etch rate is governed by the ion-bombardment energy under the saturated chlorination conditions.     

Electrical properties of SiO2/TiO2 high-k gate dielectric stack

The trapping/detrapping behavior of charge carriers in ultrathin SiO₂/TiO₂ stacked gate dielectric during constant current (CCS) and voltage stressing (CVS) has been investigated. Titanium tetrakis iso-propoxides (TTIP) was used as the organometallic source for the deposition of ultra-thin TiO₂ films at low temperature (<200 °C) on strained-Si/relaxed-Si_0.8Ge_0.2 heterolayers by plasma-enhanced chemical vapor deposition (PECVD) in a microwave (700 W, 2.45 GHz) plasma cavity discharge system at a pressure of 66.67 Pa. Stress-induced leakage current (SILC) through SiO₂/TiO₂ stacked gate dielectric is modeled by taking into account the inelastic trap-assisted tunneling (ITAT) mechanism via traps located below the conduction band of TiO₂ layer. The increase in the gate current density observed during CVS from room temperature up to 125 ^oC has been analyzed and modeled considering both the buildup of charges in the layer as well as the SILC contribution. Trap generation rate and trap cross-section are extracted. A capture cross-section in the range of 10⁻¹⁹ cm² as compared to 10⁻¹⁶ cm² in SiO₂ has been observed. A temperature-dependent trap generation rate and defects have also been investigated using time-dependent current density variation during CVS. The time dependence of defect density variation is calculated within the dispersive transport model, assuming that these defects are produced during random hopping transport of positively charge species in the insulating high-k stacked layers. SILC generation kinetics, i.e. defect generation probability under different injected fluences for various high-constant stress voltages in both polarities have been studied. An empirical relation between trap generation probability and applied stress voltage for various injected fluences has been developed.     

Germanium FETs and capacitors with rare earth CeO2/HfO2 gates

Long channel Ge FETs and capacitors with CeO₂/HfO₂/TiN gates were fabricated by photolithography and gate wet etch. Rare earth CeO₂ in direct contact with Ge was used as a passivating layer producing lowest D_it values in the mid 10¹¹ eV⁻¹ cm⁻² range. HfO₂ cap reduces leakage and improves equivalent oxide thickness scaling of the whole gate stack. The p-FETs show exceptionally high I_ON/I_OFF ratio 10⁶, mainly due to low OFF current, and peak channel mobility around 80 cm²/V s. The n-FETs, although functional, show inferior performance producing ON currents an order of magnitude lower compared to p-FETs.     

The separation of generation lifetimes of Si and SiGe using capacitance-transient measurements on MOS capacitors formed by plasma anodisation of Si:Si0.9Ge0.1:Si substrates

A simple technique leading to the measurement of minority carrier lifetimes of UHV compatible LPCVD Si and SiGe by C–t depth profiling of Metal:Oxide:Si:SiGe:Si structures is reported. A high quality gate oxide is realised by low temperature (<100°C) plasma anodisation thereby reducing any oxidation effects on the underlying epitaxial layer quality. Capacitance response times were observed for an impurity concentration of 2.5×10¹⁷ cm⁻³, giving rise to generation lifetimes of the Si and Si_0.9Ge_0.1 of >0.55 and 2.6 μs respectively, reflective of very high quality epitaxial semiconductor material.     

Pentacene organic field-effect transistors with polymeric dielectric interfaces: Performance and stability

Low-voltage pentacene organic field-effect transistors (OFETs) with different gate dielectric interfaces are studied and their performance in terms of electrical properties and operational stability is compared. Overall high electrical performance is demonstrated at low voltage by using a 100 nm-thick high-κ gate dielectric layer of aluminum oxide (Al₂O₃) fabricated by atomic layer deposition (ALD) and modified with hydroxyl-free low-κ polymers like polystyrene (PS), divinyltetramethyldisiloxane-bis(benzocyclobutene) (BCB) (Cyclotene™, Dow Chemicals), and as well as with the widely used octadecyl-trichlorosilane (OTS). Devices with PS and BCB dielectric surfaces exhibit almost similar electrical performance with high field-effect mobilities, low subthreshold voltages, and high on/off current ratios. The higher mobility in pentacene transistors with PS can be correlated to the better structural ordering of pentacene films, as demonstrated by atomic force microscopy (AFM) images and X-ray diffraction (XRD). The devices with PS show good electrical stability under bias stress conditions (V_GS = V_DS = −10 V for 1 h), resulting in a negligible drop (2%) in saturation current (I_DS) in comparison to that in devices with OTS (12%), and to a very high decay (30%) for the devices with BCB.     

Determining factors affecting ESD failure voltage using DOE

Factors influencing machine model (MM) ESD failure voltage are investigated in two statistically designed experiments. Several variables (or factors), namely wafer lot, type of ESD handling procedure, pulse polarity order and assembly house are studied. The results are examined using three methods: survival analysis, logistic regression and an empirical approach. Each method can be used to predict the cumulative distribution function (cdf) which is the probability of failure on or before a particular voltage. Survival analysis treats the failure voltage as a response to the settings of the various factors. The failure voltage is analogous to the “failure time”. This method predicts the cdf given the settings of the different variables. In contrast, logistic regression treats voltage as a factor, along with the other variables and will similarly predict the cdf given the settings of all the factors. The empirical approach is used to estimate the cdf using only the distribution of failure voltages for each run in a designed experiment and is not derived from the factor settings. This third approach can be used as a check on the first two.In the first DOE, the factors wafer lot, level of ESD-safe handling, pulse polarity order and their interactions are found to change the predicted median failure voltage from 19 to 34 V, a swing of ±30% from the overall median 26 V. The effect of wafer lot along with the interaction between the level of ESD protection and pulse polarity order are found to be statistically significant. In the second DOE, only the effects of wafer and assembly house are studied. Here, just wafer has a significant effect. The range of ESD failure voltages is much smaller in round 2 (30 to 36 V).Although the failure voltages reported here are relatively low, the methods described herein are general. Thus, the approaches described can be applied to circuits with much higher ESD failure voltages.     

Nanoscale electrical characterization of ultrathin high-k dielectric MOS stacks: A conducting AFM study

Extreme scaling in both silicon and alternative channel CMOS has highlighted the importance of localized characterization on the nanometer scale. We have used a conductive-contact atomic force microscopy (C-AFM) technique in ultra high vacuum (UHV) conditions to analyze and compare intrinsic stack degradation mechanisms leading to breakdown (BD) for ultrathin high-k dielectric films of (4 nm) Hf_xSiO_y/SiO₂ on Si and (2 nm) ZrO₂/GeO₂ on Ge. Simultaneous nanoscale current–voltage I–V characteristics, topography, tunneling current and relative tip–surface contact interactions as normal and lateral force maps revealed localized injected charge dependence on electrical stress. It is shown that the charge can propagate laterally. Successive voltage scanning is related to the overall post-BD conductivity for pre- to post-BD degradation propagation. In contrast with SiO₂ interface, an increased GeO₂ interlayer reactivity yielding more active interface defects is suggested.     

Indium tin oxide-free semi-transparent inverted polymer solar cells using conducting polymer as both bottom and top electrodes

Poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS) is investigated as a transparent cathode to replace indium tin oxide (ITO) in inverted polymer solar cells. Increasing the thickness of the PEDOT:PSS electrode leads to a reduction in transparency and sheet resistance which lowers the photocurrent but increases the fill factor of the solar cells. The offset of photocurrent and fill factor as the thickness is increased leads to a saturation of the power conversion efficiency to 3%. These electrodes were applied to flexible substrates showing similar device performance to glass based devices. Cyclic bending test of these flexible polymer electrodes show improved conversion efficiency retention (92%) when compared to flexible ITO based electrodes (50%) after 300 bend cycles. In addition to using PEDOT:PSS as a cathode replacement for ITO in inverted solar cells, its use as a semi-transparent anode replacement to Ag is also examined. Semi-transparent inverted solar cells fabricated with ITO as the cathode and PEDOT:PSS as the top anode electrode were demonstrated showing efficiencies of 2.51% while replacement of both ITO and Ag with PEDOT:PSS as both the cathode and anode show efficiencies of 0.47%.     

Bulk oxide charge and slow states in Si–SiO2 structures generated by RIE-mode plasma

The damage induced in the thin SiO₂–Si system after an exposure to O₂ and N₂ plasma working in reactive ion etching (RIE) mode has been studied. A generation of high density (up to 5×10¹² cm⁻² in the first 15 s plasma exposure) of positive oxide charge in bulk traps as well as in slow states has been established. The RIE damage effects become highly process dependent as the plasma time increases, the fixed oxide charge first increases and then slows down or even turns around depending on discharge conditions. It is suggested that the relative contribution of the two main plasma components (ion bombardment and vacuum UV photons) at different discharge regimes is the reason for the appearance or the absence of the “turn-around” effect. It is established that the combination O₂ plasma and low pressure is critical for the degradation of the plasma treated samples. The results reveal a strong linear correlation between the leakage current detected and plasma created positive charge.     

High performance a-Si:H thin film transistors based on aluminum gate metallization

We present a systematic study of the sputter deposition conditions for aluminum thin films employed as gate metallization for high performance a-Si:H thin film transistors (TFTs). Here, we vary sputtering parameters such as deposition temperature, process pressure, and power, all of which have a strong bearing on the surface roughness of the film, including hillock generation induced by thermal processing. For example, at a low deposition temperature (30°C) and a low process pressure (5 mTorr), the surface roughness appeared to be significantly reduced. Transistors with gate metallization deposited under these conditions show a low leakage current (10 fA), an ON/OFF ratio better than 10⁸, and a mobility of 1.1 cm²/V s. In contrast, films deposited at 150°C and 10 mTorr, yield a degradation in mobility to 0.77 cm²/V s and an increase in leakage current to 1 pA, caused by the high interface roughness of the TFT channel due to hillock formation on the Al gate.     

Effect of trap density on the dielectric response of varistor ceramics

A careful analysis of the dielectric response of ZnO-based commercial varistors in the frequency range between 100 Hz and 15 MHz and temperature range from 290 to 400 K enables a complete characterization of deep level electronic transitions in space-charge regions. In the investigated systems, oxygen vacancies are the origin of trap states situated 0.30 eV below the conduction band. However, samples exhibit a contrasting dielectric response concerning the power law exponent of the loss peak. First we present the case of near-Debye behaviour modeled by a Cole-Cole response with slight deviations α0.1 (it is ascribed to a distribution of activation energies) and next the case of very broad loss peaks (nearly constant-loss dielectric response). In this last case, the relative increment in the value of the real part of the capacitance (C₀-C_∞)/C_∞ (which is commonly used as a measure of the density of trapping states in semiconductor devices) reaches higher values than those obtained for the former. This suggests that dielectric loss broadness can be regarded as an indication of high density or a disordered distribution of traps.     

Investigation of strontium tantalate thin films for high-k gate dielectric applications

Strontium tantalate (STO) films were grown by liquid-delivery (LD) metalorganic chemical vapor deposition (MOCVD) using Sr[Ta(OEt)₅(OC₂H₄OMe)]₂ as precursor. The deposition of the films was investigated in dependence on process conditions, such as substrate temperature, pressure, and concentration of the precursor. The growth rate varied from 4 to 300 nm/h and the highest rates were observed at the higher process temperature, pressure, and concentration of the precursor. The films were annealed at temperatures ranging from 600 to 1000 °C. Transmission electron microscopy (TEM), X-ray diffraction (XRD), and ellipsometry indicated that the as-deposited and the annealed films were uniform and amorphous and a thin (>2 nm) SiO₂ interlayer was found. Crystallization took place at temperatures of about 1000 °C. Annealing at moderate temperatures was found to improve the electrical characteristics despite different film thickness (effective dielectric constant up to 40, the leakage current up to 6×10⁻⁸ A/cm², and lowest midgap density value of 8×10¹⁰ eV⁻¹ cm⁻²) and did not change the uniformity of the STO films, while annealing at higher temperatures (1000 °C) created voids in the film and enhanced the SiO₂ interlayer thickness, which made the electrical properties worse. Thus, annealing temperatures of about 800 °C resulted in an optimum of the electrical properties of the STO films for gate dielectric applications.     

Dielectric thin films for MEMS-based optical sensors

Nanoindentation and optical measurements have been employed in order to investigate the mechanical properties of low-temperature (50–330 °C) plasma-enhanced chemical vapour deposited (PECVD) SiN_x, as well as thermally evaporated SiO_x and Ge thin films for applications in micro-electro-mechanical systems (MEMS) fabricated on temperature sensitive, non-standard substrates. The temperature of the SiN_x deposition process is found to strongly influence Young’s modulus, hardness, and stress, with a critical deposition temperature in the 100 °C to 150 °C range which depends on the details of other deposition conditions such as chamber pressure and RF-power. The properties of PECVD SiN_x films deposited above this critical temperature are found to be suitable for MEMS applications, whereas films deposited at lower temperatures exhibit low Young’s modulus and hardness, as well as environment-induced stress instabilities. The investigated thin films have been incorporated into a monolithic integrated technology comprising low-temperature (125 °C) MEMS and HgCdTe IR detectors, in order to realize successful prototypes of tuneable IR microspectrometers.     

The effect of Cu diffusion on the TDDB behavior in a low-k interlevel dielectrics

The effect of Copper on TDDB failure in a structure incorporating a low-k interlevel dielectric was studied theoretically and experimentally. Interdigitated comb capacitor structures were prepared with and without Cu metallization and stressed at 4.0 to 6.6 MV/cm at 150C. The samples without Cu did not fail to over 1800 hours at 4 MV/cm whereas the samples with Cu exhibited a median time to failure (t₅₀) of 45 minutes. At 6.6 MV/cm, the t₅₀ was 1.8 hours for the Cu free samples. This experiment demonstrated the importance of Cu in the TDDB behaviour of low-k dielectrics, but also demonstrated that the presence of Cu was not a necessary condition for failure. The effect of Cu diffusion on TDDB behaviour was studied in the context of the “Impact Damage” model. Both field assisted ionic diffusion and diffusion of neutral Cu was considered. It is seen that the behaviour at low fields near use conditions may have little relationship to the predictions obtained from the results of typical TDDB testing.     

High strength coupling and low polarization-dependent long-period fiber gratings based on the helicoidal structure

A compact helicoidal long-period fiber grating (HLPFG) was fabricated by twisting a single mode fiber with CO₂ laser beam exposure and its characteristic was experimentally investigated. The eccentricity between the core and the cladding of a fiber is introduced from the screw-type deformation. This helically induced significant periodic index change along the fiber produces strong mode coupling between the core and the cladding of −20 dB with a short grating length of 1 cm. The novel resonance wavelength shift of a HLPFG was analyzed with co-directional or contra-directional torsion to the helix.     

Metallization of microvias by sputter-deposition

In high-density interconnection technologies the size of via holes significantly effects the space available for component assembly. Commonly used CO₂ lasers do not produce microvias small enough for future demands. In this paper we investigate metallization of UV-laser drilled microvias by magnetron sputtering.The core material of the test boards was a copper-clad FR-4 laminate. The boards were coated with two types of nonphotoimageable liquid dielectrics. A thin chrome layer (0.1 μm) with a subsequent copper layer (3 μm) or copper layer without any intermediate chrome layer was sputtered onto the surfaces and within the microvias. Copper was electrolytically grown onto the sputtered metal layers. In fine lines the adhesion of the metallic layer to the core material is essential. Our earlier studies have shown that chrome has good adhesion to epoxy and it is used as a seeding layer between epoxy and sputtered copper.The purpose of our research is to assess the usefulness of sputtering techniques for metallizing small vias and to find a combination of dielectric material, technologies for microvia formation and plating for achieving reliable microvia connections. Microvias were analyzed after every process stage by means of a microscope and a scanning electronic microscope.     

Tin whisker formation of lead-free plated leadframes

This paper presents the evaluation results of whiskers on two kinds of lead-free finish materials at the plating temperature and under the reliability test. The rising plating temperature caused increasing the size of plating grain and shorting the growth of whisker. The whisker was grown under the temperature cycling the bent shaped in matte pure Sn finish and hillock shape in matte Sn–Bi. The whisker growth in Sn–Bi finish was shorter than that in Sn finish. In FeNi42 leadframe, the 8.0–10.0 μm diameter and the 25.0–45.0 μm long whisker was grown under 300 cycles. In the 300 cycles of Cu leadframe, only the nodule-shaped grew on the surface, and in the 600 cycles, a 3.0–4.0 μm short whisker grew. After 600 cycles, the 0.25 μm thin Ni₃Sn₄ formed on the Sn-plated FeNi42. However, we observed the amount of 0.76–1.14 μm thick Cu₆Sn₅ and 0.27 μm thin Cu₃Sn intermetallics were observed between the Sn and Cu interfaces. Therefore, the main growth factor of a whisker is the intermetallic compound in the Cu leadframe, and the coefficient of thermal expansion mismatch in FeNi42.     

The impacts of high tensile stress CESL and geometry design on device performance and reliability for 90 nm SOI nMOSFETs

The thickness effects of high-tensile-stress contact etch stop layer (HS CESL) and impact of layout geometry (length of diffusion and gate width) on mobility enhancement of 100/(100) 90 nm SOI nMOSFETs were studied in detail. Additionally, we also inspected the low frequency characteristic with low-frequency noise investigation for FB-SOI nMOSFETs. Experimental results show that devices with 1100 Å HS CESL possess worse characteristics and hot-carrier-induced degradations than devices with 700 Å HS CESL due to serious stress-induced defects happen. The lower plateau of Lorentzian noise spectrum observed from input-referred voltage noise (S_vg) implies higher leakage current for the devices with 1100 Å HS CESL. On the other hand, we found that devices with narrow gate widths possess higher driving capacity because of larger fringing electric fields and higher compressive stress in direction perpendicular to the channel. Owing to the more serious impact of compressive stress in direction parallel to the channel, the device performance was degraded particularly for devices with shorter LOD.