催化裂化装置计算机模拟优化控制

本文简要介绍了催化裂化装置模拟优化控制系统软件的特点,硬件配置对比及现场应用情况。包括以催化裂化反应动力学研究中广泛应用的布兰丁(BLANDING)方程为理论基础催化裂化数学模型,以帕威尼—海姆布劳(Paviani—Himmelblau)的可变误差多面体法做为有约束的非线性最优化方法。介绍了由 INTEL 公司的80286 CPU、MOTOROLA 的68020 CPU(辅以 MC68881协处理器)及 PRO-LOG 公司的 STD 总线工业控制微机组成的多 CPU 组合系统做为数据采集、信息管理、模拟优化计算及闭环控制的硬件系统。     

The SUPRENUM vector floating-point unit

The paper describes the implementation of a high-performance 64-bit vector floating-point unit. This implementation consists of a microcontroller, coprocessor interface (for the 68020), DMA controller, various specialised memories, and the Weitek floating-point processors.     

Direct function calls in lisp

This paper compares implementation strategies for function calls in compiled Lisp. We discuss various ways of allowing compiled call instructions to branch immediately to a callee's code (direct calls), rather than to refer to a symbol that points to the function's definition (indirect calls). We examine the performance of direct and indirect function calls on the VAX and MC68020, and on a RISC architecture—the SPUR multiprocessor. For the SPUR architecture, single indirection slows applications by 3–4%, and double indirection slows applications by 6–8%. The performance benefits of direct function calls are considerably smaller for the VAX and MC68020 architectures. We discuss also the costs and complexities involved in implementing direct function calls.     

Direct function calls in lisp

This paper compares implementation strategies for function calls in compiled Lisp. We discuss various ways of allowing compiled call instructions to branch immediately to a callee's code (direct calls), rather than to refer to a symbol that points to the function's definition (indirect calls). We examine the performance of direct and indirect function calls on the VAX and MC68020, and on a RISC architecture—the SPUR multiprocessor. For the SPUR architecture, single indirection slows applications by 3–4%, and double indirection slows applications by 6–8%. The performance benefits of direct function calls are considerably smaller for the VAX and MC68020 architectures. We discuss also the costs and complexities involved in implementing direct function calls.This research was funded by DARPA contract number N00039-85-C-0269 as part of the SPUR research project.     

The 68040 processor. I. Design and implementation

The design of the 68040, a third-generation, full-32-b microprocessor in the Motorola 68000 family, is presented. The 68040 integrates over 1.2 million transistors on one chip and can execute the complete 68020 microprocessor and 68882 floating-point coprocessor instruction sets. Pipelined integer and floating-point execution units that operate concurrently with separate internal memory controllers and an autonomous bus controller contribute to its high performance level. Physical caches of 4 kB each for instruction and data reside on chip. Separate address-translation caches of 64 entries apiece operate in parallel with the instruction and data caches. This arrangement provides complete memory management in a virtual, demand-paged operating system. The design team explains its total approach and the workings of the integer and floating-point units     

A Benchmark Comparison of 32-bit Microprocessors

The benchmarking of four 32-bit microprocessors?the MC68020, the NS32032, the AT&T 32100, and the Intel 80386?revealed some specific reasons for the differences in performance that were observed.     

MUTABOR, a coprocessor supporting memory management in anobject-oriented architecture

The author describes MUTABOR, a micro-programmable coprocessor that works with a 68020 CPU to control and update a 4096-entry address translation cache that achieves an excellent hit rate. He defines the requirements for an object-oriented memory-management unit, and outlines the architecture of MUTABOR and the object-addressing mechanism. He also discusses the design decisions concerning the address translation cache, which were based on simulation results     

A code generation interface for ANSI C

1cc is a retargetable, production compiler for ANSI C; it has been ported to the VAX, Motorola 68020, SPARC, and MIPS R3000, and some versions have been in use for over a year and a half. It is smaller and faster than generally available alternatives, and its local code is comparable. This paper describes the interface between the target-independent front end and the target-dependent back ends. The interface consists of shared data structures, a few functions, and a dag language. While this approach couples the front and back ends tightly, it results in efficient, compact compilers. The interface is illustrated by detailing a code generator that emits naive VAX code.     

Simple register spilling in a retargetable compiler

This paper describes the management of register spills in a retargetable C compiler. Spills are rare, which means that testing is a bigger problem than performance. The trade-offs have been arranged so that the common case (no spills) generates respectable code quickly and the uncommon case (spills) is less efficient but as simple as possible. The technique has proven practical and is in production use on VAX, Motorola 68020, SPARC and MIPS machines.     

Autonomous mobile robot navigation and learning

Research focused on the development and experimental validation of intelligent control techniques for autonomous mobile robots able to plan and perform a variety of assigned tasks in unstructured environments is presented. In particular, an autonomous mobile robot, HERMIES-IIB intelligence experiment series, is described. It is a self-powered, wheel-driven platform containing an onboard 16-node Ncube hypercube parallel processor interfaced to effectors and sensors through a VME-based system containing a Motorola 68020 processor, a phased sonar array, dual manipulator arms, and multiple cameras. Research on navigation and learning is examined     

Self motion determination based on actuator velocity bounds for redundant manipulators

The movement of redundant manipulator joints that does not cause any end-effector motion is referred to as its self motion. Control schemes for redundant manipulators utilize its self motion to optimize a performance criterion. Thus, commanded joint motion at each sampling step is the sum of the minimum joint motion required for the desired end-effector motion and the self motion. However, the amount of self motion is limited by the bounds on actuator velocities, which are limited by the actuator torque bounds. A scheme is presented to determine the magnitude of self motion, the direction of which is determined by a gradient projection scheme. Implementation of this scheme on a Motorola 68020 VMEbus-based controller of a seven-degree-of-freedom manipulator is described.     

Microprocessor memory management units

This tutorial describes the current crop of commercial memory management units (MMUs) for 32-bit microprocessors. The discussion includes both complex- and reduced-instruction-set computers (CISCs and RISCs). The rationale, principles, and issues related to hardware support for memory management and virtual memory are reviewed. The design and features of high-end microprocessor MMUs are reviewed and compared with respect to a common set of criteria. Special attention is paid to Unix requirements and multiprocessor, multiple MMU considerations. The MMUs covered are Intel 80386, i486, and i860; Motorola's 68851 (MMU for the 68020), 68030, 68040, and 88200 (MMU for the 88000 series); the Fujitsu MB86920 (Sparc MMU); and the MIPS R2000/R3000     

A comparison of two paradigms for distributed shared memory

Two paradigms for distributed shared memory on loosely-coupled computing systems are compared: the shared data-object model as used in Orca, a programming language specially designed for loosely-coupled computing systems, and the shared virtual memory model. For both paradigms two systems are described, one using only point-to-point messages, the other using broadcasting as well. The two paradigms and their implementations are described briefly. Their performances are compared on four applications: the travelling-salesman problem, alpha-beta search, matrix multiplication and the all-pairs shortest-paths problem. Measurements were obtained on a system consisting of 10 MC68020 processors connected by an Ethernet. For comparison purposes, the applications have also been run on a system with physical shared memory. In addition, the paper gives measurements for the first two applications above when remote procedure call is used as the communication mechanism. The measurements show that both paradigms can be used efficiently for programming large-grain parallel applications, with significant speed-ups. The structured shared data-object model achieves the highest speed-ups and is easiest to program and to debug.     

Mapping extended Kalman filters onto linear arrays

Techniques for mapping extended Kalman filters onto linear arrays of programmable cells designed for real-time applications are described. First, a general method for mapping a standard (nonsquare root) Kalman filter, where the columns of the covariance matrix are updated in parallel, is introduced. Next, a general method for mapping a factorized (square root) filter, where fast Givens rotations are used to triangularize the prematrix and where rotations of the rows of the prematrix are performed in parallel, is introduced. These mappings are used to implement an extended Kalman filter commonly used in target tracking applications on the Warp computer. The Warp is a commercially available linear array of 10 or more programmable cells connected to an MC68020-based workstation. The Warp implementation of the standard Kalman filter running on 8 Warp cells achieves a measured speedup of 7 over the same filter running on a single cell. The Warp implementation of the factorized filter running on 10 Warp cells achieves a measured speedup of 2     

A set of BASIC programs to evaluate relationships among protein sequences by optimum alignment and distance matrix analysis.

These six programs evaluate relationships among a number (> 2) of protein (or DNA) sequences. Program 1 automatically computes optimum alignments and total distances for all pairwise sequence combinations over any user desired range of the two gap penalties. Programs 2, 3 and 4 generate a square, symmetrical distance matrix, which can be exported for cluster analysis, or further analysed with programs 5 and 6 to give specific distances between sequences and extract sequence relationships. Data and results are exchanged among these programs, which are written in BASIC and compiled to run on Macintosh (68020/030/040) type machines with coprocessor and at least one MB of RAM. BASIC graphics commands or those for the Macintosh interface are avoided to facilitate use on other machines. Two groups of sequences are used to demonstrate (a) alignment, inter sequence distance calculation and dendrogram generation and (b) specific distance calculation and its usage in detecting sub groups of related sequences in dendrograms.     

Stereo vision for planetary rovers: Stochastic modeling to near real-time implementation

NASA scenarios for lunar and planetary missions include robotic vehicles that function in both teleoperated and semi-autonomous modes. Under teleoperation, on-board stereo cameras may provide 3-D scene information to human operators via stereographic displays; likewise, under semi-autonomy, machine stereo vision may provide 3-D information for obstacle avoidance. In the past, the slow speed of machine stereo vision systems has posed a hurdle to the semi-autonomous scenario; however, recent work at JPL and other laboratories has produced stereo systems with high reliability and near real-time performance for low-resolution image pairs. In particular, JPL has taken a significant step by achieving the first autonomous, cross-country robotic traverses (of up to 100 meters) to use stereo vision, with all computing on-board the vehicle. Here, we describe the stereo vision system, including the underlying statistical model and the details of the implementation. The statistical and algorithmic aspects employ random field models of the disparity map, Bayesian formulations of single-scale matching, and area-based image comparisons. The implementation builds bandpass image pyramids and produces disparity maps from the 60×64 level of the pyramids at rates of up to two seconds per image pair. All vision processing is done in one 68020 augmented with Datacube image processing boards. We argue that the overall approach provides a unifying paradigm for practical, domain-independent stereo ranging. We close with a discussion of practical and theoretical issues involved in evaluating and extending the performance of the stereo system.     

基于云数据中心的多源异构数据治理技术研究

目前常规的多源异构数据治理方法主要通过对数据属性进行判断,从而实现分区域数据清洗,由于缺乏对非线性数据的分析,导致治理性能不佳;对此,提出基于云数据中心的多源异构数据治理技术;采用关系型数据库中的ETL功能对数据进行清洗,对数据转换模式以及数据清洗规则进行定义;引入互信息系数对数据相关程度进行判定,并进行非线性数据相关性分析;以云数据中心作为载体,对多源异构数据治理体系进行构建;在实验中,对提出的数据治理技术进行了治理性能的检验;最终的实验结果表明,提出的数据治理技术具备较高的查准率,对云数据中心多源异构数据具备较为理想的数据治理效果。     

基于OEM模型的半结构化数据的模式发现

随着Web数据和数据集成技术的飞速发展,半结构化数据越来越引起人们的重视。半结构化数据是指那些具有隐含结构或结构不严谨的自描述数据。它不同于传统数据中的模式,它是先有数据后有模式,而且半结构化数据的模式是用于描述数据的结构信息而不是对数据结构进行强制约束。为此,半结构化数据的模式发现就成为知识发现的首要步骤。采用了层次数据的概念,提出了分层事务数据库和“累加变换”的计数原则,并据此提出了基于SHDP-tree树结构的SHDP-mine算法和挖掘出半结构、层次数据的基本模式。最后从理论和实验分析和验证了它的有效性和高效性。     

被动声传感器网络数据仿真平台研究

目标的声传感器数据是被动声传感器网络算法研究的前提和依据,其可靠性和真实性是非常重要的,但是如果通过现场实测获得,往往耗资巨大,设计一种逼近实际的被动声传感器网络数据仿真平台越来越显示出其必要性。给出了一种被动声传感器网络数据仿真平台的实现方法,通过该平台,可以方便灵活地模拟低空和超低空目标的各种机动飞行,并产生仿真数据。实验将平台产生的仿真数据与实测数据进行了对比,结果表明该数据仿真平台符合应用要求。     

一种直播服务器的设计与实现

提出一种直播服务器设计方案,媒体接收端根据节目链接访问媒体源,获取媒体数据流;媒体数据缓冲区是一个双循环缓冲区,循环缓存媒体接收端获取的媒体数据流;媒体服务器发送端根据媒体数据缓冲区建立子会话,生成访问该节目的直播服务器链接,终端通过链接访问直播服务器,直播服务器从媒体数据缓冲区中循环读取媒体数据发送给终端。设计方案具有适合多种网络、架设过程简单、可多台服务器级联等特点,并且成本低廉,可扩展性强。