Board level solder joint reliability modeling and testing of TFBGA packages for telecommunication applications

For thin-profile fine-pitch BGA (TFBGA) packages, board level solder joint reliability during the thermal cycling test is a critical issue. In this paper, both global and local parametric 3D FEA fatigue models are established for TFBGA on board with considerations of detailed pad design, realistic shape of solder joint, and nonlinear material properties. They have the capability to predict the fatigue life of solder joint during the thermal cycling test within ±13% error. The fatigue model applied is based on a modified Darveaux’s approach with nonlinear viscoplastic analysis of solder joints. A solder joint damage model is used to establish a connection between the strain energy density (SED) per cycle obtained from the FEA model and the actual characteristic life during the thermal cycling test. For the test vehicles studied, the maximum SED is observed at the top corner of outermost diagonal solder ball. The modeling predicted fatigue life is first correlated to the thermal cycling test results using modified correlation constants, curve-fitted from in-house BGA thermal cycling test data. Subsequently, design analysis is performed to study the effects of 14 key package dimensions, material properties, and thermal cycling test condition. In general, smaller die size, higher solder ball standoff, smaller maximum solder ball diameter, bigger solder mask opening, thinner board, higher mold compound CTE, smaller thermal cycling temperature range, and depopulated array type of ball layout pattern contribute to longer fatigue life.     

Comprehensive board-level solder joint reliability modeling and testing of QFN and PowerQFN packages

For quad flat non-lead (QFN) packages, board-level solder joint reliability during thermal cycling test is a critical issue. In this paper, a parametric 3D FEA sliced model is established for QFN on board with considerations of detailed pad design, realistic shape of solder joint and solder fillet, and non-linear material properties. It has the capability to predict the fatigue life of solder joint during thermal cycling test within ±34% error. The fatigue model applied is based on a modified Darveaux’s approach with non-linear viscoplastic analysis of solder joints. A solder joint damage model is used to establish a connection between the strain energy density (SED) per cycle obtained from the FEA model and the actual characteristic life during thermal cycling test. For the test vehicles studied, the maximum SED is observed mostly at the top corner of peripheral solder joint. The modeling predicted fatigue life is first correlated to thermal cycling test results using modified correlation constants, curve-fitted from in-house QFN thermal cycling test data. Subsequently, design analysis is performed to study the effects of 17 key package dimensions, material properties, and thermal cycling test condition. Generally, smaller package size, smaller die size, bigger pad size, thinner PCB, higher mold compound CTE, higher solder standoff, and extra soldering at the center pad help to enhance the fatigue life. Comparisons are made with thermal cycling test results to confirm the relative trends of certain effects. Another enhanced QFN design with better solder joint reliability, PowerQFN, is also studied and compared with QFN of the same package size.     

CSP封装Sn-3.5Ag焊点的热疲劳寿命预测

对芯片尺寸封装(CSP)中Sn-3.5Ag无铅焊点在热循环加速载荷下的热疲劳寿命进行了预测.首先利用ANSYS软件建立CSP封装的三维有限元对称模型,运用Anand本构模型描述Sn-3.5Ag无铅焊点的粘塑性材料特性;通过有限元模拟的方法分析了封装结构在热循环载荷下的变形及焊点的应力应变行为,并结合Darveaux疲劳寿命模型预测了无铅焊点的热疲劳寿命.     

倒装焊SnPb焊点热循环失效和底充胶的影响

采用实验方法,确定了倒装焊SnPb焊点的热循环寿命．采用粘塑性和粘弹性材料模式描述了SnPb焊料和底充胶的力学行为,用有限元方法模拟了SnPb焊点在热循环条件下的应力应变过程．基于计算的塑性应变范围和实验的热循环寿命,确定了倒装焊SnPb焊点热循环失效Coffin-Manson经验方程的材料参数．研究表明,有底充胶倒装焊SnPb焊点的塑性应变范围比无底充胶时明显减小,热循环寿命可提高约20倍,充胶后的焊点高度对可靠性的影响变得不明显．     

Solder joint reliability of a low cost chip size package—NuCSP

The accumulated elasto-plastic strain range and the time-dependent elasto-plastic-creep deformation of a wire bondable land grid array (LGA) chip size package (NuCSP) assembly’s solder joint under thermal cycling condition are presented. The solder is assumed to be a temperature-dependent material. The thermal fatigue life of the solder joint is estimated based on two methods, namely, the accumulated plastic strain range and Coffin–Manson equation, and viscoplastic strain energy density and an empirical equation based on the assumption of linear fatigue crack growth.     

Board level solder joint reliability analysis of stacked die mixed flip-chip and wirebond BGA

Stacked die BGA has recently gained popularity in telecommunication applications. However, its board level solder joint reliability during the thermal cycling test is not as well-studied as common single die BGA. In this paper, solder joint fatigue of lead-free stacked die BGA with mixed flip-chip (FC) and wirebond (WB) interconnect is analyzed in detail. 3D fatigue model is established for stacked die BGA with considerations of detailed pad design, realistic shape of solder ball, and non-linear material properties. The fatigue model applied is based on a modified Darveaux’s approach with non-linear viscoplastic analysis of solder joints. Based on the FC–WB stack die configuration, the critical solder ball is observed located between the top and bottom dice corner, and failure interface is along the top solder/pad interface. The modeling predicted fatigue life is first correlated to the thermal cycling test results using modified correlation constants, curve-fitted from in-house lead-free TFBGA46 (thin-profile fine-pitch BGA) thermal cycling test data. Subsequently, design analyzes are performed to study the effects of 20 key design variations in package dimensions, material properties, and thermal cycling test conditions. In general, thinner PCB and mold compound, thicker substrate, larger top or bottom dice sizes, thicker top die, higher solder ball standoff, larger solder mask opening, smaller PCB pad size, smaller thermal cycling temperature range, longer ramp time, and shorter dwell time contribute to longer fatigue life. SnAgCu is a common lead-free solder, and it has much better board level reliability performance than eutectic solder based on modeling results, especially low stress packages.     

Solder joint crack propagation analysis of wafer-level chip scalepackage on printed circuit board assemblies

The solder-joint reliability of a low-cost wafer-level chip scale package (WLCSP) on printed circuit board (PCB) under thermal fatigue is studied. The solder joints are subjected to thermal cycling and their crack lengths at different thermal cycles are measured. Also, the stress intensity factors at the crack tip of different crack lengths in the corner solder joint are determined by fracture mechanics with finite element method. Furthermore, an empirical equation for predicting the thermal-fatigue life of flip chip solder joints is proposed     

Board level solder joint reliability analysis of a fine pitch Cu post type wafer level package (WLP)

Wafer level packaging (WLP) has many advantages, such as ease of fabrication and reduced fabrication cost. However, solder joint reliability of traditional WLPs is the weakest point of the technology. In this paper, a 0.4 mm pitch Cu post type WLP has been developed for mobile computing application. The Cu post type WLP has 440 I/Os and 12 × 12 mm die size. The initial design WLP has been fabricated and subjected to a thermal cycling (TC) testing. The failure life of the original WLP under TC was 296 cycles. This paper also presents a nonlinear finite element analysis of the board level solder joint reliability and methods for enhancement of the WLP. A viscoplastic constitutive relation is adopted for the solder joints to account for its time and temperature dependence in TC. The fatigue life of the solder joint is estimated by the modified Coffin–Manson equation. The two coefficients in the modified Coffin–Manson equation are also determined. A series of parametric studies are performed by changing the passivation (PI) thickness, redistribution layer (RDL) thickness, polymer height (Cu post height accordingly varies), die thickness, PCB thickness, and PCB CTE. The results obtained from the modeling are useful to formulate design guidelines for board level reliability enhancement of the WLP.     

CQFP器件板级温循可靠性的设计与仿真

温度循环是考核封装产品板级可靠性的重要试验之一。陶瓷四边引脚扁平封装(CQFP)适用于表面贴装,由于陶瓷材料与PCB热膨胀系数的差异,温循过程中引线互联部分产生周期性的应力应变,当陶瓷壳体面积较大时,焊点易出现疲劳失效现象。CQFP引线成形方式分顶部成形和底部成形两类。针对CQFP引线底部成形产品在板级温循中出现的焊接层开裂现象,采用有限元方法对焊接层的疲劳寿命进行了预测分析。采用二次成形方法对引线进行再次成形以缓解和释放热失配产生的应力。仿真和试验结果显示,引线二次成形有利于提高焊接层的温循疲劳寿命。与引线底部成形相比,当引线采用顶部成形时,焊接层的温循疲劳寿命显著提高。     

Board level solder joint reliability analysis and optimization of pyramidal stacked die BGA packages

Due to requirements of cost-saving and miniaturization, stacked die BGA has recently gained popularity in many applications. However, its board level solder joint reliability during the thermal cycling test is not as well-studied as common single die BGA. In this paper, solder joint fatigue of wirebond stacked die BGA is analyzed in detail. 3D fatigue model is established for stacked die BGA with considerations of detailed pad design, realistic shape of solder ball, and non-linear material properties. The fatigue model applied is based on a modified Darveaux's approach with non-linear viscoplastic analysis of solder joints. The critical solder ball is observed located between the top and bottom dice corner, and failure interface is along the top solder/pad interface. The modeling predicted fatigue life is first correlated to the thermal cycling test results using modified correlation constants, curve-fitted from in-house TFBGA (thin-profile fine-pitch BGA) thermal cycling test data. Subsequently, design analyses are performed to study the effects of 16 key design variations in package dimensions, material properties, and thermal cycling test conditions. In general, smaller top and bottom dice sizes, thicker top or bottom die, thinner PCB, thicker substrate, higher solder ball standoff, larger solder mask opening size, smaller maximum ball diameter, smaller PCB pad size, smaller thermal cycling temperature range, longer ramp time, and shorter dwell time contribute to longer fatigue life. The effect of number of layers of stacked-die is also investigated. Finally, design optimization is performed based on selected critical design variables.     

Development of a low-cycle fatigue life curve for 80In15Pb5Ag

The purpose of this study is to develop a methodology to predict the low-cycle (large strain—from 0.1 to 0.35 strain) fatigue life of solders subject to thermal cycling. Solders are commonly used in electronic assemblies. Using thermal fatigue data measured for 80In15Pb5Ag, a low-cycle fatigue curve for 80In15Pb5Ag solder subject to thermal cycling was developed. Specifically a Coffin-Manson relationship was derived for the solder, with a high degree of correlation (see Table I), for four different failure criteria, defined in the body of the paper. This relationship, together with calculated strains in the solder joint, allows the low-cycle fatigue life of the solder joint to be predicted.     

Quantitative reliability analysis of flip-chip packages under thermal-cyclic loading and in consideration of parameter uncertainties

To study the quantitative reliability of electronic packages, a finite element analysis with the assumption that certain geometric parameters are random variables is carried out for a flip-chip package. The equivalent plastic strain range of the package subject to thermal-cyclic loading is obtained, and the fatigue life of the package is determined based on a modified Coffin-Manson equation. Both quantities obtained are random variables owing to the randomness or uncertainties of geometric parameters. It is found that, among different geometric parameters, the size of the solder bump affects the random fatigue life of the package the most. In the second phase of the study, a modified Coffin-Manson equation with random nature is considered. This can be achieved by assuming some parameters in the equation to be random variables. It also reflects a certain kind of uncertainty of the material property. Through mathematical derivation and numerical illustration, it is shown that the predicted fatigue lives may have different mean values and different variations, and the difference may be significant. The present study indicates that both random geometric configuration and random life prediction rule may cause the fatigue life of the package to have scattered distribution as those observed from experiments.     

底部填充物对CSP-LED芯片抗跌落性能研究

为了提高芯片级封装发光二极管(CSP-LED)焊点疲劳寿命,利用有限元仿真软件ABAQUS模拟计算了CSP-LED芯片在跌落冲击载荷下焊点的塑性应变,并研究了裂纹拓展趋势。以焊点失效前跌落次数为指标,利用Coffin-Manson经验公式计算焊点寿命,研究了底部填充物对CSP-LED芯片在不同冲击载荷下焊点寿命的影响。结果表明,随着冲击载荷增大,焊点疲劳寿命减少,使用填充物能使芯片焊点寿命提高4~6倍,其影响通过跌落实验和仿真结果的对比得到了验证。     

Thermal cycling analysis of flip-chip solder joint reliability

The reliability concern in flip-chip-on-board (FCOB) technology is the high thermal mismatch deformation between the silicon die and the printed circuit board that results in large solder joint stresses and strains causing fatigue failure. Accelerated thermal cycling (ATC) test is one of the reliability tests performed to evaluate the fatigue strength of the solder interconnects. Finite element analysis (FEA) was employed to simulate thermal cycling loading for solder joint reliability in electronic assemblies. This study investigates different methods of implementing thermal cycling analysis, namely using the "dwell creep" and "full creep" methods based on a phenomenological approach to modeling time independent plastic and time dependent creep deformations. There are significant differences between the "dwell creep" and "full creep" analysis results for the flip chip solder joint strain responses and the predicted fatigue life. Comparison was made with a rate dependent viscoplastic analysis approach. Investigations on thermal cycling analysis of the temperature range, (ΔT) effects on the predicted fatigue lives of solder joints are reported     

Thermo-mechanical finite element analysis in a multichip build up substrate based package design

This paper presents a thermo-mechanical analysis of a multichip module (MCM) package design, with emphasis on the package warpage, thermally induced stress and the second level solder joint reliability. The MCM package contains four flip chips which are mounted on a build up substrate. First, the effect of the positioning of four silicon dice within the MCM package on the warpage of the package is studied. Second, the effect of package dimensions (the heat spreader thickness, the structural adhesive thickness and the substrate thickness) on the maximum residual stress as well as the warpage of the package is performed. Finally, this paper presents a 3D sliced model for solder joint reliability of the MCM assembly. A creep constitutive relation is adopted for the 63Sn/37Pb solder to account for its time and temperature dependence in thermal cycling. The fatigue life of solder joint is estimated by the Darveaux's approach. A series of parametric study is performed by changing the package dimensions. The results show that the largest die tends to experience highest stresses at its corner and has more influence on the warpage of the package than smaller dice. The results also show the most sensitivity factors that affect the package warpage and the second level solder joint reliability are the substrate thickness and the heat spreader thickness. The structural adhesive thickness has no major effect on the package warpage, the maximum von Mises stress of the package and the second level solder joint reliability.     

Thermal cycling aging effects on microstructural and mechanicalproperties of a single PBGA solder joint specimen

This paper reports on an experimental study on how thermal cycling aging exposure changes the solder joint microstructure, intermetallic layer thickness and the residual shear strength and fatigue life in a single plastic ball grid array (PBGA) solder joint specimen. The single BGA solder joint specimen was specially designed to evaluate the microstructure and mechanical properties of three different batches of solder joint after subjected to 0, 500, 1000, and 2000 cycles of thermal cycling aging (-40°C to 125°C). It is important to relate the effects of thermal cycling aging on the changes of the microstructural and intermetallic layer thickness to the residual shear strength and fatigue life of solder joints subjected to thermal cycling aging exposure. The results of this study shows that the microstructural and intermetallic development due to thermal cycling aging has a major impact on the residual mechanical and fatigue strength of the solder joint. It was noted that the solder joint shear strength and residual fatigue life degrades with exposure to thermal cycling aging     

Design and analysis of wafer-level CSP with a double-pad structure

Wafer level chip scale packaging (WLCSP) is very promising for the miniature of packaging size, the reduction of manufacturing cost, and the enhancement of the package's performance. However, the long-term board level reliability of integrated circuit (IC) devices using wafer level packaging with large distances from neutral point (DNP) is still not fully solved. This research proposes a novel, alternative WLCSP design for facilitating higher board level reliability. The main feature of the novel WLCSP is basically in its double-pad structure (DPS) design in the interface between solder joints and silicon chip. To characterize the solder joint reliability of the DPS-WLCSP, a three-dimensional (3-D) nonlinear finite element (FE) modeling technique is employed. Based on the FE modeling, the numerical accelerated thermal cycling (ATC) test is performed under the JEDEC temperature cycling specification. The validity of the proposed FE modeling is verified by using an optical measurement method Twyman-Green interferometer. By the derived incremental equivalent plastic strain, the cumulative cycles to failure in solder joints associated with these four WLCSP are assessed based on a modified Coffin-Manson relationship. The modeled fatigue life is compared against the experimental results that adopt a two-parameter Weibull distribution to characterize cycles-to-failure distribution. For comparison, the investigation also involves several existing types of WLCSP, including the conventional (C-WLCSP), the copper post (CP-WLCSP), and the polymer post (PP-WLCSP), and solder joint reliability performance among these WLCSP packages is extensively compared. The results demonstrate that the DPS-WLCSP design not only has potential for enhancing the corresponding solder joint reliability but is also particularly effective in manufacturing process and cost. And finally, some reliability-enhanced design guidelines are provided through parametric design of the DPS.     

Mechanical, thermal, and electrical analysis of a compliant interconnect

Ball grid array (BGA) package styles use solder balls as electrical interconnects between packages and application boards. Solder balls are rigid and tend to fracture under thermal fatigue and/or shock loading. Metalized polymer spheres (MPS) offer a more compliant interconnect, compared to solder balls, thereby increasing the thermal cycling fatigue life. A reduction in thermal and electrical performance may be expected for MPS interconnects as a result of its higher thermal and electrical resistances. A 5% and an 8% increase in MPS thermal resistance was measured for a carrier array ball grid array (CABGA) package and a plastic ball grid array (PBGA) package, respectively, compared to eutectic solder balls. However, this small reduction was offset by large gains in the solder joint life. A 1.6 times increase in the mean thermal fatigue life was measured for a CABGA using MPS interconnects compared to eutectic solder balls. A first-order model showed that eutectic solder balls provide greater process margins, compared to MPS interconnects, due to the ball collapse during reflow.     

Finite element modeling of thermal fatigue and damage of solder joints in a ceramic ball grid array package

A nonlinear finite element model is presented for analyzing the cyclic and thermal fatigue loading and for viscoplastic damage characterization of the lead-tin (Pb-Sn) solder joints in a ceramic ball grid array (CBGA) surface mount package. An approach using a Δ ∈ _eq ⁱⁿ -modified Coffin-Manson equation is proposed to estimate the fatigue life of the solder joints. The Δ ∈ _eq ⁱⁿ represents a saturated equivalent inelastic strain range as determined by the finite element model. The present study shows that the predictied fatigue life and the associated damage mechanism of the solder joint agree reasonably well with the test data for the 18,25, and 32 mm CBGA packages run at a cyclic temperature load of 0°C/100°C with a frequency of 1.5 cycles per hour. Analysis also shows that a preferred failure site is expected to occur in and around the Pb37-Sn63 solder attachment of the solder joint. A time-dependent (creep induced) damage mechanism is found to be more pronounced than the time-independent (plastic deformation) mechanism.     

The effects of underfill and its material models onthermomechanical behaviors of a flip chip package

In this paper, the effects of underfill on thermomechanical behavior of two types of flip chip packages with different bumping size and stand-off height were investigated under thermal cycling both experimentally and two-dimensional (2-D) finite element simulation. The materials inelasticity, i.e., viscoelasticity of underfill U8437-3 and viscoplasticity of 60 Sn40 Pb solder, were considered in the simulations. The results show that the use of underfill encapsulant increases tremendously (~20 times) the thermal fatigue lifetime of SnPb solder joint, weakens the effects of stand-off height on the reliability, and changes the deformation mode of the package. It was found that the thermal fatigue crack occurs in the region with maximum plastic strain range, and the Coffin-Manson type equation could then be used for both packages with and without underfill. Solder joint crack initiation occurred before delamination when using underfill with good adhesion (75 MPa) and the underfill delamination may not be a dominant failure mode in the present study. The interfacial stresses at the underfill/chip interface were calculated to analyze delamination sites, which agree with the results from acoustic image. Moreover, the effects of material models of underfill, i.e., constant elasticity (EC) and temperature dependent elasticity (ET) as well as the viscoelasticity (VE), on the thermomechanical behaviors of flip chip package were also studied in the simulation. The VE model gives comparatively large plastic strain range and large displacements in the shear direction, as well as decreased solders joint lifetime. The ET model gives similar results as the VE model and could be used instead of VE in simulations for the purpose of simplicity