A Self-Mixing NMOS Channel-Detector Optimized for mm-Wave and THZ Signals

A self-mixing terahertz signal detector combined with a low noise amplifier and a properly balanced - folded dipole or slot antenna for concentrating millimeter wave signals to NMOS detectors is described. The detector was optimized to 300 GHz signals. The noise equivalent power (NEP) was estimated to 320 pW/√Hz while the total output referred noise of 2.1 μV/(Hz)^1/2 was measured at amplifier gain of 46 dB. This was achieved by using NMOS mixer devices optimized for resistive mixing that operate in a linear region of operation where the channel voltage is set close to zero by means of regulating the virtual ground level. The NMOS device, which is positioned at the antenna connections, has a minimum channel length that permits a far more precise calculation of the coupling devices. A position like termination of the two symmetrical detector devices was distributed between an antenna area and the amplification stage. The detectors were fully integrated using the 250 nm CMOS technology. Good matching was found between mathematically analyzed and simulated noise performances and prototypes measurements, where comparable measurements were performed on a THz array which consists of four pixels with folded dipole antennas or those with slot type antennas.     

多晶硅双栅全耗尽SOI CMOS器件与电路

对多晶硅双栅全耗尽SO I CM O S工艺进行了研究,开发出了1.2μm多晶硅双栅全耗尽SO I CM O S器件及电路工艺,获得了性能良好的器件和电路。NM O S和PM O S的阈值电压绝对值比较接近,且关态漏电流很小,NM O S和PM O S的驱动电流分别为275μA/μm和135μA/μm,NM O S和PM O S的峰值跨导分别为136.85 m S/mm和81.7 m S/mm。在工作电压为3 V时,1.2μm栅长的101级环振的单级延迟仅为66 ps。     

A high-performance all-enhancement NMOS operational amplifier

An NMOS operational amplifier has been designed and fabricated using only enhancement mode MOSFETs in a circuit that employs a novel feedforward compensation scheme. Specifications achieved include high open loop gain (2200), low-power (15 mW or less depending on the load), fast settling time (0.1 percent settling time in 3 /spl mu/s for a 4 V input step and a 10 pF load), and small area. While this amplifier uses only a small number of transistors, its performance is comparable to that of recent depletion load amplifiers. Fewer critical steps are needed to fabricate this amplifier, making it attractive for large analog/digital LSI circuits.     

A 1.5-V high drive capability CMOS op-amp

A novel CMOS operational amplifier with a 1.5 V power supply is presented. It is based on a folded-mirror transconductance amplifier and a high-efficiency output stage. The amplifier achieves an open-loop gain and a gain-bandwidth product higher than 65 dB and 1 MHz, respectively. In addition, a 1 V peak-to-peak output voltage into a 500 Ω and 50 pF output load is provided with a total harmonic distortion of -77 dB. This performance was achieved using maximum aspect ratios of 120/1.2 and 360/1.2 for the NMOS and PMOS transistors, respectively, and a quiescent current as low as 60 μA for the driver transistors. The amplifier was implemented in a standard 1.2 μm CMOS process with threshold voltages around 0.8 V. It dissipates less than 300 μW     

A high-speed, small-area, threshold-voltage-mismatch compensationsense amplifier for gigabit-scale DRAM arrays

A high-speed small-area DRAM sense amplifier with a threshold-voltage (V_T) mismatch compensation function is proposed. This sense amplifier features a novel hierarchical data-line architecture with a direct sensing scheme that uses only NMOS transistors in the array, and simple V_T mismatch compensation circuitry using a pair of NMOS switching transistors. The layout area of the sense amplifier is reduced to 70% of that of a conventional CMOS common I/O sense amplifier due to the removal of PMOS transistors from the array. The readout time is improved to 35% of that of a conventional CMOS sense amplifier because of direct sensing and a 1/10 reduction in V_T mismatch. This sense amplifier eliminates the sensitivity degradation and the area overhead increase that are expected in gigabit-scale DRAM arrays     

A New Method Modifying Single Miller Feedforward Frequency Compensation to Drive Large Capacitive Loads: Putting an Attenuator in the Path

A new method to compensate three-stage amplifier to drive large capacitive loads is proposed in this paper. Gain Bandwidth Product is increased due to use an attenuator in the path of miller compensation capacitor. Analysis demonstrates that the gain bandwidth product will be improved significantly without using large compensation capacitor. Using a feedforward path is deployed to control a left half plane zero which is able to cancel out first non-dominant pole. A three stage amplifier is simulated in a 0.18 μm CMOS technology. The purpose of the design is to compensate three-stage amplifier loading 1000 pF capacitive load. The simulated amplifier with a 1000 pF capacitive load is performed in 3.3 MHz gain bandwidth product, and phase margin of 50. The compensation capacitor is reduced extremely compared to conventional nested miller compensation methods. Since transconductance of each stage is not distinct, and it is close to one another; as a result, this method is suitable low power design methodology.     

CMOS RF amplifier and mixer circuits utilizing complementary Characteristics of parallel combined NMOS and PMOS devices

Design and chip fabrication results for complementary RF circuit topologies that utilize the complementary RF characteristics of both NMOS and PMOS field-effect-transistor devices combined in parallel way are reported, which can inherently provide single-ended differential signal-processing capability, requiring neither baluns, nor differential signal generating/combining circuits. The proposed complementary CMOS parallel push-pull (CCPP) amplifier gives an order of magnitude improvement in IP/sub 2/ than an NMOS common-source amplifier and single-balanced CCPP resistive mixer, which functions effectively as a double-balanced one, provides more than an order of magnitude better linearity in IP/sub 2/, and similar order of magnitude better local oscillator (LO)-IF and LO-RF isolations than NMOS counterparts.     

A Multicell Linear Power Amplifier for Driving Piezoelectric Loads

A multicell amplifier is developed by connecting floating signal modules in series to drive piezoelectric devices. The amplifier generates a high voltage gain by summing the individual module gains. The bandwidth equals that of a single module. The multicell amplifier provides a means of achieving high power and can divide the total power dissipation among the modules, because each module delivers the same output voltage and current. A prototype circuit that consists of six floating signal modules exhibits precise linear operation over a wide range of input frequencies and capacitive loads. The circuit provides a plusmn 200-V output swing with a corner frequency of around 100 kHz at a driving capacitive load of 0.1 muF. The slew rate is as high as 115 V/mus, and the maximum output current is plusmn2.6 A. The practicality and performance of the presented modular implementation concepts were verified by the close match between the simulated and experimental results.     

A 35 ns 16K NMOS static RAM

An NMOS 16K/spl times/1 bit fully static MOS RAM with 35 ns access time has been successfully developed. High speed access time was achieved by the combination of an NMOS process with the 2.2 /spl mu/m gate length transistor, high speed sense amplifier, and reduction on delay time at the crossunder. The improvements of row and column decoder circuits result in the low active and standby power dissipation of 275 mW and 22.5 mW, respectively. The soft error rate of the poly load cell was minimized by reducing the collection efficiency of alpha-particle induced electrons.     

A fully on-chip fast-transient NMOS low dropout voltage regulator with quasi floating gate pass element

This paper presents a fully on-chip NMOS low-dropout regulator (LDO) for portable applications with quasi floating gate pass element and fast transient response. The quasi floating gate structure makes the gate of the NMOS transistor only periodically charged or refreshed by the charge pump, which allows the charge pump to be a small economical circuit with small silicon area. In addition, a variable reference circuit is introduced enlarging the dynamic range of error amplifier during load transient. The proposed LDO has been implemented in a 0.35 μm BCD process. From experimental results, the regulator can operate with a minimum dropout voltage of 250 mV at a maximum 1 A load and I_Q of 395 μA. Under full-range load current step, the voltage undershoot and overshoot of the proposed LDO are reduced to 50 and 26 mV, respectively.     

A low-temperature NMOS technology with Cesium-implanted load devices

A 2-µm enhancement/depletion-type NMOS technology designed for operation at liquid-nitrogen temperature is described. A cesium oxide implant has been used to realize load devices that are not degraded by the freeze out of mobile carriers that occurs in the bulk of conventional depletion-mode transistors at low temperature, Unloaded ring oscillators, fabricated using this technology, have an average propagation delay of 360 ps/stage and a power dissipation of 190 µW/stage with a 2.5-V power supply at 77 K; this represents an improvement in speed of a factor of 2.5 over a conventional NMOS technology operating at room temperature. Simulations predict a further decrease in delay to 200 ps/stage for a 2-/µm process may be achieved through optimization of the Cs-implanted load device without compromising noise margins.     

A Mixed-Signal Approach Towards Linear and Efficient N-Way Doherty Amplifiers

A mixed-signal approach for the design and testing of high-performance N-way Doherty amplifiers is introduced. In support of this, an analysis of N-way power-combining networks is presented-in particular, their optimum design-by examining the relationship between the drive conditions of the active devices and input power. This analysis makes no prior assumption on the network topology and facilitates free-to-choose levels for the high-efficiency power back-off points. By comparing the results of this analysis with prior work, it is shown that very specific drive conditions apply to traditional three-way Doherty amplifier implementations to obtain simultaneously high-efficiency and high-linearity operation. To support these conclusions, a 15-W three-way Doherty amplifier was constructed using Philips GEN4 LDMOS devices featuring three separate inputs to independently drive the main and peaking devices. By testing this three-way amplifier with a custom-built measurement setup, capable of providing multiple digitally controlled coherent RF input signals with high spectral purity, a unique flexible amplifier concept is created resulting in a record-high efficiency for LDMOS-based Doherty amplifiers over a 12-dB back-off power range     

A novel dual p-/p+ poly gate CMOS VLSItechnology

A CMOS VLSI technology using p^- and p⁺ poly gates for NMOS and PMOS devices is presented. Due to the midgap work function of the p^- poly gate, the NMOS native threshold voltage is 0.7 V and, therefore, no additional threshold adjust implantation is required. The NMOS transistor is a surface-channel device with improved field-effect mobility and lower body effect due to the reduction in the channel doping concentration. In addition, the p ^- poly gate is shown to be compatible with p⁺ poly-gated surface-channel PMOS devices     

A wide dynamic range analog predistortion-type linearizer using self-cancellation scheme

A new radio frequency linearized power amplifier (LPA) system for wideband-code-division-multiple-access (WCDMA) application is demonstrated. The main amplifier is a parallel combination of drive amplifiers, and the same type of drive amplifier is also used to generate the predistortion signal. Self-cancellation of the intermodulation-distortion (IMD) components is obtained by the generic identity between the nonlinear characteristics of the main amplifier and the predistortion signal, both of which are originated from the same type of devices. Such self-cancellation scheme exhibits the improvement of 13 dB in the adjacent channel leakage ratio (ACLR) for WCDMA signal excitation.     

A simulation study to evaluate the feasibility of midgap workfunction metal gates in 25 nm bulk CMOS

The performance of 25 nm metallurgical channel length bulk MOSFETs with midgap workfunction metal gates has been compared with conventional polysilicon gates and bandedge workfunction metal gates. Device design using pocket halo implants was implemented to achieve the required off-state leakage specification. Highly accurate, full device simulations have been performed with a linear chain of inverters taking quantum effects into consideration. Drain induced barrier lowering (DIBL) was used as an indicator of short channel effects, and the stage delay of a linear chain of inverters and the on state drive current (I/sub on/) have been identified as metrics for performance. Compared to bandedge metal gates, midgap gates suffer from lower drive currents for both NMOS and PMOS devices. On the other hand, midgap devices were comparable in their performance to N/sup +/ polysilicon gated devices and exceeded that of P/sup +/ polysilicon devices. This high performance was attributed to a lack of poly depletion in midgap metal devices and a higher degree of DIBL which resulted in a lower V/sub t/ under high drain bias providing high drive current. Conclusions have been drawn on the feasibility of using midgap metal gates to simplify process integration in future generation CMOS devices.     

A 10-bit video BiCMOS track-and-hold amplifier

A 1.2-μm VLSI BiCMOS technology has been used to implement a monolithic video track-and-hold amplifier that settles to an accuracy of 10 b in 15 ns. This level of performance is competitive with hybrid track-and-hold circuits and surpasses previously reported monolithic implementations by nearly two orders of magnitude. The amplifier's design is based on a closed-loop topology incorporating two BiCMOS folded-cascode gain stages, an NMOS sampling switch, and a BiCMOS switch driver with 1-ns transitions between ±4 V. The circuit operates from ±5-V power supplies and is capable of driving a 50-Ω load with ±1-V swings. For a fully differential implementation, the power dissipation is 1.2 W. The amplifier can be integrated either as a stand-alone track-and-hold circuit or as the front end of an analog-to-digital conversion system for video and high-speed instrumentation applications     

A 25-ns low-power full-CMOS 1-Mbit (128 K×8) SRAM

A 5-V full-CMOS 1-Mb SRAM (static random-access memory) is described. The access time is 25 ns with 30-pF load, and power dissipation is 75 mW at 10 MHz and less than 1 μW in standby mode. The chip is made in a 0.7-μm twin-tub, single-poly, double-metal technology on p/p⁺ epi substrate. Cascoding of NMOS devices and special timing techniques are used to suppress hot-electron degradation. The authors describe circuit techniques that obtain low active power dissipation and high speed for a byte-wide part     

A 86 to 108 GHz Amplifier in 90 nm CMOS

This letter presents a CMOS amplifier with 22 GHz 3-dB bandwidth ranging from 86 to 108 GHz. The amplifier is implemented in 90 nm mixed signal/radio frequency (RF) CMOS process using three-stage cascode RF NMOS configuration. It achieves a peak gain of 17.4 dB at 91 GHz from the measured results. To our knowledge, this is the highest frequency CMOS amplifier reported to date.     

Chopper stabilization of MOS operational amplifiers using feed-forward techniques

A monolithic chopper amplifier system has been developed that reduces the effective offset voltage of an NMOS operational amplifier to a few microvolts without compromising bandwidth. Internally, two amplifiers are used, connected in a switched feed-forward configuration. The system is realized in a standard silicon gate enhancement/depletion process.     

A high-performance five-channel NMOSFET using selective epitaxialgrowth and lateral solid phase epitaxy

In this letter, a novel five-channel NMOSFET (FC-NMOS) using selective epitaxial growth (SEG) and lateral solid phase epitaxy (LSPE) is reported. The FC-NMOS is an integration of a conventional bulk NMOS, two vertical NMOS, and a gate-all-around NMOS. The top silicon layer for implementing the gate-all-around structure is obtained by using the LSPE with the SEG pillar as the silicon seed. The FC-NMOS has a 3.6× higher current drive as compared to the conventional bulk NMOS. This makes the FC-NMOS very promising for VLSI/ULSI applications