复合控制生成器

文中设计了一种新型密钥流生成器复控生成器,该生成器由一个(3)上的线性移位寄存器和一个(q)上的线性移位寄存器构成.文中详细讨论了不同的(q)对应的复控序列的周期和线性复杂度.研究表明主控序列的周期和线性复杂度都优于缩控序列和自缩控序列.     

一种新型的缩控生成器

将缩减生成器与一种新型的钟控生成器组合构成了一种新型的伪随机序列生成器—缩控生成器,它是由两个三元的线性反馈移位寄存器(LFSR)构成。文章讨论了这种新型的缩控序列的周期,线性复杂度,符号分布及1,2-重量复杂度等密码学性质。分析结果表明,这种缩控序列具有大的周期,大的线性复杂度,符号分布也比较均衡,而且当LFSR级数很大时,缩控序列能够有效地抵抗B-M算法的攻击,适合于流密码系统中的应用。     

扩散输出序列的构造与分析

基于钟控、缩减生成器的构造思想,结合个别元素控制扩大输出的方式构造了一种新型伪随机序列生成器—扩散输出生成器。分析得到其生成序列—扩散输出序列的周期、线性复杂度及游程分布。文中进一步改变扩散输出组,得到一组伪随机序列,分析得到相应序列的周期和线性复杂度,实现对扩散输出生成器的拓展.     

钟控密钥流生成器及其密码性能

提出了一种新的钟控密钥流生成器,由3个移位寄存器组成：两个被钟控的线性反馈移位寄存器A和B,一个提供钟控信息的非线性反馈移位寄存器C。设A、B和C的长度分别为l1、l2和l3。移位寄存器A和B的钟控信息由从移位寄存器C选取的两个比特串提供,移位的次数分别是两个比特串的汉明重量。研究了该生成器的周期、线性复杂度和k错线性复杂度,分析了这种密钥流生成器的安全性。     

一类具有良好特性的二元周期序列

本文利用m-序列和前馈序列的特性提出了一种新的生成器。这种生成器所生成的序列具有大的周期和线性复杂度,并且具有良好的伪随机特性。     

一种基于m-序列的逆矩阵置换生产方法

在序列密码中,输出序列的线性复杂度是一种非常重要的特征性质,因为已知的Berlekamp-massey算法对滚动密钥生成器是一种有效而且威胁极大的攻击手段,所以在设计滚动密钥序列生成器时必须能产生具有极大线性复杂度的密钥序列,虽然这只是个必要非充分的条件。利用m-序列的良好特性与代数上的逆矩阵理论提出了一种用本原多项式生成的线性反馈移位寄存器序列置换生成的具有良好性质的伪随机序列。新生成的二元序列不但保持了m-序列的良好特性,同时还极大提高了序列的线性复杂度,在一定范围内具有良好实用价值。     

采样序列的分析

钟控生成器是一种重要的密钥流生成器,它产生的钟控序列具有较好的复杂度和较强的伪随机性质。目前提出的钟控模型大多是基于序列的相互控制,对输入序列进行采样,而且经常是一类非均匀采样序列,要研究其性质,就必须对采样序列进行分析。丈中分析了采出序列的周期和线性复杂性与被采序列的周期和线性复杂性之间的关系,并以A5／1算法为例,分析变形后的A5／1算法的输出序列的周期和线性复杂度。     

振荡生成器

文章基于GF（2）上一条m-序列，给出一类新型的伪随机序列生成器——振荡生成器。并进一步给出了简化模型，且生成序列具有大周期和高线性复杂度．其简化模型生成序列周期和线性复杂度分别达到（2^m-1）^2和m（2^m-1），稳定性良好，适于在密码系统中使用。     

二维缩控生成器的构造与分析

论文基于三元伪随机序列,将钟控生成器和缩减生成器结合进行二维输出,构成一种新型伪随机序列生成器—二维缩控生成器,由其生成的二维缩控序列具有大周期和高线性复杂度,能够抵抗诸如B-M算法等综合算法攻击,且证明了序列游程长度为1或2,数据率为8/9,符号分布基本平衡等性质。因此,二维缩控生成器适合在流密码系统中应用。     

一类具有可控线性复杂度和双重密钥的非线性生成器

本文讨论一类非线性生成器的分析与综合。这类非线性生成器由三部份组成:nm级的带有本原联结多项式的线性移位寄存器,随机选择器;m端的非线性前馈函数。本文证明了该系统的线性复杂度是可控制的;易于实现(其软件实现的计算复杂度为O(m~3+nm));安全性远远高于原始的前馈网络,即在已知前馈函数和线性移位寄存器时,破译该系统穷举法成功的概率几乎为零。     

一款切合实际的30A能量计

本文介绍了一款集成了30A检测电阻器LTC2947.     

注钼纯铝的研究

利用从金属蒸汽真空弧离子源（简称ＭＢＶＶＡ源）引出的强束流钼离子对纯铝进行了不同束流密度的离子注入。加速电压为４８ｋＶ，剂量为３×１０￣（１７）ｃｍ￣（－２），束流密度为２５和４７μＡ·ｃｍ￣（－２），Ｘ衍射分析证明在注入层内可形成Ａｌ＿（１２）Ｍｏ晶体，背散射（ＲＢＳ）分析证明Ａｌ＿（１２）Ｍｏ的厚度可达６００至７００ｎｍ。     

A charge-balancing monolithic A/D converter

The quest for a minimum-parts-count DPM led to the development of this monolithic, low power analog-to-digital converter. It incorporates the analog and digital functions historically implemented separately with specialized process technologies into a chip with full /spl plusmn/3 digit accuracy. The integration of resistors, compensation capacitors, and an oscillator reduces the external component complement to three capacitors and one adjustable reference. TTL compatible outputs include sign, overrange, and under range information in addition to the three digit strobes and the BCD data outputs. The logic operates between +5 V and ground, the linear section between +5 V and -5 V. The paper describes the conversion algorithm and its CMOS implementation, emphasizing the analog design of this innovative device.     

A Convenient Multivariate Gram-Charlier Type A Series

It is often necessary to approximate the probability density function of a random variable from given statistical moments. The Gram-Charlier Type A series is one well known method for such representations. In this note, the Gram-Charlier Type A series is generalized to the multidimensional case.     

一种识别说话者的新方法

在能够自动识别视频中的说话者的系统中,大部分采用的是声音和唇部运动相结合的方法。文中则采用了另一种方法有效地达到了目的,即通过检测人体头部和手部的运动来鉴别说话者。基于演讲者在说话时通常会伴有头部运动或是手部运动,该方法既能实现说话者的检测,又能避免由于观测点过远而导致无法判断人唇部运动的局限性。在系统的实施过程中,运用了多种图像处理方法,并且对三帧差运动法做出了改善,使其能更高效、更准确地检测到头部和手部的运动。经过多个不同的视频测试后,本系统的F1 score高达91．91％,从而验证了该系统的可行性。     

高速高精度A/D转换器

本文介绍了用于观测太阳磁场的天文望远镜系统的高速高精度局部级联式多阈值A/D转换器。文章着重讨论了,为实现高速、高精度所采用的技术要点,并提出了研制高速高精度A/D转换器所必须考虑的有关问题。 我们所研制的A/D转换器,分辨率为1mV,相对误差0.025％,字长12位,前面接采样保持电路后,速度为10万次/秒。     

A Nyquist-rate delta-sigma A/D converter

This paper describes an analog-to-digital converter which combines multiple delta-sigma modulators in parallel so that time oversampling may be reduced or even eliminated. By doubling the number of Lth-order delta-sigma modulators, the resolution of this architecture is increased by approximately L bits. Thus, the resolution obtained by combining M delta-sigma modulators in parallel with no oversampling is similar to operating the same modulator with an oversampling rate of M. A parallel delta-sigma A/D converter implementation composed of two, four, and eight second-order delta-sigma modulators is described that does not require oversampling. Using this prototype, the design issues of the parallel delta-sigma A/D converter are explored and the theoretical performance with no oversampling and with low oversampling is verified. This architecture shows promise for obtaining high speed and resolution conversion since it retains much of the insensitivity to nonideal circuit behavior characteristic of the individual delta-sigma modulators     

A charge-domain D/A conversion system

In this article, a new multiplication type D/A conversion system using CCD is proposed and the result of simulations for evaluating its performance is reported. The system consists of a recursive charge divider which divides input charge-packet Qin sequentially into output charge-packets Qin · 2^-i and two charge-packet accumulators which accumulates output charge-packets from the recursive divider selectively according to digital input signal bits starting from MSB. The system converts input digital signal bit by bit, fully in charge-domain, thus the power consumption for this system is supposed to be very low. Also in this article, an effective method to achieve higher accuracy for splitting a charge-packet into two equal-sized packets using very simple hard-ware structure is proposed. As the result of simulations, we have found that the upper limit of accuracy for the conversion is determined by transfer efficiency of CCD, and within this range a trade-off relationship exists among conversion-accuracy, circuit-size and conversion-rate. This unique relationship enables to reduce the circuit size of D/A converter significantly maintaining the accuracy of conversion by slowing down the conversion-rate. This D/A converter is appropriate especially for the system integration because of its simple structure, tolerance to the fabrication error and low power consumption inherrent in the nature of CCD. By using of this system, it is expected to be possible to realize a focal plane image processor performing parallel analog operations such as DCT conversion with CCD imager incorporated on the same Si chip by the same MOS process technology.     

A monolithic video A/D converter

The design and measured performance of a fully parallel monolithic 8-bit A/D converter is reported. The required comparators and combining logic were designed and fabricated with a standard high-performance triple-diffused technology. A bipolar comparator circuit giving good performance with high input impedance is described. Circuit operation is reported at sample rates up to 30 megasamples per second (MS/s), with analog input signal power at frequencies up to 6 MHz. Full 8-bit linearity was achieved. An SNR of 42-44 dB was observed at input signal frequencies up to 5.3 MHz.     

没有管理者的密钥共享方案

一般的密钥共享方案中都假设有一个管理者,管理者的作用是分发密钥,因此对管理者的可信要求很高,而现实生活中很难找到符合要求的管理者.文中利用单调存取结构上的张成方案构造了一个没有管理者的密钥共享方案,并证明其是一个可行的实用的密钥共享方案.基于这个的方案,构造了一个分布式密钥生成器.