Development of process modeling methodology for flip chip on flex interconnections with non-conductive adhesives

This paper presents a comprehensive methodology to model the assembly process of flip chip on flex interconnections with non-conductive adhesives (NCAs). The methodology combines experimental techniques for material characterization, finite element modeling, and model validation. A non-conductive adhesive has been characterized using several techniques. A unique experimental technique has been developed to measure the cure shrinkage. A 2D axisymmetric finite element model is used for analysis of flip chip on flex package with the non-conductive adhesive (NCA), which takes into account assembly force, cure shrinkage, adhesive modulus buildup, removal of assembly force, and cooling down to room temperature. The relationship between the bump contact resistance and the bump pressure has been established through the development of a dedicated experimental setup, which uses a micro-force tester combined with a digital multimeter and a nano-voltmeter. The process modeling has been validated by comparing the predicted bump contact resistance value and the measured bump contact resistance value after assembly process. The approach developed in this paper can be used to provide guidelines with respect to adhesive material properties, assembly process parameters, and good reliability performances.     

Anisotropic conductive adhesives with enhanced thermal conductivity for flip chip applications

This paper presents the development of new anisotropic conductive adhesives (ACAs) with enhanced thermal conductivity for improved reliability of adhesive flip chip assembly under high current density condition. As the bump size in the flip chip assembly is reduced, the current density through the bump also increases. This increased current density causes new failure mechanisms, such as interface degradation due to intermetallic compound formation and adhesive swelling resulting from high current stressing. This process is found especially in high current density interconnection in which the high junction temperature enhances such failure mechanisms. Therefore, it is necessary for the ACA to become a thermal transfer medium that allows the board to act as a new heat sink for the flip chip package and improve the lifetime of the ACA flip chip joint. We developed the thermally conductive ACA of 0.63 W/m·K thermal conductivity by using a formulation incorporating the 5-μm Ni-filled and 0.2-μm SiC-filled epoxy-based binder system. The current carrying capability and the electrical reliability under the current stressing condition for the thermally conductive ACA flip chip joints were improved in comparison to conventional ACA. This improvement was attributed to the effective heat dissipation from Au stud bumps/ACA/PCB pad structure by the thermally conductive ACA.     

Highly reliable, fine pitch chip on glass (COG) joints fabricated using Sn/Cu bumps and non-conductive adhesives

We have developed a reliable and ultra-fine pitch chip on glass (COG) bonding technique using Sn/Cu bumps and non-conductive adhesive (NCA). Sn/Cu bumps were formed by electroplating and reflowed, forming dome shaped Sn bumps on Cu columns. COG bonding was performed between the reflowed Sn/Cu bumps on the oxidized Si wafer and ITO/Au/Cu/Ti/glass substrate using a thermo-compression bonder. Three different NCAs were applied during bonding. Bonding temperature was 150 °C for NCA-A and NCA-B, and 110 °C for NCA-C. The electrical properties of COG joints were evaluated by measuring the contact resistance of each joint through the four-point probe method. All joints were successfully bonded and the electrical measurement showed that the average contact resistance of each joint was approximately 30 mΩ, regardless of NCA types. The COG joints were subjected to a series of reliability tests: high temperature storage test (85 °C, 160 h); thermal cycling test (−40 °C/+85 °C, 20 cycle); and a temperature and humidity test (50 °C/90%, 160 h) were sequentially performed to evaluate the reliability of the COG joints. The contact resistance measurement showed that there were no failed bumps in all specimens and all joints passed the criterion after reliability test.     

Bump formation for flip chip and CSP by solder paste printing

Area array packages (flip chip, CSP and BGA) require the formation of bumps for the board assembly. Since the established bumping methods need expensive equipment or are limited by the throughput, minimal pitch and yield the industry is currently searching for new and lower cost bumping approaches. In this paper the experimental work of stencil printing to create solder bumps for flip chip and wafer level CSP (CSP-WL) is described in detail.This paper is divided into two parts. In the first part of the paper a low cost wafer bumping process for flip chip applications will be studied in particular. The process is based on an electroless Nickel under bump metallization and solder bumping by stencil printing. The experimental results for this technology will be presented and the limits concerning pitch, reproducibility and bump height will be discussed in detail. The second part of the paper is focused on solder paste printing for wafer-level CSPs. In order to achieve large bumps an optimized printing method will be presented. Additionally advanced stencil design will be shown and the achieved results will be compared with conventional methods.     

Transmission property of flip chip package with adhesive interconnection for RF applications

The radio frequency (RF) and high frequency performance of the flip chip interconnects with anisotropic conductive film (ACF) and non-conductive film (NCF) was investigated and compared by measuring the scattering parameters (S-parameters) of the flip chip modules. Low cost electroless-Ni immersion-Au (ENIG) plating was employed to form the bumps for the adhesive bonding. To compare the accurate intrinsic RF performance of the ACF and NCF interconnect without lossy effect of chip and substrate, a de-embedding modeling algorithm was employed. The effects of two chip materials (Si and GaAs), the height of ENIG bumps, and the metal pattern gap between the signal line and ground plane in the coplanar waveguide (CPW) on the RF performance of the flip chip module were also investigated. The transmission properties of the GaAs were markedly improved on those of the Si chip, which was not suitable for the measurement of the S-parameters of the flip chip interconnect. Extracted impedance parameters showed that the RF performance of the flip chip interconnect with NCF was slightly better than that of the interconnect with ACF, mainly due to the capacitive component between the bump and substrate and self inductance of the conductive particle surface in the ACF interconnect.     

Single chip bumping and reliability for flip chip processes

Processes of bump deposition based on mechanical procedures together with their reliability data are summarized in this paper. The stud bumping of gold, palladium, and solder is described and also a novel bumping approach for fine pitch solder deposition down to 100 μm pitches using thermosonic bonding on a modified wedge–wedge bonding machine. This wedge bumping doesn’t require a wire flame-off process step. Because of this, no active atmosphere is necessary. The minimum pad diameter which can be bumped using the solder wedge bumping is 50 μm, up to now. This bumping process is highly reproducible and therefore well-suited for different flip chip soldering applications. Palladium stud bumps provide a solderable under bump metallization. Results from aging of lead/tin solder bumps on palladium are shown. The growth of intermetallics and its impact on the mechanical reliability are investigated.     

Current-carrying capacity of anisotropic-conductive film joints for the flip chip on flex applications

The effect of the substrate-pad physical properties (surface roughness and hardness) on the current-carrying capacity of anisotropic-conductive film (ACF) joints is investigated in this work. Flip chips with Au bumps were bonded to the flexible substrates with Au/Cu and Au/Ni/Cu pads using different bonding pressure. It was found that the current-carrying capacity of ACF joints increased to a maximum value with the rise of the bonding pressure; then, it reduced if the bonding pressure continually increased. The maximum average value per unit area of Au/Ni/Cu pad and Au/Cu pad ACF joints is about 93 μA/μm² and 118 μA/μm², respectively, at 100-MPa bonding pressure. The variation trend of connection resistance is the opposite of current-carrying capacity. The variation of current-carrying capacity (or connection resistance) of Au/Cu pad joints is larger than that of Au/Ni/Cu pad joints. The current-carrying capacity is related to the variation of the resistance of ACF joints. The connection resistance of ACF joints depends primarily on the particle constriction resistance (R_coi), R_coi ∞ 1/a, where “a” is the radius of contact spot. A smaller contact area results in larger joule heat generation per unit volume (Q_g), Q_g ∞ 1/a⁴, which preferentially elevates the temperature of the constriction. The raised temperature increases the resistance because of the temperature-dependent coefficient of the metal resistivity. The theory of tribology is used to explain the difference between Au/Cu pad and Au/Ni/Cu pad ACF joints. For the Au/Cu pad ACF joints, the deformation of the particles’ upper and bottom sides is nearly symmetrical; the contact between conductive particles and pad has the character of “sliding contact,” especially under high pressure. For the Au/Ni/Cu pad ACF joint, the contact between particles and pad determined the conduction characteristics of ACF joints. It has the character of “static contact.” Thus, the current-carrying capacity (or connection resistance) of Au/Cu pad joints is more sensitive to the bonding pressure.     

倒装芯片凸焊点的UBM

介绍了倒装芯片凸焊点的焊点下金属（UBM）系统,讨论了电镀Au凸焊点用UBM的溅射工艺和相应靶材、溅射气氛的选择,给出了凸焊点UBM质量的考核试验方法和相关指标。     

Laser-assisted bumping for flip chip assembly

A novel laser-assisted chip bumping technique is presented in which bumps are fabricated on a carrier and subsequently transferred onto silicon chips by a laser-driven release process. Copper bumps with gold bonding layers and intermediate nickel barriers are fabricated on quartz wafers with pre-deposited polyimide layers, using UV lithography and electroplating. The bumps are thermosonically bonded to their respective chips and then released from the carrier by laser machining of the polyimide layer, using light incident through the carrier. Bumps of 60 to 85 μm diameter and 50 μm height at a pitch of 127 μm have been fabricated in peripheral arrays. Parallel bonding and subsequent transfer of arrays of 28 bumps onto test chips have been successfully demonstrated. Individual bump shear tests have been performed on a sample of 13 test chips, showing an average bond strength of 26 gf per bump     

Analysis of nickel cylindrical bump insertion into aluminium thin film for flip chip applications

This paper investigates the mechanical deformation and the electrical contact resistance of an electroplated Ni micro-cylinder called micro-insert inserted in an Al thin film. A modified nanoindentation apparatus is used to perform the experiments with 6 μm, 8.5 μm and 12.5 μm diameters micro-inserts having the same 5 μm height. Mechanical deformation of Ni micro-insert and Al film is described at different maximum loads corresponding to an equivalent stress of 0.8 GPa, 1.6 GPa and 3.2 GPa. At equivalent stress less than 1.6 GPa, Ni micro-insert exhibits an elastic deformation while at 3.2 GPa it presents an elastic-plastic deformation with a large amount of compression and penetration into micro-insert foundation. Visco-plastic deformation of Al film is noticed during hold at all maximum loads. Beside, Al creep parameters are extracted using a combined Maxwell/Kelvin-Voigt phenomenological model. Mechanical results are coupled to electrical contact resistance measurement.     

Coaxial transitions for CPW-to-CPW flip chip interconnects

A novel coaxial transition for CPW-to-CPW flip chip interconnect is presented and experimentally demonstrated. To realise the coaxial transition on the CPW circuit, benzocyclobutene was used as the interlayer dielectric between the vertical coaxial transition and the CPW circuit. The coaxial interconnect structure was successfully fabricated and RF characterised to 67 GHz. The structure showed excellent interconnect performance from DC up to 55 GHz with low return loss below 20 dB and low insertion loss less than 0.5 dB even when the underfill was applied to the structure.     

Parametric compact models for flip chip assemblies

A parametric thermal compact modeling study of flip chip assemblies is presented. First, a star network of four thermal resistors was found to be optimal for a flip chip with arbitrary geometry and material properties. In a second step several parameters such as thermal underfill conductivity and die size were varied. The effect of these variations on the values of the four thermal resistors of the compact model is investigated. In a third step, a response surface model is derived from these compact models, which gives end-users the possibility of choosing a flip chip with arbitrary geometry and deduce automatically the corresponding thermal compact model. Having the compact model, it is now possible to apply customer specific boundary conditions to this compact model and compute the maximal temperature reached at the junction of the flip chip assembly in the specified environment     

Cycling copper flip chip interconnects

Use of flip chip assembly on compound semiconductor circuits is relatively new. Although solder bumping has been around for a while, use of copper bumps is also new. This discussion is intended to provide some initial data on the melding of copper flip chip bumps and compound semiconductor technologies, with respect to thermal excursion testing––cycling. For comparison, it is known that attempts to accelerate degradation caused by thermal excursions on solder bumps can result in irregular failure mechanisms. This work shows that on-chip power cycling can be used to cause identical failure mechanisms to those caused by normal temperature cycling.     

Effect of misalignment on electrical characteristics of ACF joints for flip chip on flex applications

The effect of misalignment on the electrical properties of anisotropic conductive film (ACF) joints is investigated in this work. It is found that along with the increase of misalignment, the connection resistance of ACF joints increases. When the misalignment in x-direction is less than 5 μm, the increase rate of connection resistance is quite large. Then, along with the severity of misalignment, the increase rate becomes smaller. Finally, when the misalignment is close to 20 μm, the increase rate rises again. The Holm's electric contact theory is used for understanding the connection resistance variation. On the other hand, with the increase of misalignment in x-direction, the insulation resistance between ACF joints decreases. If the misalignment exceeded 10 μm, the decrease is prominent for the Ni particle ACF joints. This phenomenon can be explained by the effect of dielectric damage of the epoxy.Computer programs are also developed to calculate the variation of the probability of open and shorting after misalignment and predicate the maximum misalignment tolerance. The results show that the open and shorting probability increase abruptly after misalignment. On the view of pad parameters, the open probability is mainly related to the pad area, while the pads gap is critical to the shorting probability. Large pads gap (small pad width) can reduce the shorting probability obviously. On the other hand, enlarging the pad area by increasing pad length decreases the open probability significantly. So comparing to square shape pad, rectangle shape pad can reduce the failure probability greatly.     

Comparison of different flex materials in high density flip chip on flex applications

This paper presents the results from the evaluation of different types of flexible substrates for high-density flip chip application. In this work four different flexible substrates were used. The flex substrates were Espanex, Upilex and epoxy glass with 80 μm pitch and Upilex with 54 μm pitch. Two different test IC’s were used for both pitches. In test IC1 (80 μm pitch) and IC3 (54 μm pitch) the bumps were in one row and test IC2 (80 μm pitch) and IC4 (54 μm pitch) in two rows. The total amount of contacts in test IC1 was 190, in test IC2 173, in test IC3 293 and in test IC4 270. The anisotropically conductive adhesive that was used in the tests was epoxy based thermosetting adhesive film with conductive particles. The conductive particles in the adhesives were isolated soft metal-coated polymer particles. The contact resistance was measured using Kelvin four-point method and the continuity and series resistance using daisy chain structure. The reliability of the flip chip interconnections was tested in temperature cycling test and environmental test. Cross section samples were made to analyse the possible reason for failures. The results presented in this paper are from FLEXIL development project that is part of European Union IST research program.     

Investigation of cure kinetics and its effect on adhesion strength of nonconductive adhesives used in flip chip assembly

The reaction kinetics of a commercial fast cure nonconductive adhesive has been systematically investigated using differential scanning calorimetry. Samples were isothermally cured at temperatures from 120 to 160/spl deg/C and dynamically cured at ramp rates between 5 and 20/spl deg/C/min. A good agreement between the autocatalytic kinetic model prediction and experimental results was demonstrated. Deviation occurred at high degrees of cure for curing below 140/spl deg/C due to the occurrence of vitrification. Additionally, by comparing the dynamic cure prediction with the isothermal experiment, good agreements and equivalence were demonstrated. As such, it is possible to predict the isothermal reaction behavior of fast cure materials at high temperature provided that the variation between the actual temperature of the heating system and the setting temperature is not large. Furthermore, the effect of curing process on the adhesion strength has been demonstrated by testing the shear strength of lap joint specimens. It was found that the evolution of adhesion strength was largely dependent on the buildup of mechanical properties during the curing process. At low and medium degrees of cure, cohesive and adhesive failures were respectively observed, while at high degrees of cure, adhesion strength surpassing the shear strength of the solder mask was observed. The sharp increase in adhesion strength was observed to coincide with the gelation point marked by the crossover between the storage and loss modulii, thus suggesting that the contributors to adhesion strength include mechanical interlocking as well as chemical bonding, as evidenced by buildup of storage modulus and mechanical strength of the adhesive.