Pt-Germanide Schottky source/drain Germanium p-MOSFET with HfO/sub 2/ gate dielectric and TaN gate electrode

Schottky source/drain (S/D) transistors using Pt-germanide and HfO/sub 2//TaN gate stack are fabricated on Ge-substrate with conventional self-aligned top-gate process. It was found that Pt-germanide provides promising properties for p-MOSFET: negative effective hole barrier height, low resistivity, atomically sharp junction with Ge with good morphology. Pt-germanide Ge-p-MOSFETs showed well-behaved I/sub D/-V/sub D/ characteristics and much suppressed I/sub off/ compared to Ni-germanide and conventional heavily doped S/D MOSFETs.     

High-performance poly-silicon TFTs using HfO/sub 2/ gate dielectric

High-performance low-temperature poly-Si thin-film transistors (TFTs) using high-/spl kappa/ (HfO/sub 2/) gate dielectric is demonstrated for the first time. Because of the high gate capacitance density and thin equivalent-oxide thickness contributed by the high-/spl kappa/ gate dielectric, excellent device performance can be achieved including high driving current, low subthreshold swing, low threshold voltage, and high ON/OFF current ratio. It should be noted that the ON-state current of high-/spl kappa/ gate-dielectric TFTs is almost five times higher than that of SiO/sub 2/ gate-dielectric TFTs. Moreover, superior threshold-voltage (V/sub th/) rolloff property is also demonstrated. All of these results suggest that high-/spl kappa/ gate dielectric is a good choice for high-performance TFTs.     

Gate capacitances behavior of nanometer FD SOI CMOS devices with HfO/sub 2/ high-k gate dielectric considering vertical and fringing displacement effects using 2-D Simulation

This paper reports the gate-source (drain)/source (drain)-gate capacitance behavior of 100-nm fully depleted silicon-on-insulator CMOS devices with HfO/sub 2/ high-k gate dielectric considering vertical and fringing displacement effects. Based on the two-dimensional simulation results, a unique two-step C/sub S(D)G//C/sub GS/ versus V/sub G/ curve could be identified for the device with the 1.5-nm HfO/sub 2/ gate dielectric due to the vertical and fringing displacement effects.     

Gate-first Germanium nMOSFET with CVD HfO/sub 2/ gate dielectric and silicon surface passivation

A gate-first self-aligned Ge n-channel MOSFET (nMOSFET) with chemical vapor deposited (CVD) high-/spl kappa/ gate dielectric HfO/sub 2/ was demonstrated. By tuning the thickness of the ultrathin silicon-passivation layer on top of the germanium, it is found that increasing the silicon thickness helps to reduce the hysteresis, fixed charge in the gate dielectric, and interface trap density at the oxide/semiconductor interface. About 61% improvement in peak electron mobility of the Ge nMOSFET with a thick silicon-passivation layer over the CVD HfO/sub 2//Si system was achieved.     

HfO/sub 2/ MIS capacitor with copper gate electrode

Metal-insulator-semiconductor capacitors were fabricated using atomic vapor deposition HfO/sub 2/ dielectric with sputtered copper (Cu) and aluminum (Al) gate electrodes. The counterparts with SiO/sub 2/ dielectric were also fabricated for comparison. Bias-temperature stress and charge-to-breakdown (Q/sub BD/) test were conducted to examine the stability and reliability of these capacitors. In contrast with the high Cu drift rate in an SiO/sub 2/ dielectric, Cu in contact with HfO/sub 2/ seems to be very stable. The HfO/sub 2/ capacitors with a Cu-gate also depict higher capacitance without showing any reliability degradation, compared to the Al-gate counterparts. These results indicate that HfO/sub 2/ with its considerably high density of 9.68 g/cm/sup 3/ is acting as a good barrier to Cu diffusion, and it thus appears feasible to integrate Cu metal with the post-gate-dielectric ultralarge-scale integration manufacturing processes.     

Low-frequency noise in submicrometer MOSFETs with HfO/sub 2/, HfO/sub 2//Al/sub 2/O/sub 3/ and HfAlO/sub x/ gate stacks

Low-frequency noise measurements were performed on p- and n-channel MOSFETs with HfO/sub 2/, HfAlO/sub x/ and HfO/sub 2//Al/sub 2/O/sub 3/ as the gate dielectric materials. The gate length varied from 0.135 to 0.36 /spl mu/m with 10.02 /spl mu/m gate width. The equivalent oxide thicknesses were: HfO/sub 2/ 23 /spl Aring/, HfAlO/sub x/ 28.5 /spl Aring/ and HfO/sub 2//Al/sub 2/O/sub 3/ 33 /spl Aring/. In addition to the core structures with only about 10 /spl Aring/ of oxide between the high-K dielectric and silicon substrate, there were "double-gate oxide" structures where an interfacial oxide layer of 40 /spl Aring/ was grown between the high-K dielectric and Si. DC analysis showed low gate leakage currents in the order of 10/sup -12/ A(2-5 /spl times/ 10/sup -5/ A/cm/sup 2/) for the devices and, in general, yielded higher threshold voltages and lower mobility values when compared to the corresponding SiO/sub 2/ devices. The unified number-mobility fluctuation model was used to account for the observed 1/f noise and to extract the oxide trap density, which ranged from 1.8 /spl times/ 10/sup 17/ cm/sup -3/ eV/sup -1/ to 1, 3 /spl times/ 10/sup 19/ cm/sup -3/ eV/sup -1/ somewhat higher compared to conventional SiO/sub 2/ MOSFETs with the similar device dimensions. There was no evidence of single electron switching events or random telegraph signals. The aim of this paper is to present a general discussion on low-frequency noise characteristics of the three different high-K/gate stacks, relative comparison among them and to the Si-SiO/sub 2/ system.     

Mobility enhancement in TaN metal-gate MOSFETs using tantalum incorporated HfO/sub 2/ gate dielectric

TaN metal-gate nMOSFETs using HfTaO gate dielectrics have been investigated for the first time. Compared to pure HfO/sub 2/, a reduction of one order of magnitude in interface state density (D/sub it/) was observed in HfTaO film. This may be attributed to a high atomic percentage of Si-O bonds in the interfacial layer between HfTaO and Si. It also suggests a chemical similarity of the HfTaO-Si interface to the high-quality SiO/sub 2/-Si interface. In addition, a charge trapping-induced threshold voltage (V/sub th/) shift in HfTaO film with constant voltage stress was 20 times lower than that of HfO/sub 2/. This indicates that the HfTaO film has fewer charged traps compared to HfO/sub 2/ film. The electron mobility in nMOSFETs with HfO/sub 2/ gate dielectric was significantly enhanced by incorporating Ta.     

Low-frequency noise in submicrometer MOSFETs with HfO/sub 2/, HfO/sub 2//Al/sub 2/O/sub 3/ and HfAlO/sub x/ gate stacks

Low-frequency noise measurements were performed on p- and n-channel MOSFETs with HfO/sub 2/, HfAlO/sub x/ and HfO/sub 2//Al/sub 2/O/sub 3/ as the gate dielectric materials. The gate length varied from 0.135 to 0.36 /spl mu/m with 10.02 /spl mu/m gate width. The equivalent oxide thicknesses were: HfO/sub 2/ 23 /spl Aring/, HfAlO/sub x/ 28.5 /spl Aring/ and HfO/sub 2//Al/sub 2/O/sub 3/ 33 /spl Aring/. In addition to the core structures with only about 10 /spl Aring/ of oxide between the high-/spl kappa/ dielectric and silicon substrate, there were "double-gate oxide" structures where an interfacial oxide layer of 40 /spl Aring/ was grown between the high-/spl kappa/ dielectric and Si. DC analysis showed low gate leakage currents in the order of 10/sup -12/A(2-5/spl times/10/sup -5/ A/cm/sup 2/) for the devices and, in general, yielded higher threshold voltages and lower mobility values when compared to the corresponding SiO/sub 2/ devices. The unified number-mobility fluctuation model was used to account for the observed 1/f noise and to extract the oxide trap density, which ranged from 1.8/spl times/10/sup 17/ cm/sup -3/eV/sup -1/ to 1.3/spl times/10/sup 19/ cm/sup -3/eV/sup -1/, somewhat higher compared to conventional SiO/sub 2/ MOSFETs with the similar device dimensions. There was no evidence of single electron switching events or random telegraph signals. The aim of this paper is to present a general discussion on low-frequency noise characteristics of the three different high-/spl kappa//gate stacks, relative comparison among them and to the Si--SiO/sub 2/ system.     

Bias-temperature instabilities of polysilicon gate HfO/sub 2/ MOSFETs

Bias-temperature instabilities (BTI) of HfO/sub 2/ metal oxide semiconductor field effect transistors (MOSFETs) have been systematically studied for the first time. NMOS positive BTI (PBTI) exhibited a more significant V/sub t/ instability than that of PMOS negative BTI (NBTI), and limited the lifetime of HfO/sub 2/ MOSFETs. Although high-temperature forming gas annealing (HT-FGA) improved the interface quality by passivating the interfacial states with hydrogen, BTI behaviors were not strongly affected by the technique. Charge pumping measurements were extensively used to investigate the nature of the BTI degradation, and it was found that V/sub t/ degradation of NMOS PBTI was primarily caused by charge trapping in bulk HfO/sub 2/ rather than interfacial degradation. Deuterium (D/sub 2/) annealing was found to be an excellent technique to improve BTI immunity as well as to enhance the mobility of HfO/sub 2/ MOSFETs.     

Modeling of tunneling currents through HfO/sub 2/ and (HfO/sub 2/)/sub x/(Al/sub 2/O/sub 3/)/sub 1-x/ gate stacks

We present a physical modeling of tunneling currents through ultrathin high-/spl kappa/ gate stacks, which includes an ultrathin interface layer, both electron and hole quantization in the substrate and gate electrode, and energy band offsets between high-/spl kappa/ dielectrics and Si determined from high-resolution XPS. Excellent agreements between simulated and experimentally measured tunneling currents have been obtained for chemical vapor deposited and physical vapor deposited HfO/sub 2/ with and without NH/sub 3/-based interface layers, and ALD Al/sub 2/O/sub 3/ gate stacks with different EOT and bias polarities. This model is applied to more thermally stable (HfO/sub 2/)/sub x/(Al/sub 2/O/sub 3/)/sub 1-x/ gate stacks in order to project their scalability for future CMOS applications.     

ZnO transparent thin-film transistors with HfO/sub 2//Ta/sub 2/O/sub 5/ stacking gate dielectrics

The performance improvement of ZnO thin-film transistors (TFTs) using HfO₂/Ta₂O₅ stacked gate dielectrics was demonstrated. The ZnO TFTs exhibited transistor behaviour over the range 0-10 V; the field effect mobility, subthreshold slope and on/off ratio were measured to be 1.3 cm² V^-1 s^-1, 0.5 V/decade and ~10⁶, respectively.     

Ultrathin Al/sub 2/O/sub 3/ and HfO/sub 2/ gate dielectrics on surface-nitrided Ge

We have studied ultrathin Al/sub 2/O/sub 3/ and HfO/sub 2/ gate dielectrics on Ge grown by ultrahigh vacuum-reactive atomic-beam deposition and ultraviolet ozone oxidation. Al/sub 2/O/sub 3/-Ge gate stack had a t/sub eq//spl sim/23 /spl Aring/, and three orders of magnitude lower leakage current compared to SiO/sub 2/. HfO/sub 2/-Ge allowed even greater scaling, achieving t/sub eq//spl sim/11 /spl Aring/ and six orders of magnitude lower leakage current compared to SiO/sub 2/. We have carried out a detailed study of cleaning conditions for the Ge wafer, dielectric deposition condition, and anneal conditions and their effect on the electrical properties of metal-gated dielectric-Ge capacitors. We show that surface nitridation is important in reducing hysteresis, interfacial layer formation and leakage current. However, surface nitridation also introduces positive trapped charges and/or dipoles at the interface, resulting in significant flatband voltage shifts, which are mitigated by post-deposition anneals.     

Low-frequency noise in TaSiN/HfO/sub 2/ nMOSFETs and the effect of stress-relieved preoxide interfacial layer

Low-frequency noise characteristics are reported for TaSiN-gated n-channel MOSFETs with atomic-layer deposited HfO/sub 2/ on thermal SiO/sub 2/ with stress-relieved preoxide (SRPO) pretreatment. For comparison, control devices were also included with chemical SiO/sub 2/ resulting from standard Radio Corporation of America clean process. The normalized noise spectral density values for these devices are found to be lower when compared to reference poly Si gate stack with similar HfO/sub 2/ dielectric. Consequently, a lower oxide trap density of /spl sim/4/spl times/10/sup 17/ cm/sup -3/eV/sup -1/ is extracted compared to over 3/spl times/10/sup 18/ cm/sup -3/eV/sup -1/ values reported for poly Si devices indicating an improvement in the high-/spl kappa/ and interfacial layer quality. In fact, this represents the lowest trap density values reported to date on HfO/sub 2/ MOSFETs. The peak electron mobility measured on the SRPO devices is over 330 cm/sup 2//V/spl middot/s, much higher than those for equivalent poly Si or metal gate stacks. In addition, the devices with SRPO SiO/sub 2/ are found to exhibit at least /spl sim/10% higher effective mobility than RCA devices, notwithstanding the differences in the high-/spl kappa/ and interfacial layer thicknesses. The lower Coulomb scattering coefficient obtained from the noise data for the SRPO devices imply that channel carriers are better screened due to the presence of SRPO SiO/sub 2/, which, in part, contributes to the mobility improvement.     

TDDB and polarity-dependent reliability of high-quality, ultrathin CVD HfO/sub 2/ gate stack with TaN gate electrode

In this letter, we present a comprehensive study on longterm reliability of ultrathin TaN-gated chemical vapor deposition gate stack with EOT=8.5-10.5. It is found that, due to the asymmetric band structure of HfO/sub 2/ gate stack with an interfacial layer, the HfO/sub 2/ gate stack shows polarity-dependent leakage current, critical defect density, and defect generation rate, under gate and substrate injection. However, no such polarity dependence of time-to-breakdown (T/sub BD/) is observed when T/sub BD/ is plotted as a function of gate voltage. The 10-year lifetime of an HfO/sub 2/ gate stack is projected to be Vg=-1.63 V for the equivalent oxide thickness (EOT) =8.6 and Vg=-1.88 V for EOT=10.6 at 25/spl deg/C. These excellent reliability characteristics are attributed to reduced leakage current of HfO/sub 2/ gate stack with physically thicker films that result in larger critical defect density and Weibull slope to that of SiO/sub 2/ for the same EOT. However, at 150/spl deg/C, and with area scaling to 0.1 cm/sup 2/ and low percentile of 0.01%, the maximum allowed voltages are projected to Vg=-0.6 V and -0.75 V for EOT of 8.6, and 10.6, respectively.     

Dual layer SrTiO3/HfO2 gate dielectric for aggressively scaled band-edge nMOS devices

We have fabricated TiN/Poly-Si gated MOS devices with SrTiO₃/HfO₂ dual layer gate dielectric. These gate dielectrics show EOT (Equivalent Oxide Thickness) scaling of less than 0.7 nm as well as large V_fb shift in the nMOS direction after conventional gate first process. A sweet spot is observed for 0.5 nm SrTiO₃ where a band-edge effective work-function is obtained with improved EOT, reduced gate leakage and minimal hysteresis increase. But Sr diffuse into the interfacial layer leads to interface degradation. It is shown that proper PDA (post-deposition anneal) can improve interface quality while maintaining thinner EOT.     

Effects of deuterium anneal on MOSFETs with HfO/sub 2/ gate dielectrics

The effects of high-temperature (600/spl deg/C) anneal in a dilute deuterium (N/sub 2/ : D/sub 2/= 96 : 4) atmosphere was first investigated and evaluated in comparison to high-temperature forming gas (N/sub 2/ : H/sub 2/= 96 : 4) anneal (600/spl deg/C) and nonanneal samples. The high-temperature deuterium anneal was as effective as the forming gas anneal in improving MOSCAP and MOSFET characteristics such as the C-V curve, drain current, subthreshold swing, and carrier mobility. These can be attributed to the improved interface quality by D/sub 2/ atoms. However, unlike the forming gas anneal, the deuterium anneal provided the hafnium oxide (HfO/sub 2/) gate dielectric MOSFET with better reliability characteristics such as threshold voltage (V/sub T/) stability under high voltage stress.     

Schottky-barrier source/drain MOSFETs on ultrathin SOI body with a tungsten metallic midgap gate

This letter presents a simple low-temperature process to fabricate Schottky-barrier (SB) MOSFETs that integrates a midgap metallic gate (tungsten). The device architecture is based on a thin (10 nm) and lowly doped silicon-on-insulator film that provides a threshold voltage of -0.3 V independent on the depletion charge and therefore not sensitive to variations in film thickness and doping. A gate encapsulation technique using an SiO/sub 2/-like hydrogen silsesquioxane capping layer features 15-nm-wide spacers and ensures the compatibility with the PtSi self-aligned silicide process. Long-channel devices present an ideal subthreshold swing of 60 mV/dec, over six decades of I/sub on//I/sub off/ without any sign of sublinear upward bending of the I/sub DS/--V/sub DS/ curves at low drain voltage.     

Aggressively scaled ultra thin undoped HfO/sub 2/ gate dielectric (EOT<0.7 nm) with TaN gate electrode using engineered interface layer

The ultrathin HfO/sub 2/ gate dielectric (EOT<0.7 nm) has been achieved by using a novel "oxygen-scavenging effect" technique without incorporation of nitrogen or other "dopants" such as Al, Ti, or La. Interfacial oxidation growth was suppressed by Hf scavenging layer on HfO/sub 2/ gate dielectric with appropriate annealing, leading to thinner EOT. As the scavenging layer thickness increases, EOT becomes thinner. This scavenging technique produced a EOT of 7.1 /spl Aring/, the thinnest EOT value reported to date for "undoped" HfO/sub 2/ with acceptable leakage current, while EOT of 12.5 /spl Aring/ was obtained for the control HfO/sub 2/ film with the same physical thickness after 450/spl deg/C anneal for 30 min at forming gas ambient. This reduced EOT is attributed to "scavenging effect" that Hf metal layer consumes oxygen during anneal and suppresses interfacial reaction effectively, making thinner interface layer. Using this fabrication approach, EOT of /spl sim/ 0.9 nm after conventional self-aligned MOSFETs process was successfully obtained.     

Charge trapping and degradation of HfO/sub 2//SiO/sub 2/ MOS gate stacks observed with enhanced CAFM

In this letter, a prototype of conductive atomic force microscope with enhanced electrical performance has been used to separately investigate the effect of the electrical stress on the SiO/sub 2/ and the HfO/sub 2/ layers of a high-/spl kappa/ gate stack. Charge trapping in HfO/sub 2/ native defects and degradation of both layers have been observed, depending on the stress level.     

Mobility enhancement in surface channel SiGe PMOSFETs with HfO/sub 2/ gate dielectrics

We report for the first time drive current enhancement and higher mobilities than the universal mobility for SiO/sub 2/ on Si in compressively strained Si/sub 1-x/Ge/sub x/-on-Si surface channel PMOSFETs with HfO/sub 2/ gate dielectrics, for gate lengths (L/sub G/) down to 180 nm. Thirty six percent drive current enhancement was achieved for Si/sub 0.8/Ge/sub 0.2/ channel PMOSFETs compared to Si PMOSFETs with HfO/sub 2/ gate dielectric. We demonstrate that using Si/sub 1-x/Ge/sub x/ in the channel may be one way to recover the mobility degradation due to the use of HfO/sub 2/ on Si.