A hybrid memory architecture supporting fine-grained data migration

Hybrid memory systems composed of dynamic random access memory (DRAM) and Non-volatile memory (NVM) often exploit page migration technologies to fully take the advantages of different memory media. Most previous proposals usually migrate data at a granularity of 4 KB pages, and thus waste memory bandwidth and DRAM resource. In this paper, we propose Mocha, a non-hierarchical architecture that organizes DRAM and NVM in a flat address space physically, but manages them in a cache/memory hierarchy. Since the commercial NVM device–Intel Optane DC Persistent Memory Modules (DCPMM) actually access the physical media at a granularity of 256 bytes (an Optane block), we manage the DRAM cache at the 256-byte size to adapt to this feature of Optane. This design not only enables fine-grained data migration and management for the DRAM cache, but also avoids write amplification for Intel Optane DCPMM. We also create an Indirect Address Cache (IAC) in Hybrid Memory Controller (HMC) and propose a reverse address mapping table in the DRAM to speed up address translation and cache replacement. Moreover, we exploit a utility-based caching mechanism to filter cold blocks in the NVM, and further improve the efficiency of the DRAM cache. We implement Mocha in an architectural simulator. Experimental results show that Mocha can improve application performance by 8.2% on average (up to 24.6%), reduce 6.9% energy consumption and 25.9% data migration traffic on average, compared with a typical hybrid memory architecture–HSCC.     

基于持久化内存的索引设计重新思考与优化

非易失性内存(non-volatile memory,NVM)是近几年来出现的一种新型存储介质.一方面,同传统的易失性内存一样,它有着低访问延迟、可字节寻址的特性;另一方面,与易失性内存不同的是,掉电后它存储的数据不会丢失,此外它还有着更高的密度以及更低的能耗开销.这些特性使得非易失性内存有望被大规模应用在未来的计算机系统中.非易失性内存的出现为构建高效的持久化索引提供了新的思路.由于非易失性硬件还处于研究阶段,因此大多数面向非易失性内存的索引研究工作基于模拟环境开展.在2019年4月英特尔发布了基于3D-XPoint技术的非易失性内存硬件apache pass(AEP),这使得研究人员可以基于真实的硬件环境去进行相关研究工作.首先评测了真实的非易失性内存器件,结果显示AEP的写延迟接近DRAM,而读延迟是DRAM的3~4倍.基于对硬件的实际评测结果,研究发现过去很多工作对非易失性内存的性能假设存在偏差,这使得过去的一些工作大多只针对写性能进行优化,并没有针对读性能进行优化.因此,重新审视了之前研究工作,针对过去的混合索引工作进行了读优化.此外,还提出了一种基于混合内存的异步缓存方法.实验结果表明,经过异步缓存方法优化后的混合索引读性能是优化前的1.8倍,此外,经过异步缓存优化后的持久化索引最多可以降低50%的读延迟.     

Unimem: Runtime Data Management on Non-Volatile Memory-Based Heterogeneous Main Memory for High Performance Computing

Non-volatile memory(NVM)provides a scalable and power-efficient solution to replace dynamic random access memory(DRAM)as main memory.However,because of the relatively high latency and low bandwidth of NVM,NVM is often paired with DRAM to build a heterogeneous memory system(HMS).As a result,data objects of the application must be carefully placed to NVM and DRAM for the best performance.In this paper,we introduce a lightweight runtime solution that automatically and transparently manages data placement on HMS without the requirement of hardware modifications and disruptive change to applications.Leveraging online profiling and performance models,the runtime solution characterizes memory access patterns associated with data objects,and minimizes unnecessary data movement.Our runtime solution effectively bridges the performance gap between NVM and DRAM.We demonstrate that using NVM to replace the majority of DRAM can be a feasible solution for future HPC systems with the assistance of a software-based data management.     

基于DRAM牺牲Cache的异构内存页迁移机制

当海量数据请求访问异构内存系统时,异构内存页在动态随机存储器(dynamic random access memory,DRAM)和非易失性存储器(non-volatile memory,NVM)之间进行频繁的往返迁移.然而,应用于传统内存页的迁移策略难以适应内存页"冷""热"度的快速动态变化,这使得从DRAM迁移至N...     

Energy efficient task allocation for hybrid main memory architecture

Compared with the conventional dynamic random access memory (DRAM), emerging non-volatile memory technologies provide better density and energy efficiency. However, current NVM devices typically suffer from high write power, long write latency and low write endurance. In this paper, we study the task allocation problem for the hybrid main memory architecture with both DRAM and PRAM, in order to leverage system performance and the energy consumption of the memory subsystem via assigning different memory devices for each individual task. For an embedded system with a static set of periodical tasks, we design an integer linear programming (ILP) based offline adaptive space allocation (offline-ASA) algorithm to obtain the optimal task allocation. Furthermore, we propose an online adaptive space allocation (online-ASA) algorithm for dynamic task set where arrivals of tasks are not known in advance. Experimental results show that our proposed schemes achieve 27.01% energy saving on average, with additional performance cost of 13.6%.     

Pmfs中目录项索引的实现

可字节寻址的非易失存储介质,如相变存储器等,使数据可以在内存级别持久化。由于非易失存储器（NVM）本身的读写延时非常低,系统软件开销成为了决定整个持久化内存系统性能的主要因素。Pmfs是一个专门为持久化内存所设计的文件系统,然而,Pmfs下的每个目录操作（打开、创建或删除）都会遍历目录下的所有目录项,导致了随文件数增长而线性增长的目录项查找开销。通过测试发现,在特定类型负载下这种开销成为了整个文件系统的瓶颈。针对该问题,在Pmfs中实现了持久化的目录项索引来加速目录操作。测试结果显示,基于单目录下100000文件的负载,该优化使得文件创建速度提高了12倍,带宽增加了27.3%。     

面向DRAM和NVM异构混合内存架构的排序连接算法优化

随着计算机技术的高速发展,数据的应用规模也在不断扩大,各行各业对于数据存取速度的要求也越来越高.为了满足这种需求,内存数据库的思想被提出,然而传统的内存存储器DRAM由于密度和能耗的限制无法大规模集成和扩展.与此同时,非易失内存(NVM)以其性能高、密度高、能耗低的优势弥补了DRAM的不足.DRAM和NVM结合在一起组...     

Prober: exploiting sequential characteristics in buffer for improving SSDs write performance

Solid state disks (SSDs) are becoming one of the mainstream storage devices due to their salient features, such as high read performance and low power consumption. In order to obtain high write performance and extend flash lifespan, SSDs leverage an internal DRAM to buffer frequently rewritten data to reduce the number of program operations upon the flash. However, existing buffer management algorithms demonstrate their blank in leveraging data access features to predict data attributes. In various real-world workloads, most of large sequential write requests are rarely rewritten in near future. Once these write requests occur, many hot data will be evicted from DRAM into flash memory, thus jeopardizing the overall system performance. In order to address this problem, we propose a novel large write data identification scheme, called Prober. This scheme probes large sequential write sequences among the write streams at early stage to prevent them from residing in the buffer. In the meantime, to further release space and reduce waiting time for handling the incoming requests, we temporarily buffer the large data into DRAM when the buffer has free space, and leverage an actively write-back scheme for large sequential write data when the flash array turns into idle state. Experimental results demonstrate that our schemes improve hit ratio of write requests by up to 10%, decrease the average response time by up to 42% and reduce the number of erase operations by up to 11%, compared with the state-of-the-art buffer replacement algorithms.     

NVRC:一种面向NVM的写限制日志方案

非易失性内存(Non-Volatile Memory,NVM)具有支持按字节寻址、持久性、存储密度高、读写延迟低等特点,因此成为解决DRAM(Dynamic Random Access Memory)容量有限问题的首选技术。随着数据库系统中NVM的引入,传统的日志技术需要考虑如何适应NVM特性。首先总结了已有的面向NVM的日志技术研究,进而提出了一种尽可能限制NVM写操作的数据库日志方案NVRC(Non-Volatile Record-updating with Cacheline)。文中提出了结合异地更新和原地更新的日志管理方案。具体而言,NVRC在异地更新的“影子记录”的基础上,引入了“缓存行原地更新”策略,并通过代价分析选择合理的日志更新策略,从而减少对NVM的写操作。采用DRAM模拟NVM的方式在YCSB测试负载上进行了实验,并对比了NVRC与传统的WAL(Write Ahead Log)以及NVM感知的PCMLx(PCMLoggingx)方法。结果表明,NVRC的NVM写次数在修改均匀的情况下比WAL和PCMLx分别减少了54%和17%,同时更新性能分别提升了59%和10%。     

WOBTree: a write-optimized B+-tree for non-volatile memory

The emergence of non-volatile memory (NVM) has introduced new opportunities for performance optimizations in existing storage systems. To better utilize its byte-addressability and near-DRAM performance, NVM can be attached on the memory bus and accessed via load/store memory instructions rather than the conventional block interface. In this scenario, a cache line (usually 64 bytes) becomes the data transfer unit between volatile and non-volatile devices. However, the failureatomicity of write on NVM is the memory bit width (usually 8 bytes). This mismatch between the data transfer unit and the atomicity unit may introduce write amplification and compromise data consistency of node-based data structures such as B+-trees. In this paper, we propose WOBTree, a Write-Optimized B+-Tree for NVM to address the mismatch problem without expensive logging. WOBTree minimizes the update granularity from a tree node to a much smaller subnode and carefully arranges the write operations in it to ensure crash consistency and reduce write amplification. Experimental results show that compared with previous persistent B+-tree solutions, WOBTree reduces the write amplification by up to 86× and improves write performance by up to 61× while maintaining similar search performance.     

基于NVM和HTM的低时延事务处理

硬件事务内存(hardware transactional memory,HTM)能够极大地提升多核内存事务处理的吞吐.然而,为了避免慢速持久化设备对事务吞吐的影响,现有系统以批量的方式提交事务,这使得事务提交有极高的延迟.低时延非易失性内存(non-volatile memory,NVM)的出现,给降低基于HTM的内...     

非易失性内存安全技术综述

大数据应用对内存容量的需求越来越大，而在大数据应用中，以动态随机存储器为内存介质的传统存储器所凸显出来的问题也越来越严重。计算机设计者们开始考虑用非易失性内存去替代传统的动态随机存储器内存。非易失性内存作为非易失的存储介质，不需要动态刷新，因此不会引起大量的能量消耗；此外，非易失性内存的读性能与动态随机存储器相近，且非易失性内存单个存储单元的容量具有较强的可扩展性。但将非易失性内存作为内存集成到现有的计算机系统中，需要解决其安全性问题。传统的动态随机存储器作为内存介质掉电后数据会自动丢失，即数据不会在存储介质中驻留较长时间，而当非易失性内存作为非易失性存储介质时，数据可以保留相对较久的时间。若攻击者获得了非易失性内存存储器的访问权，扫描存储内容，便可以获取内存中的数据，这一安全性问题被定义为数据的“恢复漏洞”。因此，在基于非易失性内存模组的数据中心环境中，如何充分有效地利用非易失性内存，并保证其安全性，成为迫切需要解决的问题。该文从非易失性内存的安全层面出发，对近年来的研究热点及进展进行介绍。首先，该文总结了非易失性内存所面临的主要安全问题，如数据窃取、完整性破坏、数据一致性与崩溃恢复，以及由加解密和完整性保护技术引入而导致的系统性能下降等问题。然后，针对上述各问题，对组合计数器模式加密技术、完整性保护技术扩展的默克尔树、数据一致性与崩溃恢复技术，以及相关优化方案作了详细介绍。最后，对全文进行了总结，并对非易失性内存未来需要进一步关注的问题进行了展望。     

支持高并发访问的新型NVM存储系统

I/O系统软件栈是影响NVM存储系统性能的重要因素。针对NVM存储系统的读写速度不均衡、写寿命有限等问题，设计了同异步融合的访问请求管理策略；在使用异步策略管理数据量较大的写操作的同时，仍然使用同步策略管理读请求和少量数据的写请求。针对多核处理器环境下不同计算核心访问存储系统时地址转换开销大的问题，设计了面向多核处理器地址转换缓存策略，减少地址转换的时间开销。最后实现了支持高并发访问NVM存储系统（CNVMS）的原型，并使用通用测试工具进行了随机读写、顺序读写、混合读写和实际应用负载的测试。实验结果表明，与PMBD相比，所提策略能提高1%~22%的读写速度和9%~15%的IOPS，验证了CNVMS策略能有效提高NVM存储系统的I/O性能和访问请求处理速度。     

Reducing Transaction Processing Latency in Hardware Transactional Memory-based Database with Non-volatile Memory

The emergency of Hardware Transactional Memory (HTM) has greatly boosted the transaction processing performance in in-memory databases. However, the group commit protocol, aiming at reducing the impact from slow storage devices, leads to high transaction commit latency. Non-Volatile Memory (NVM) opens opportunities for reducing transaction commit latency. However, HTM cannot cooperate with NVM together: flushing data to NVM will always cause HTM to abort. In this paper, we propose a technique called parity version to decouple the process of HTM execution and NVM write. Thus, the transactions can correctly and efficiently use NVM to reduce their commit latency with HTM. We have integrated this technique into DBX, a state-of-the-art HTM-based database, and propose DBXN: a low-latency and high-throughput in-memory transaction processing system. Evaluations using typical OLTP workloads including TPC-C show that it has 99% lower latency and 2.1 times higher throughput than DBX.     

An energy-efficient encryption mechanism for NVM-based main memory in mobile systems

Emerging non-volatile memory (NVM) has been considered as the most promising candidate of DRAM for future main memory design in mobile devices. NVM-based main memory exhibits attractive features, such as byte-addressability, low standby power, high density and near DRAM performance. However, the nature of non-volatility makes NVM vulnerable to be attacked by malicious programs. Though several data encryption techniques have been proposed to solve this problem, they do not consider the limited resources in mobile systems. To address this issue, in this paper, we propose an energy-efficient encryption mechanism, named MobiLock, to effectively enhance the security of NVM-based main memory in mobile systems. The basic idea is to enhance the encryption and decryption performance by utilizing cache and concurrency mechanisms, respectively. To achieve this, we first develop a cache mechanism to cache the encrypted intermediate data (i.e., PAD) whose plaintexts are updated frequently, for accelerating decryption and reducing recomputation of PAD. We then propose a concurrency mechanism to read the ciphertext in NVM and calculate the PAD simultaneously, to reduce the decryption latency. The evaluation results show that our technique can effectively reduce encryption energy consumption and decryption latency, respectively.     

内存体系划分技术的研究与发展

在多核计算机时代,多道程序在整个共享内存体系上的“访存干扰”是制约系统总体性能和服务质量的重要因素.即使当前内存资源已相对丰富,但如何优化内存体系的性能、降低访存干扰并高效地管理内存资源,仍是计算机体系结构领域的研究热点.为深入研究该问题,详述将“页着色(pagecoloring)”内存划分技术应用于整个内存体系(包括Cache、内存通道以及内存DRAM Bank),进而消除了并行多道程序在共享内存体系上的访存干扰的一系列先进方法.从DRAM Bank、Channel与Cache以及非易失性内存(non-volatile memory, NVM)等内存体系中介质为切入点,层次分明地展开论述:首先,详述将页着色应用于多道程序在DRAM Bank与通道的划分,消除多道程序间的访存冲突;随后是将页着色应用于在内存体系中Cache和DRAM的“垂直”协同划分,可同时消除多级内存介质上的访存干扰;最后是将页着色应用于包含NVM的混合内存体系,以提高程序运行效率和系统整体效能.实验结果表明,所提内存划分方法提高了系统整体性能(平均5%-15%)、服务质量(QoS),并有效地降低了系统能耗.通过梳理...     

Exploiting write power asymmetry to improve phase change memory system performance

Phase change memory (PCM) is a promising candidate to replace DRAM as main memory, thanks to its better scalability and lower static power than DRAM. However, PCM also presents a few drawbacks, such as long write latency and high write power. Moreover, the write commands parallelism of PCM is restricted by instantaneous power constraints, which degrades write bandwidth and overall performance. The write power of PCM is asymmetric: writing a zero consumes more power than writing a one. In this paper, we propose a new scheduling policy, write power asymmetry scheduling (WPAS), that exploits the asymmetry of write power. WPAS improveswrite commands parallelism of PCM memory without violating power constraint. The evaluation results show that WPAS can improve performance by up to 35.5%, and 18.5% on average. The effective read latency can be reduced by up to 33.0%, and 17.1% on average.     

Reorder Write Sequence by Hetero-Buffer to Extend SSD’s Lifespan

The limited lifespan is the Achilles’ heel of solid state drives(SSDs) based on NAND flash.NAND flash has two drawbacks that degrade SSDs’ lifespan.One is the out-of-place update.Another is the sequential write constraint within a block.SSDs usually employ write buffer to extend their lifetime.However,existing write buffer schemes only pay attention to the first drawback,while neglect the second one.We propose a hetero-buffer architecture covering both aspects simultaneously.The hetero-buffer consists of two components,dynamic random access memory(DRAM) and the reorder area.DRAM endeavors to reduce write traffic as much as possible by pursuing a higher hit ratio(overcome the first drawback).The reorder area focuses on reordering write sequence(overcome the second drawback).Our hetero-buffer outperforms traditional write buffers because of two reasons.First,the DRAM can adopt existing superior cache replacement policy,thus achieves higher hit ratio.Second,the hetero-buffer reorders the write sequence,which has not been exploited by traditional write buffers.Besides the optimizations mentioned above,our hetero-buffer considers the work environment of write buffer,which is also neglected by traditional write buffers.By this way,the hetero-buffer is further improved.The performance is evaluated via trace-driven simulations.Experimental results show that,SSDs employing the hetero-buffer survive longer lifespan on most workloads.     

一种基于时间戳的高扩展性的持久性软件事务内存

新兴的非易失性内存(non-volatile memory,NVM)具有字节寻址、持久性、大容量和低功耗等优点,然而,在NVM上进行并发编程往往比较困难,用户既要保证数据的崩溃一致性又要保证并发的正确性.为了降低用户开发难度,研究人员提出持久性事务内存方案,但是现有持久性事务内存普遍存在扩展性较差问题.测试发现限制扩展性的关键因素在于全局逻辑时钟和冗余NVM写操作.针对这2个方面,提出了线程逻辑时钟方法,通过允许每个线程拥有一个独立时钟,消除全局逻辑时钟中心化问题;提出了缓存行感知的双版本方法,为数据维护2个版本,通过循环更新这2个版本来保证数据的崩溃一致性,从而消除冗余的NVM写操作.基于所提出的这2个方法,实现了一个基于时间戳的高扩展的持久性软件事务内存(scalable durable transactional memory,SDTM),对比测试显示,在YCSB负载下,与DudeTM和PMDK相比,SDTM的性能最多分别提高了2.8倍和29倍.     

NVM Storage in IoT Devices: Opportunities and Challenges

Edge storage stores the data directly at the data collection point, and does not need to transmit the collected data to the storage central server through the network. It is a critical technology that supports applications such as edge computing and 5G network applications, with lower network communication overhead, lower interaction delay and lower bandwidth cost. However, with the explosion of data and higher real-time requirements, the traditional Internet of Things (IoT) storage architecture cannot meet the requirements of low latency and large capacity. Non-volatile memory (NVM) presents new possibilities regarding this aspect. This paper classifies the different storage architectures based on NVM and compares the system goals, architectures, features, and limitations to explore new research opportunities. Moreover, the existing solutions to reduce the write latency and energy consumption and increase the lifetime of NVM IoT storage devices are analyzed. Furthermore, we discuss the security and privacy issues of IoT devices and compare the mainstream solutions. Finally, we present the opportunities and challenges of building IoT storage systems based on NVM.