CMOS: compatible wafer bonding for MEMS and wafer-level 3D integration

Wafer bonding became during past decade an important technology for MEMS manufacturing and wafer-level 3D integration applications. The increased complexity of the MEMS devices brings new challenges to the processing techniques. In MEMS manufacturing wafer bonding can be used for integration of the electronic components (e.g. CMOS circuitries) with the mechanical (e.g. resonators) or optical components (e.g. waveguides, mirrors) in a single, wafer-level process step. However, wafer bonding with CMOS wafers brings additional challenges due to very strict requirements in terms of process temperature and contamination. These challenges were identified and wafer bonding process solutions will be presented illustrated with examples.     

Flexible integration of MEMS and IC for low-cost production of wireless sensor nodes

In this paper, we proposed a flexible process for size-free MEMS and IC integration with high efficiency for MEMS ubiquitous applications in wireless sensor network. In this approach, MEMS and IC can be fabricated individually by different wafers. MEMS and IC known-good-dies (KGD) are temporarily bonded onto carrier wafer with rapid and high-accurate self-alignment by using fine pattern of hydrophobic surface assembled monolayer and capillary force of H₂O; and then KGD are de-bonded from carrier wafer and transferred to target wafer by wafer level permanent bonding with plasma surface activation to reduce bonding temperature and load force. By applying above 2-step process, size of both wafer and chip could be flexible selected. Besides, CMOS processed wafer or silicon interposer can be used as the target wafer. This approach offers us excellent process flexibilities for low-cost production of wireless sensor nodes.     

Low-temperature wafer-level transfer bonding

In this paper, we present a new wafer-level transfer bonding technology. The technology can be used to transfer devices or films from one substrate wafer (sacrificial device wafer) to another substrate wafer (target wafer). The transfer bonding technology includes only low-temperature processes; thus, it is compatible with integrated circuits. The process flow consists of low-temperature adhesive bonding followed by sacrificially thinning of the device wafer. The transferred devices/films can be electrically interconnected to the target wafer (e.g., a CMOS wafer) if required. We present three example devices for which we have used the transfer bonding technology. The examples include two polycrystalline silicon structures and a test device for temperature coefficient of resistance measurements of thin-film materials. One of the main advantages of the new transfer bonding technology is that transducers and integrated circuits can be independently processed and optimized on different wafers before integrating the transducers on the integrated circuit wafer. Thus, the transducers can be made of, e.g., monocrystalline silicon or other high-temperature annealed, high-performance materials. Wafer-level transfer bonding can be a competitive alternative to flip-chip bonding, especially for thin-film devices with small feature sizes and when small electrical interconnections (<3×3 μm²) between the devices and the target wafer are required     

Low temperature Si/Si wafer direct bonding using a plasma activated method

Manufacturing and integration of micro-electro-mechanical systems (MEMS) devices and integrated circuits (ICs) by wafer bonding often generate problems caused by thermal properties of materials. This paper presents a low temperature wafer direct bonding process assisted by O₂ plasma. Silicon wafers were treated with wet chemical cleaning and subsequently activated by O₂ plasma in the etch element of a sputtering system. Then, two wafers were brought into contact in the bonder followed by annealing in N₂ atmosphere for several hours. An infrared imaging system was used to detect bonding defects and a razor blade test was carried out to determine surface energy. The bonding yield reaches 90%–95% and the achieved surface energy is 1.76 J/m² when the bonded wafers are annealed at 350 °C in N₂ atmosphere for 2 h. Void formation was systematically observed and elimination methods were proposed. The size and density of voids greatly depend on the annealing temperature. Short O₂ plasma treatment for 60 s can alleviate void formation and enhance surface energy. A pulling test reveals that the bonding strength is more than 11.0 MPa. This low temperature wafer direct bonding process provides an efficient and reliable method for 3D integration, system on chip, and MEMS packaging.     

Arrays of monocrystalline silicon micromirrors fabricated using CMOS compatible transfer bonding

In this paper, we present CMOS compatible fabrication of monocrystalline silicon micromirror arrays using membrane transfer bonding. To fabricate the micromirrors, a thin monocrystalline silicon device layer is transferred from a standard silicon-on-insulator (SOI) wafer to a target wafer (e.g., a CMOS wafer) using low-temperature adhesive wafer bonding. In this way, very flat, uniform and low-stress micromirror membranes made of monocrystalline silicon can be directly fabricated on top of CMOS circuits. The mirror fabrication does not contain any bond alignment between the wafers, thus, the mirror dimensions and alignment accuracies are only limited by the photolithographic steps. Micromirror arrays with 4/spl times/4 pixels and a pitch size of 16 /spl mu/m/spl times/16 /spl mu/m have been fabricated. The monocrystalline silicon micromirrors are 0.34 /spl mu/m thick and have feature sizes as small as 0.6 /spl mu/m. The distance between the addressing electrodes and the mirror membranes is 0.8 /spl mu/m. Torsional micromirror arrays are used as spatial light modulators, and have potential applications in projection display systems, pattern generators for maskless lithography systems, optical spectroscopy, and optical communication systems. In principle, the membrane transfer bonding technique can be applied for integration of CMOS circuits with any type of transducer that consists of membranes and that benefits from the use of high temperature annealed or monocrystalline materials. These types of devices include thermal infrared detectors, RF-MEMS devices, tuneable vertical cavity surface emitting lasers (VCSEL) and other optical transducers.     

Stamp-and-stick room-temperature bonding technique for microdevices

Multilayer MEMS and microfluidic designs using diverse materials demand separate fabrication of device components followed by assembly to make the final device. Structural and moving components, labile bio-molecules, fluids and temperature-sensitive materials place special restrictions on the bonding processes that can be used for assembly of MEMS devices. We describe a room temperature "stamp and stick (SAS)" transfer bonding technique for silicon, glass and nitride surfaces using a UV curable adhesive. Alternatively, poly(dimethylsiloxane) (PDMS) can also be used as the adhesive; this is particularly useful for bonding PDMS devices. A thin layer of adhesive is first spun on a flat wafer. This adhesive layer is then selectively transferred to the device chip from the wafer using a stamping process. The device chip can then be aligned and bonded to other chips/wafers. This bonding process is conformal and works even on surfaces with uneven topography. This aspect is especially relevant to microfluidics, where good sealing can be difficult to obtain with channels on uneven surfaces. Burst pressure tests suggest that wafer bonds using the UV curable adhesive could withstand pressures of 700 kPa (7 atmospheres); those with PDMS could withstand 200 to 700 kPa (2-7 atmospheres) depending on the geometry and configuration of the device.     

Wafer-level bonding and direct electrical interconnection of stacked 3D MEMS by a hybrid low temperature process

The presented fabrication technology enables the direct integration of electrical interconnects during low temperature wafer bonding of stacked 3D MEMS and wafer-level packaging. The low temperature fabrication process is based on hydrophilic direct bonding of plasma activated Si/SiO₂ surfaces and the simultaneous interconnection of two metallization layers by eutectic bonding of ultra-thin AuSn connects. This hybrid wafer-level bonding and interconnection technology allows for the integration of metal interconnects and multiple materials in stacked MEMS devices. The process flow is successfully validated by fabricating test structures made out of a two wafer stack and featuring multiple ohmic electrical interconnects.     

A new approach for handling and transferring of thin semiconductor materials

 Based on the fracture mechanics analysis of crack propagation, the phenomenon of subcritical crack growth was utilized for a controlled debonding of directly wafer-bonded interfaces. The approach allowed the well-defined separation of bonded wafers although the bond strength was high due to thermal annealing. The achieved splitting velocity depended on the wafer material, the wafer thickness ratio, the bonding process parameters, and the environmental conditions during cleaving. In combination with wafer bonding, the method can be used for a temporary stiffening and handling of thin and brittle wafers during fabrication, even if the wafers are exposed to high process temperatures. The approach can also be applied to fabricate micromechanical systems (MEMS). Received: 12 July 2001/Accepted: 26 February 2002 This paper was presented at the Conference of Micro System Technologies 2001 in March 2001.     

InP dies transferred onto silicon substrate for optical interconnects application

We bonded quantum well InP dies on a photonic layer transferred on silicon CMOS processed wafer using direct molecular bonding. This approach is suitable for new applications, viz., photonics on silicon, 3D packaging and integrated sensors. The chips are diced from a bulk substrate and bonded directly onto a silicon substrate without any organic nor metallic adhesive layer. A thin silicon dioxide layer can be added on both assembled surfaces to enhance bonding quality. After bonding, the dies can mechanically be thinned down to 20 μm and chemically etched. The InAsP quantum well stack of the InP dies keeps its optoelectronics features and performances after being transferred onto a silicon substrate.     

Adhesive bonding with SU-8 in a vacuum for capacitive pressure sensors

This paper describes a method for fabricating capacitive pressure sensors through the use of adhesive bonding with SU-8 in a vacuum. The influence of different parameters on the bonding of structured wafers was investigated. It was found that pre-bake time, pumping time, and the thickness of the crosslink layer are the most important factors for successful bonding. Bonding quality was evaluated by inspection through the transparent glass of the sensor and through the use of an SEM photograph, with 90% of the area successfully bonded and an ultimate yield of 70% of the sensors. The measured bonding strength was 17.15 MPa and 19.6 MPa for wafers bonded in 80 °C and 100 °C, respectively. The pressure–capacitance characteristic test results show that this bonding process is a viable micro electro mechanical systems (MEMS) fabrication technology for cavity sealing in a vacuum.     

Wafer‐scale monolithic hybrid integration of Si‐based IC and III–V epi‐layers—A mass manufacturable approach for active matrix micro‐LED micro‐displays

Hybridization of silicon integrated circuits (ICs) with compound semiconductor device arrays are crucial for making functional hybrid chips, which are found to have enormous applications in many areas. Although widely used in manufacturing hybrid chips, the flip‐chip technology suffers from several limitations that are difficult to overcome, especially when the demand is raised to make functional hybrid chips with higher device array density without sacrificing the chip footprint. To address those issues, Beida Jade Bird Display Limited has developed its unique wafer‐level monolithic hybrid integration technology and demonstrated its advantages in making large‐scale hybrid integration of functional device arrays on Si IC wafers. Active matrix micro‐light‐emitting diode micro‐displays with a resolution of 5000+ pixel per inch were successfully fabricated using Beida Jade Bird Display Limited's monolithic hybrid integration technology. The general fabrication method is described, and the result is presented in this paper. The fabricated monochromatic micro‐light‐emitting diode micro‐displays exhibit improved device performance than do other micro‐display technologies and have great potentials in applications such as portable projectors and near‐to‐eye projection for augmented reality. More importantly, the wafer‐scale monolithic hybrid integration technology offers a clear path for low‐cost mass production of hybrid optoelectronic IC chips.     

Micromachining of buried micro channels in silicon

A new method for the fabrication of micro structures for fluidic applications, such as channels, cavities, and connector holes in the bulk of silicon wafers, called buried channel technology (BCT), is presented in this paper. The micro structures are constructed by trench etching, coating of the sidewalls of the trench, removal of the coating at the bottom of the trench, and etching into the bulk of the silicon substrate. The structures can be sealed by deposition of a suitable layer that closes the trench. BCT is a process that can be used to fabricate complete micro channels in a single wafer with only one lithographic mask and processing on one side of the wafer, without the need for assembly and bonding. The process leaves a substrate surface with little topography, which easily allows further processing, such as the integration of electronic circuits or solid-state sensors. The essential features of the technology, as well as design rules and feasible process schemes, will be demonstrated on examples from the field of μ-fluidics     

M-TEST: A test chip for MEMS material property measurement usingelectrostatically actuated test structures

A set of electrostatically actuated microelectromechanical test structures is presented that meets the emerging need for microelectromechanical systems (MEMS) process monitoring and material property measurement at the wafer level during both process development and manufacturing. When implemented as a test chip or drop-in pattern for MEMS processes, M-Test becomes analogous to the electrical MOSFET test structures (often called E-Test) used for extraction of MOS device parameters. The principle of M-Test is the electrostatic pull-in of three sets of test structures [cantilever beams (CB's), fixed-fixed beams (FB's), and clamped circular diaphragms (CD's)] followed by the extraction of two intermediate quantities (the S and B parameters) that depend on the product of material properties and test structure geometry. The S and B parameters give a direct measure of the process uniformity across an individual wafer and process repeatability between wafers and lots. The extraction of material properties (e.g., Young's modulus, plate modulus, and residual stress) from these S and B parameters is then accomplished using geometric metrology data. Experimental demonstration of M-Test is presented using results from MIT's dielectrically isolated wafer-bonded silicon process. This yielded silicon plate modulus results which agreed with literature values to within ±4%. Guidelines for adapting the method to other MEMS process technologies are presented     

Wafer direct bonding with ambient pressure plasma activation

Ambient pressure plasma processes were applied for surface activation of semiconductor (Si, Ge and GaAs) and other wafers (glass) before direct wafer bonding for MEMS and engineered substrates. Surface properties of activated wafers were analysed. Caused by activation high bond energies were obtained for homogeneous (e.g. Si/Si) as well as for heterogeneous material combinations (for instance Si/Ge) after a subsequent low temperature annealing process at 200°C. The resulting bond energies are analogous or higher as obtained for low-pressure plasma activation processes. The advantages of the ambient pressure plasma processes are described; a technical solution is discussed demonstrating the low risk for contamination and radiation damage.     

Microrivets for MEMS packaging: concept, fabrication, and strengthtesting

Microriveting is introduced as a novel and alternative joining technique to package MEMS devices. In contrast to the existing methods, mostly surface bonding, the reported technique joins two wafer pieces together by riveting, a mechanical joining means. Advantages include wafer joining at room temperature and low voltage, and relaxed requirements for surface preparation. The microrivets, which hold a cap-base wafer pair together, are formed by filling rivet holes through electroplating. The cap wafer has a recess to house the MEMS devices and also has through-holes to serve as rivet molds. The seed layer on the base wafer becomes the base of the rivet. The process requires only simple mechanical clamping of the wafer pair during riveting, compared with the more involved procedures needed for wafer bonding. Directionality of electroplating in an electric field is what makes this process simple and robust. Strength testing is carried out to evaluate the joining with microrivets. Different modes of rivet failure under different loading conditions are identified and investigated. Effective strength between 7 and 11 MPa was measured under normal loading with nickel microrivets. Joining strengths comparable to conventional wafer bonding processes, ease of fabrication with repeatability, and compatibility with batch fabrication show that microriveting is a feasible technique to join wafers for MEMS packaging, especially when hermetic sealing is not essential     

Low temperature wafer bonding for thin silicon film transfer

In this work, we investigate the low temperature (<200 °C) wafer bonding using wet chemical surface activation and we demonstrate high bonding strength sufficient to achieve the transfer of a thin silicon film of thickness less than 400 nm on top of another silicon wafer using spin-on-glass (SOG) film as an intermediate layer. The process developed is the first critical step that can enable three-dimensional (3D) integration and wafer level packaging of MEMS with electronic circuits.     

Wafer- and piece-wise Si tip transfer technologies for applicationsin scanning probe microscopy

A novel tip transfer technology is proposed for applications in scanning probe microscopy (SPM). The technology is based on the concept of fabricating tips on an independent wafer and transferring them onto the target wafer. The transfer is also feasible on a full 4-in wafer scale. This is especially attractive for postprocessing CMOS wafers, e.g., for atomic force microscopy chips with integrated electronics. A yield of more than 90% has been achieved in a first experimental set-up. Moreover, a piece-wise tip transfer onto a free-standing cantilever is also shown. During this transfer, the tip is completely encapsulated in a resist post and, hence, protected against mechanical impact. This technology can be applied not only to SPM probe fabrication but also to create a new kind of MEMS device     

Functional testing and characterisation of (bio-)chemical sensors on wafer level

An automated computer-assisted system for the functional testing and characterisation of (bio-)chemical sensors on wafer level is developed and integrated into a commercial prober station. The system enables the identification and selection of “good” sensors on wafer level and thus, allows to avoid further expensive bonding, encapsulation and packaging processes for defective or non-functioning sensor structures. Moreover, a specifically designed flow-through electrochemical microcell offers the possibility of wafer-level characterisation of (bio-)chemical sensors in terms of sensitivity, drift, hysteresis and response time at an early process stage. The system has been exemplarily tested using wafers combining pH-sensitive capacitive electrolyte-insulator-semiconductor structures as well as ion-sensitive field-effect transistors with different geometrical sizes and gate layouts.     

Discussion of tooling solutions for the direct bonding of silicon wafers

Silicon-to-silicon fusion (or direct) pre-bonding is an important enabling technology for many emerging microelectronics and MEMS technologies. A silicon–silicon direct bond can be easily formed, where the wafer surfaces are highly flat and very clean (Tong and Gosele), however for practical structured MEMS devices, wafer bow and local roughness may be compromised such that it is no longer a trivial task to achieve a direct bond. Tooling has been developed to facilitate the in situ alignment and bonding of silicon-to-silicon wafers in a vacuum chamber. The rate and direction of the bond propagation are controlled, thus minimising the occurrence of non-particle related voids. The tooling system also allows wafers with “non-ideal” surfaces or warped profiles to be bonded, by maximising the area across which bonding occurs and providing in situ annealing. The ability to anneal the wafers while maintaining clamping force creates attractive forces high enough to overcome the mechanical repulsive forces between the wafers and maintain a permanent bond. The tooling system can also be configured to give control over the bow or residual stress in the bonded pair, a factor that is critical in multi-stack direct wafer bonding.     

Precision passive mechanical alignment of wafers

A passive mechanical wafer alignment technique, capable of micron and better alignment accuracy, was developed, fabricated and tested. This technique is based on the principle of elastic averaging: It uses mating pyramid (convex) and groove (concave) elements, which have been previously patterned on the wafers, to passively align wafers to each other as they are stacked. The concave and convex elements were micro machined on 4-in (100) silicon wafers using wet anisotropic (KOH) etching and deep reactive ion etching. Submicron repeatability and accuracy on the order of one micron were shown through testing. Repeatability and accuracy were also measured as a function of the number of engaged elements. Submicrometer repeatability was achieved with as little as eight mating elements. Potential applications of this technique are precision alignment for bonding of multiwafer MEMS devices and three-dimensional (3-D) interconnect integrated circuits (ICs), as well as one-step alignment for simultaneous bonding of multiple wafer stacks. Future work will focus on minimizing the size of the elements.