降低SDH网络指针调整引入抖动的有效方法

本文首先介绍了抖动的基本概念以及ＳＤＨ系统指针调整引入抖动的机理；接着着重讨论了降低ＳＤＨ网络指针调整引入抖动的原理并给出ＰＬＬ型去同步器和两种新型去同步器；最后指出采用上述原理的去同步器，在其ＳＤＨ系统中高达４．６ｐｐｍ时钟频漂情况下可使输出抖动降至０．６ＵＩ以下。     

降低SDH网络指针调整引人抖动的有效方法

本文首先介绍了抖动的基本概念以及ＳＤＨ系统指针调整引入抖动的机理；接着着重讨论了降低ＳＤＨ网络指针调整引入抖动的大批量并给出ＰＬ型去同步器和两种新型去同步器；最后指出采用上述原理的去同步器，在其ＳＤＨ系统中高达４．６ｐｐｍ时钟频漂情况下可使输出抖动降至０．６ＵＩ以下。     

SDH指针调整技术的研究

本文首先讲述了ＳＤＨ的指针调整原理,并举例说明了指针调整时指针字节各比特状态的变化过程,接着论述了指针调整对ＰＤＨ支路信号所造成的传输损伤,介绍了一种减小指针调整引入抖动的解同步器,讨论了ＳＤＨ／ＰＤＨ混合网抖动累积的统计规律。     

一种比特泄漏的优化方案——调制前馈泄漏法

ＳＤＨ指针调整引起的抖动是ＳＤＨ网中重要的传输损伤,如何抑制指针调整引起的抖动已经成为ＳＤＨ系统设计中一个关键的问题,本文提出一种能有效减低抖动的方法－调制前馈泄漏法,并对这种方法进行了理论分析和计算。     

SDH中的指针调整对PDH信号的抖动损伤

光同步数字传输网由于采用指针调整技术进步同步复用，可能会给经由ＳＤＨ传送的准同步数字信号带来较大的抖动损伤。道德给出了计算机模拟计算ＳＤＨ指针调整在ＰＤＨ信号上产生抖动的方法及其模拟结果，然后对这种抖动进行了理论分析。     

有线电视在SDH网中传输的若干问题

由于工作的原因 ,参加了某省广电系统有线电视ＳＤＨ传输网的建设 ,在整个网络的设计和施工过程中发现有线电视在ＳＤＨ网络中传输有以下几个问题需要加以注意。1　时钟与同步(1)ＳＤＨ网中信号的同步机理是采用指针调整 ,通过指针调整进行信号的相位校准 ,它不同于ＰＤＨ所采用的正 /负码速调整技术。在ＳＤＨ网中可能出现ＳＤＨ线路抖动。同步分配网中由于随机噪声引起同步信号的漂移及ＰＤＨ码速调整技术的不同 ,ＰＤＨ支路信号映射至ＳＤＨ信号时信号发生相位变化 ,在ＰＤＨ/ＳＤＨ边界上引起附加抖动和漂移 ,对视频信号而言 ,将造成可…     

一种减小SDH指针调整抖动的方法

ＳＤＨ指针调整抖动是ＳＤＨ网的主要传输损伤之一，如何抑制它已成为研究ＳＤＨ的关键技术之一。文中提出一种新的抑制指针调整抖动的方法－－数字滤波法，并分析了它的原理和实现方法，最后给出了模拟结果。     

SDH网中两种特有抖动的产生及其测试

本文分析和论述了ＳＤＨ网中的去映射抖动和指针调整抖动的产生机理及其特性，并提供了一种典型测试方法。     

PDH信号在SDH和PDH混合网中传输时指针调整抖动的积累规律

道德介绍了用计算机模拟计算ＳＤＨ提针调整抖动的方法，并给出了模拟结果。然后，在采用了抑制指针高速抖动的自适应比特泄漏技术的基础上，研究了ＰＤＨ信号在ＳＤＨ和ＰＤＨ混合网中传输时指针调整拌动的积累规律。     

SDH网指针调整的影响

本文阐述ＳＤＨ网指针调整对ＰＤＨ支路输出抖动和漂摆，对网同步，以及对抖动测试技术的影响。     

干扰抖动的非线性损伤及抑制方法

输入抖动与码速调整过程的非线性相互作用，将会产生一种低频的干扰抖动。这一干扰抖动的存在，会使近年来提出的减小抖动方法的抖动转移特性劣化。本文提出干扰抖动的概念，讨论了干扰抖动产生的机理。结果表明，当输入码流中有与塞入率相近频率的输入抖动时，由于非线性效应会产生较大的低频干扰抖动损伤。文中分析了干扰抖动下的抖动转移特性，提出了抑制这一干扰抖动的方法和干扰抖动的测试方法。     

光传送网(OTN)的抖动性能要求

处于光层网络的OTN,与电层的PDH,SDH网络一样,为保证信号传送质量,对抖动性能有相应的要求,文章主要介绍OTN的网络节点接口和设备接口的抖动性能要求,包括最大允许抖动,抖动转移特性和最小抖动容限,最后简单介绍OTN的抖动累积模型及其算法。     

VoIP系统中消除时延抖动的研究与实现

时延抖动是影响VoIP服务质量(QoS)的一个重要指标。简要介绍了时延抖动的概念,分析了消除网络时延抖动的方法,并提出了一种新的自适应抖动缓冲控制算法。该算法通过动态调整抖动缓冲的大小来消除时延抖动。实验结果表明该算法对语音通信质量有较大提高。     

Clock jitter generator with picoseconds resolution

The clock is one of the most critical signals in any synchronous system. As CMOS technology has scaled, supply voltages have dropped chip power consumption has increased and the effects of jitter due to clock frequency increase have become critical and jitter budget has become tighter. This article describes design and development of low-cost mixed-signal programmable jitter generator with high resolution. The digital technique is used for coarse-grain and an analogue technique for fine-grain clock phase shifting. Its structure allows injection of various random and deterministic jitter components in a controllable and programmable fashion. Each jitter component can be switched on or off. The jitter generator can be used in jitter tolerance test and jitter transfer function measurement of high-speed synchronous digital circuits. At operating system clock frequency of 220?MHz, a jitter with 4?ps resolution can be injected.     

Modeling of the synchronization process jitter spectrum with inputjitter

The synchronous residual time stamp (SRTS) is one approach approved for the encoding and transporting of the continuous bit rate (CBR) service clock in ATM Adaptation Layer 1 (AAL1) allowing CBR services to be transported in ATM cells over the B ISDN. It has been shown by the authors and others that the SRTS method generates waiting time jitter analogous to that produced by other synchronization processes such as pulse stuffing synchronization. Modeling of the synchronization process as it applies to the SRTS method requires a time domain approach to produce an exact expression of the jitter. In this paper, we apply a new time domain analysis technique previously developed by the authors to derive the expressions for the jitter spectrum of the synchronization process in the presence of input jitter on the service clock. Furthermore, the particular form taken by the jitter spectrum when the input jitter is sinusoidal is also found. Experiments verifying the synchronization process jitter spectrum, both with and without sinusoidal input jitter, are reported. Confirmation is also provided that it is possible to approximate timing jitter by phase jitter as long as certain frequency-amplitude limits are observed     

Phase jitter≡timing jitter?

In digital communication systems, the periodicity of timing signals is often disturbed. While timing jitter has been adopted by the International Telecommunication Union (ITU) as the standardized measurement for such disturbances, phase jitter is often used instead in much of the current relevant literature. The fundamental concepts of timing jitter and phase jitter are examined and definitions are presented. A nonlinear relationship between timing jitter and phase jitter is developed, and a general rendition under which one can be approximated by the other is obtained. This condition is tested against the timing jitter and wander tolerance for digital equipment operating at 2048 kb/s, as specified in ITU-T Recommendation G.823     

Analysis of true jitter arising from pulse-stuffing schemes

In synchronous digital hierarchy and plesiochronous digital hierarchy networks, it is frequently necessary to recover a data clock from a gapped clock derived from stuff information present at the desynchronizer. In this paper, a comprehensive analysis of the timing jitter resulting from phase-locked loop-type desynchronizers is presented. This analysis is different from the conventional analysis where the jitter is represented using a phase-error sequence. It is shown that such a simplified approach cannot accurately describe the jitter at the output of the desynchronizer. From the detailed analysis, it is also shown how the use of threshold modulation at the synchronizer reduces the low-frequency jitter at the desynchronizer. It has been demonstrated in the paper that when threshold modulation is used at the synchronizer, the dominating low-frequency jitter terms cannot be explained by the conventional jitter analysis methods. Therefore, in future networks, where tighter jitter performances are to be imposed on the synchronizers, jitter characterization using the proposed true jitter analysis technique would be very useful.     

时钟抖动度量指标和测试方法概述

数字通信系统中,时钟抖动是影响通信质量的因素之一,在系统设计、设备研制、工程验收等各环节抖动指标是必须考虑的。本文介绍了通信中常用的抖动概念、分类、度量指标和测试方法,并对时钟设备抖动指标测试进行了描述。最后对抖动测试的发展方向进行了展望。     

The importance of calibration standards in jitter measurements

When ITU-T standardized SONET/SDH in 1988, the highest speed was 156 Mb/s. The rapid growth of the Internet, as well as other factors, has increased the necessary speed of today's networks to 10 Gb/s or 40 Gb/s (10G, 40G). In 2000, ITU-T Recommendation G.783 specified the maximum jitter for error-free communications on 10G and 40G networks, but there was not a standard process to verify the accuracy of jitter measurements and no reference source with a known jitter amount. Accurate jitter measurements at high speed are difficult because of the small times involved, but they are essential for implementing error-free networks. The paper describes a method which shows that accurate jitter measurements at 10G and above must correctly account for both pattern-dependent and random jitter. Pattern-dependent jitter is caused to a much greater extent by the transmitter than by the receiver. Incorrect assumptions about the source of pattern-dependent jitter can result in large inconsistencies in jitter measurements at high speed. The method outlined solves those problems.     

带通采样时钟沿抖动对解调性能的影响分析

在中频直接采样系统中,采样时钟的抖动问题是带通采样的一个关键问题。研究了带通采样时钟抖动对系统的影响,介绍了带通采样时钟沿抖动的产生极其直观影响,分析带通采样时钟沿抖动对解调性能的影响,并仿真验证了理论分析的正确性。结合典型的调制编码方式对带通采样时钟沿抖动范围提出了要求,为带通采样的设计及实现提供了依据。