共查询到19条相似文献,搜索用时 750 毫秒
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EV8AQ160型ADC在2.5 Gsps双通道高速信号采集系统中的应用 总被引:1,自引:0,他引:1
针对某高速实时频谱仪中的高速模数转换器(ADC)的应用,基于信号采集系统硬件平台,介绍了一种最大采样率可达5 Gbps的高速8位A/D转换器EV8AQ160。该器件内部由4路并行的ADC构成,各路ADC可并行工作也可交错工作。详细描述了EV8AQ160在交错模式下的工作原理,介绍了其在某双通道高速信号采集系统中的应用,给出了EV8AQ160与Xilinx公司Virtex-6 FPGA的接口设计方案以及系统结构框图,并用ISE的在线逻辑分析仪(ChipScope Pro)测试了ADC性能。把ADC输出的数据存储在DDR3中,然后进行FFT变换,进而分析ADC的信噪比及有效位数,实测表明整体指标达到设计要求。 相似文献
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为了解决传统转换器传输接口传输速率低、抗干扰差、布局布线面积大等问题,设计了一种基于JESD204B的射频信号高速采集系统。系统对接收到的射频信号进行下变频处理,通过高速ADC对解调基带信号直接采样,采样后的数字基带信号通过自主设计的JESD204B接口逻辑传输至FPGA并缓存。测试结果表明,系统可实现1.0 Gsample/s采样率的直接采样,数据传输速率可达10 Gbit/s,且数据链路稳定可靠。 相似文献
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简述了Xilinx公司Virtex系列FPGA中数字时钟管理器(DCM)的工作原理,以及在高速ADC输出数据同步处理电路中的应用。给出采用DCM进行高速数据同步处理方法,数据同步时钟相位调节的方法和试验结论。 相似文献
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CPCI总线为不同应用的高速数字系统提供了一个通用、开放的平台,它充分发挥了PCI总线的高性能、低成本、通用操作系统等特点,而LVDS接口技术无疑也将成为解决高速数字系统数据传输的首选方案。提出了一种基于FPGA实现CPCI总线接口与LVDS接口的新方法,CPCI总线与自定义LVDS接口相结合,在不降低系统通用性的前提下,提高了系统实时并行处理能力。由于所有接口均由FPGA来实现,因此提高了系统的可重构性。 相似文献
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数字校准是高速高精度流水线ADC设计中的关键技术之一。文章提出了一种可通过校准控制生成测试信号,自动计算权重来对流水线ADC中电容失配进行误差补偿的技术。该技术能有效地减小增益有限、电荷注入等非理想因素的影响,使校准输出后的数据拥有更高的准确度,提高了系统的线性度。 相似文献
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Yi Tang Kuang-Wei Cheng Gupta S. Paramesh J. Allstot D.J. 《IEEE transactions on circuits and systems. I, Regular papers》2008,55(3):817-827
A complex analog-to-digital converter (ADC) intended for digital intermediate frequency (IF) receiver applications digitizes analog signals at IFs with excellent power/bandwidth efficiency. However, it is vulnerable to mismatches between its in-phase and quadrature (I/Q) paths that can dramatically degrade its performance. The proposed solution mitigates I/Q mismatch effects using a complex sigma-delta (SigmaDelta) modulator cascaded with 9-bit pipeline converters in each of the I and Q paths. The quantization noise of the first stage complex modulator is eliminated using an adaptive scheme to calibrate finite-impulse response digital filters in the digital noise-cancellation logic block. Although low-pass SigmaDelta cascade ADCs are widely used because of their inherent stability and high-order noise shaping, the complex bandpass cascade architecture introduced herein maintains these advantages and doubles the noise shaping bandwidth. Digital calibration also reduces the effects of analog circuit limitations such as finite operational amplifier gain, which enables high performance and low power consumption with high-speed deep-submicrometer CMOS technology. Behavioral simulations of the complex SigmaDelta/pipeline cascade bandpass ADC using the adaptive digital calibration algorithm predict a signal-to-noise ratio (SNR) of 78 dB over a 20-MHz signal bandwidth at a sampling rate of 160 MHz in the presence of a 1% I/Q mismatch. 相似文献
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流水线模数转换器(Pipeline ADC)是一种应用广泛的模数转换器结构,可以同时实现高速和高精度性能。然而电路的非理想性严重制约着流水线ADC的性能。提出了一种自适应数字技术,通过使用低速但准确的ADC作为基准,与待校正的流水线ADC并联,并将两者的数字输出的差值送入数字自适应滤波器中进行处理,使流水线ADC的输出不断逼近低速但准确的ADC输出,从而达到数字校正的目的。仿真结果表明,这种方法可以有效去除包括电容失配、有限运放增益、运放失调在内的误差。 相似文献
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针对下一代光传输系统对模数转换器(ADC)高采样率、大带宽的要求,提出一种针对该类ADC动态性能的测试方法.通过分析光传输系统中ADC芯片的特点,解决了采样时钟无法直接测量,输出数据难以捕获,分辨率不易统计,插损非线性导致带宽测量偏差等问题,并将该方法应用于光传输、雷达、卫星等高数据率场景所用超高速ADC芯片的评测中.测试结果表明,该方法解决了最高采样率70GSPS带宽16GHz的超高速ADC测试的关键问题,基本满足下一代400Gbps光传输系统对ADC动态性能测试的要求. 相似文献
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A/D转换器(ADC)的校准技术是提高高性能ADC转换精度的必要手段,它分为模拟校准技术和数字校准技术。数字校准技术较之模拟校准技术更为有效和更具灵活性。数字校准技术是在数字域进行错误代码计算,减轻了对模拟电路的精度要求。在主流制造工艺小尺寸化的趋势之下,许多创新的校准技术得到发展,并广泛应用于包括射频直接采样ADC在内的高速高精度ADC中。本文在分析最新的高速高精度ADC中采用的主要校准技术的基础上,重点研究了几种高采样率高精度ADC所采用的校准技术,侧重分析了数字校准技术。 相似文献
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Superconductor analog-to-digital converters 总被引:1,自引:0,他引:1
Mukhanov O.A. Gupta D. Kadin A.M. Semenov V.K. 《Proceedings of the IEEE. Institute of Electrical and Electronics Engineers》2004,92(10):1564-1584
Ultrafast switching speed, low power, natural quantization of magnetic flux, quantum accuracy, and low noise of cryogenic superconductor circuits enable fast and accurate data conversion between the analog and digital domains. Based on rapid single-flux quantum (RSFQ) logic, these integrated circuits are capable of achieving performance levels unattainable by any other technology. Two major classes of superconductor analog-to-digital converters (ADCs) are being developed - Nyquist sampling and oversampling converters. Complete systems with digital sampling at rates of /spl sim/20 GHz and above have been demonstrated using low-temperature superconductor device technology. Some ADC components have also been implemented using high-temperature superconductors. Superconductor ADCs have unique applications in true digital-RF communications, broadband instrumentation, and digital sensor readout. Their designs, test results, and future development trends are reviewed. 相似文献
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A 4 Gbps transmitter for a 12-bit 250 MSPS pipelined ADCs is presented. A low power current mode (CM) output driver with reverse scaling technique is proposed. A high speed, low power combined serializer is implemented to convert 12 bit parallel data into a seria1 data stream. The whole transmitter is used in a 12-bit 250 MSPS pipelined ADC for the digital output buffer and fabricated in 180 nm 1. 8 V 1P5M CMOS technology. Test results show that the transmitter provides an eye height greater than 800 mV for data rates of both 2 Gbps and 4 Gbps, the 12-bit 250 MSPS ADC achieves the SNR of 69.92 dBFS and SFDR of 81.17 dB with 20.1 MHz input at full sampling speed. The ADC with the 4 Gbps transmitter consumes the power consumption of 395 mW, where the power consumption of transmitter is 75 mW. The ADC occupies an area of 2.5×3.2 mm2, where the active area of the transmitter block is 0.5×1.2 mm2. 相似文献
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Emerging telecom systems such as ADSL and VDSL demand state-of-the-art high speed and high resolution analog-to-digital converters (ADCs) and digital-to-analog converters (DBCs). Moreover, cost and power consumption issues require the use of specific A/D and D/A architectures to achieve the wanted resolution at the required speed at minimum power. In the first part of this article we present an overview of the various ADC and DAC architectures used in Alcatel Telecom systems over the past 15 years, with an emphasis placed on the evolution of ADCs and DACs for today's asymmetrical-digital-subscriber-loop (ADSL) applications. We then discuss design considerations for high-speed and high resolution ADCs for future very-high-data-rate digital subscriber-line (VDSL) technology 相似文献
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Kamal El-Sankary 《Microelectronics Journal》2006,37(11):1231-1240
Next-generation transceivers operating with different standards require the existence of a wide bandwidth and highly linear analog-to-digital converters (ADCs) to enable software-defined radios (SDR). Several methods dealing with the design and implementation of high-resolution and high-speed ADCs to provide the stringent requirements of the wide-bandwidth transceivers are presented. A special focus is made on pipelined ADC for its superior performance in terms of speed and resolution. A digital background calibration technique to compensate for the capacitors mismatch, and the finite opamps gain is presented. Low overhead digitally oriented technique to increase the speed of the ADC beyond the technological limits by overcoming the problems of the conventional time-interleaving is also presented. Simulation results prove the effectiveness of these techniques. 相似文献