Effect of nanotopography in direct wafer bonding: modeling and measurements

Nanotopography, which refers to surface height variations of tens to hundreds of nanometers that extend across millimeter-scale wavelengths, is a wafer geometry feature that may cause failure in direct wafer bonding processes. In this work, the nanotopography that is acceptable in direct bonding is determined using mechanics-based models that compare the elastic strain energy accumulated in the wafer during bonding to the work of adhesion. The modeling results are presented in the form of design maps that show acceptable magnitudes of height variations as a function of spatial wavelength. The influence of nanotopography in the bonding of prime grade silicon wafers is then assessed through a combination of measurements and analysis. Nanotopography measurements on three 150-mm silicon wafers, which were manufactured using different polishing processes, are reported and analyzed. Several different strategies are used to compare the wafers in terms of bondability and to assess the impact of the measured nanotopography in direct bonding. The measurement and analysis techniques reported here provide a general route for assessing the impact of nanotopography in direct bonding and can be employed when evaluating different processes to manufacture wafers for bonded devices or substrates.     

The Effect of Thermal Shocks on the Stresses in a Sapphire Wafer

Sapphire wafers can experience temperature variations during processing in a furnace, which in turn can cause large deformation and stresses in the wafers. This paper aims to reveal the mechanism of stress development and evolution in sapphire wafers during thermal shocks, as well as the dependence of the stresses on some process parameters. Finite-element stress analysis was conducted on a single sapphire wafer subjected to thermal shocks. The results show that the thermal gradient in the radial direction induces high stresses even in mechanically unrestrained wafers. The largest stress components occur at the wafer edge as the largest normal stresses are circumferential; whereas the maximum tensile stress is realized upon cooling, the highest value of the maximum shear stress and the minimum compressive stress eventuate in the heating-up phase. The normal stresses have a parabolic distribution in the radial direction. It was found that holding the furnace temperature leads to a more uniform temperature distribution across the wafer but brings about higher tensile stresses in the cooling phase     

A sensitivity analysis of SPICE parameters using an eleven-stage ring oscillator

SPICE is a circuit simulator which predicts node voltages and currents as a function of time from device model parameters. Model parameters are determined by the manufacturing process. Process-induced variations in these parameters occur within a chip or from chip to chip and cause corresponding variations in circuit performance. Values for the model parameters used in simulators are usually obtained from measurements on test structures which are found along the periphery of the circuit or in test chips located at several sites on the product wafer. Because of the spatial separation between test structures and the circuits of interest, differences between measured and simulated performance can occur. This paper presents examples of how well model parameters extracted from a test chip can predict the ac response of a dynamic circuit element (ring oscillator) on the same wafer. Simulation results show which model parameters are critical to performance. A comparison between measurement and simulation results is given and the importance of intra-chip and intra-wafer parameter variations is discussed. For the samples tested, the polysilicon gate linewidth variation was determined to be the primary cause of the ring oscillator frequency variation.     

Using spatial information to analyze correlations between teststructure data [semiconductor IC manufacture]

A modeling strategy is presented that captures the dependence of performance on the spatial position of the chips on the water. The information from this model can be used to determine whether the variance and correlation of parameters are due to either random variation or deterministic function of wafer position. The modeling strategy covers deterministic variations of the mean as a function of wafer position. The authors provide a method to determine the amount of correlation which is due to the common spatial dependence (referred to as spatial correlation). When coupled with knowledge about the manufacturing process, the diagnosis system can determine the physical reasons for the yield loss. The problem is formalized and a solution is developed. Extensions to this model are discussed     

Lateral uniformity in HgCdTe layers grown by molecular beam epitaxy

The fabrication of high-quality focal plane arrays from HgCdTe layers grown by molecular beam epitaxy (MBE) requires a high degree of lateral uniformity in material properties such as the alloy composition, doping concentration, and defect density. While it is well known that MBE source flux nonuniformity can lead to radial compositional variation for rotating substrates, we have also found that composition can be affected significantly by lateral variations in substrate temperature during growth. In diagnostic experiments, we systematically varied the substrate temperature during MBE and quantified the dependence of HgCdTe alloy composition on substrate temperature. Based on these results, we developed a methodology to quickly and nondestructively characterize MBE-grown layers using postgrowth spatial mapping of the cutoff wavelength from the Fourier transform infrared (FTIR) transmission at 300 K, and we were able to obtain a quantitative relationship between the measured spatial variations in cutoff and the substrate temperature lateral distribution during growth. We refined this methodology by more directly inferring the substrate temperature distribution from secondary ion mass spectroscopy (SIMS) measurements of the As concentration across a wafer, using the fact that the As incorporation rate in MBE-grown p-type layers is highly sensitive to substrate temperature. Combining this multiple-point SIMS analysis with FTIR spatial mapping, we demonstrate how the relative contributions from flux nonuniformity and temperature variations on the lateral composition uniformity can be separated. This capability to accurately map the lateral variations in the substrate temperature has been valuable in optimizing the mounting and bonding of large substrates for MBE growth, and can also be valuable for other aspects of MBE process development.     

Wafer‐Level Self‐Organized Copolymer Templates for Nanolithography with Sub‐50 nm Feature and Spatial Resolutions

Robust lithographic templates, with sub‐50 nm feature and spatial resolutions, that exhibit high patterning integrity across a full‐wafer are demonstrated using self‐organized copolymer reverse micelles on 100 mm Si wafers. A variation of less than 5% in the feature size and periodicity of polymeric templates across the entire wafer is achieved simply by controlling the spin‐coating process. Lithographic pattern transfer using these templates yields Si nanopillar arrays spanning the entire wafer surface and exhibiting high uniformity inherited from the original templates. The variation in geometric characteristics of the pillar arrays across the full‐wafer surface is validated to be less than 5% using reflectance spectroscopy. The physical basis of the change in reflectance with respect to sub‐10 nm variations in geometric parameters of pillar arrays is shown by theoretical modelling and simulations. Successful fabrication of highly durable TiO₂ masks for nanolithography with sub‐50 nm feature width and spatial resolutions is achieved through highly controlled vapour phase processing of reverse micelle templates. This allows lithographic pattern‐transfer of organic templates with a feature thickness and separation of less than 10 nm, which is otherwise not possible through other approaches reported in literature.     

Offset in CMOS magnetotransistors. I. Analysis of causes

Fabrication imperfections cause offset in CMOS magnetotransistors (MTs). In this paper, MT offset is experimentally characterized and its causes are analyzed for two different commercial CMOS processes. For the MT structures chosen as references, the average absolute value of the offset in terms of a relative imbalance of two collector currents is up to 2.7%. The mean offset temperature drift between -40°C and +140°C is 0.25%. The offset exhibits a high degree of variation on a very small spatial scale. Additionally, variations on a large scale over the wafer are observed and, in some cases, systematic influences. The actual offset contributions of the various identified possible sources are investigated. Misalignment of the metal contact mask occurring during photolithography dominates large scale offset variations and can also have a systematic component. Another systematic influence arises from nonorthogonal dopant implantation. Doping inhomogeneities are a dominating contribution to local variations as indirect evidence suggests. Further, mismatch in emitter-collector spacing is critical. Suppressed sidewall injection magnetotransistors (SSIMTs) showing an enhanced sensitivity exhibit a quadrupling of the offset, which comes from a misalignment of the emitter guard ring. The obtained results are the basis for dedicated offset reduction in MTs as well as the development of MT-like test structures for processing tolerances     

An In Situ Approach to Real-Time Spatial Control of Steady-State Wafer Temperature During Thermal Processing in Microlithography

We proposed an in situ method to control the steady-state wafer temperature uniformity during thermal processing in microlithography. Thermal processing of wafer in the microlithography sequence is conducted by the placement of the wafer on the bake-plate for a given period of time. A physical model of the thermal system is first developed by considering energy balances on the system. Next, by monitoring the bake-plate temperature and fitting the data into the model, the temperature of the wafer can be estimated and controlled in real-time. This is useful as production wafers usually do not have temperature sensors embedded on it, these bake-plates are usually calibrated based on test wafers with embedded sensors. However, as processes are subjected to process drifts, disturbances, and wafer warpages, real-time correction of the bake-plate temperatures to achieve uniform wafer temperature at steady state is not possible in current baking systems. Any correction is done based on run-to-run control techniques which depends on the sampling frequency of the wafers. Our approach is real-time and can correct for any variations in the desired steady-state wafer temperature. Experimental results demonstrate the feasibility of the approach     

A neural-network approach to recognize defect spatial pattern insemiconductor fabrication

Yield enhancement in semiconductor fabrication is important. Even though IC yield loss may be attributed to many problems, the existence of defects on the wafer is one of the main causes. When the defects on the wafer form spatial patterns, it is usually a clue for the identification of equipment problems or process variations. This research intends to develop an intelligent system, which will recognize defect spatial patterns to aid in the diagnosis of failure causes. The neural-network architecture named adaptive resonance theory network 1 (ART1) was adopted for this purpose. Actual data obtained from a semiconductor manufacturing company in Taiwan were used in experiments with the proposed system. Comparison between ART1 and another unsupervised neural network, self-organizing map (SOM), was also conducted. The results show that ART1 architecture can recognize the similar defect spatial patterns more easily and correctly     

退火对GaAs窗口晶体力学性能的影响

在L EC Ga As晶片中,存在相当大的弹性应变,在高温退火后,晶片的晶格参数的相对变化量不到原生晶片的70 % ,残余应力得以部分释放,从而减小残余应力诱生断裂的可能性,提高了Ga As晶体的断裂模数.原生Ga As晶体加工的样品的断裂模数平均值约为135 MPa,而退火Ga As晶体加工的样品的断裂模数平均值更高,约为15 0 MPa,断裂模数最高值达16 3MPa.     

The effect of surface roughness on the radiative properties ofpatterned silicon wafers

The radiative properties of patterned silicon wafers have a major impact on the two critical issues in rapid thermal processing (RTP), namely wafer temperature uniformity and wafer temperature measurement. The surface topography variation of the die area caused by patterning and the roughness of the wafer backside can have a significant effect on the radiative properties, but these effects are not well characterized. We report measurements of room temperature reflectance of a memory die, logic die, and various multilayered wafer backsides. The surface roughness of the die areas and wafer backsides is characterized using atomic force microscopy (AFM). These data are subsequently used to assess the effectiveness of thin film optics in providing approximations for the radiative properties of patterned wafers for RTP applications     

The sensitivity of radiation-induced leakage to STI topology and sidewall doping

The sensitivity of radiation-induced source-drain leakage to the amount of recess in the shallow-trench isolation (STI) of CMOS technologies is reported. The impact of the doping profile along the STI sidewall on the magnitude of the leakage current is quantified. The sensitivity of the radiation-induced leakage current to these parameters provides insight into how process variability is manifested as variations in the radiation response.     

Reducing the influence of STI on SONOS memory through optimizing added boron implantation technology

The influence of shallow trench isolation (STI) on a 90 nm polysilicon-oxide-nitride-oxide-silicon struc-ture non-volatile memory has been studied based on experiments. It has been found that the performance of edge memory cells adjacent to STI deteriorates remarkably. The compressive stress and boron segregation induced by STI are thought to be the main causes of this problem. In order to mitigate the STI impact, an added boron implantation in the STI region is developed as a new solution. Four kinds of boron implantation experiments have been implemented to evaluate the impact of STI on edge cells, respectively. The experimental results show that the performance of edge cells can be greatly improved through optimizing added boron implantation technology.     

Benefits of real-time, in situ particle monitoring in productionmedium current implantation

Real-time free particle measurements in the loadlocks of a production medium current implanter have been conducted. These measurements correlate to both surface scans and electrical test yield. They suggest that episodic particle generating events that impact yield occur frequently and that particle levels are considerably higher when product wafers are run than when monitor wafers are run. The data correlate to monitor wafer surface counts, allowing the real-time monitor to be used in equipment requalification. The data also provide a real-time plot of machine utilization and performance and can be useful in identifying variations in both the implant process and feeder processes. It is concluded that a strategy of in situ, real-time sampling combined with test wafer monitoring can lead to improved particle control     

Defect clustering viewed through generalized Poisson distribution

It is shown that generalized double Poisson distributions provide a good basis for yield models when moderate spatial heterogeneity exists between chips of larger sizes, or when defects are almost randomly distributed. The model includes the average number and size of clusters as its parameters. On being tested with simulated as well as actual wafer particle maps, the model gave a significance level >0.95 in most of the cases. This model is simple and facilitates direct implementation of multilevel or hierarchical redundancy in regular VLSI/WSI designs. The strength of the proposed model lies in its simplicity and its ability to provide a physical explanation of the clustering process through its parameters. The model reflects the effects of the competition which can occur among defects in a cluster during wafer processing. Comparisons of yield predictions by various models for wafer maps with different spatial properties are reported     

A comprehensive geometrical and biasing analysis for latchup in 0.18-μm CoSi2 STI CMOS structure

This paper evaluates the effects of dimension variations on the latchup immunity of 0.18-μm CoSi₂ shallow trench isolation (STI) CMOS structures. A comprehensive study on the test devices, by variations of geometrical dimensions as well as the spacings, has been established. Focus has also been given to the dimensions of the STI structure, mainly on the width and depth, as the rest of the parameters are varied. The influence of biasing condition on latchup has also been investigated. The results obtained and the as-developed characterization techniques shall bestow a CMOS device that promises optimized layout dimension.     

Wafer temperature measurement in a rapid thermal processor with modulated lamp power

Pyrometry methods utilizing modulated lamp power (“ripple”) were used to improve wafer temperature measurement and control in rapid thermal processing (RTP) for silicon integrated circuit production. Data from a manufacturing line where ripple pyrometers have been tested show significantly reduced wafer to wafer and lot to lot variations in final test electrical measurements and increased yields of good chips per wafer. The pyrometers, an outgrowth of Accufiber’s ripple technique, are used to compensate for ordinary production variations in the emissivities of the backsides of wafers, which face the pyrometers. Power to the heating lamps is modulated with oscillatory functions of time at either the power line frequency or under software control. Fluctuating and quasi-steady components in detected radiation are analyzed to suppress background reflections from the lamps and to correct for effective wafer emissivity. Sheet resistances of annealed wafers with high dose shallow As implants were used to infer temperature measurement capability over a range in backside emissivity. Emissivities are varied when depositing or growing one or more layers of silicon dioxide, silicon nitride, or polycrystalline silicon on the backsides of the wafers.     

Statistical model for spatial correlation in thin film depositionand reactive growth

This paper presents a statistical method for the estimation of thickness variations present across a wafer lot in low pressure chemical vapor deposition (LPCVD) and reactively grown films. The method uses experimental thickness data to construct a unified Karhunen-Loeve expansion based model that captures both deterministic and random thickness variations. The model uses a set of quadratic interpolation functions fitted to mean spatial data to approximate the deterministic nonuniformity and a few normalized random variables to represent run-to-run fluctuations. This model therefore retains the spatial correlations present between different deposition and growth steps in a process necessary for the estimation of parametric yield and permits the calculation of distribution functions over different lot populations (wafer, die, point, etc.). Models for spatial correlations in LPCVD oxide, nitride, polycrystalline silicon, and thermal oxide growth were constructed from a data set of 35000 thickness measurements recorded from a total of 40, 25-wafer runs. In each case, the model gives good predictions (90-95% confidence) with just one or two random variables     

Influence of optical properties of the SOI structure on the wafer temperature during rapid thermal annealing

Optical characteristics are compared theoretically, and temperature differences of the Si wafer with the B-doped SOI structure and substrate wafer are evaluated during rapid thermal annealing. It is shown that under identical annealing conditions and temperatures above 800 K, the difference in their temperatures can reach ∼30 K. We studied the dependence of the total emissivity and temperature of the wafer with the SOI structure on the concentration of the doping impurity in the Si layer. The method of the quantitative analysis of variations of the wafer temperature under invariable annealing conditions depending on the variations of emissivity of its surfaces is suggested.