Fully integrated passive UHF RFID transponder IC with 16.7-/spl mu/W minimum RF input power

This paper presents a novel fully integrated passive transponder IC with 4.5- or 9.25-m reading distance at 500-mW ERP or 4-W EIRP base-station transmit power, respectively, operating in the 868/915-MHz ISM band with an antenna gain less than -0.5 dB. Apart from the printed antenna, there are no external components. The IC is implemented in a 0.5-/spl mu/m digital two-poly two-metal digital CMOS technology with EEPROM and Schottky diodes. The IC's power supply is taken from the energy of the received RF electromagnetic field with help of a Schottky diode voltage multiplier. The IC includes dc power supply generation, phase shift keying backscatter modulator, pulse width modulation demodulator, EEPROM, and logic circuitry including some finite state machines handling the protocol used for wireless write and read access to the IC's EEPROM and for the anticollision procedure. The IC outperforms other reported radio-frequency identification ICs by a factor of three in terms of required receive power level for a given base-station transmit power and tag antenna gain.     

A 0.18-/spl mu/m CMOS offset-PLL upconversion modulation loop IC for DCS1800 transmitter

A DCS1800 offset-phase-locked-loop upconversion modulation loop integrated circuit (IC) fabricated in a 0.18-/spl mu/m CMOS technology is presented in this paper. This IC operates at 2.8-V supply voltage with a current consumption of 36 mA. The measured root-mean-square and peak phase errors of the Gaussian minimum shift keying (GMSK) transmission signal are 1.6/spl deg/ and 4/spl deg/, respectively. It is shown that such circuits can be implemented in CMOS process with current dissipation and performance comparable to BiCMOS chips. Advantages of upconversion modulation loop and design issues of I/Q modulators are also described.     

Single-mode monolithic quantum-dot VCSEL in 1.3 /spl mu/m with sidemode suppression ratio over 30 dB

We present monolithic quantum-dot vertical-cavity surface-emitting lasers (QD VCSELs) operating in the 1.3-/spl mu/m optical communication wavelength. The QD VCSELs have adapted fully doped structure on GaAs substrate. The output power is /spl sim/330 /spl mu/W with slope efficiency of 0.18 W/A at room temperature. Single-mode operation was obtained with a sidemode suppression ratio of >30 dB. The modulation bandwidth and eye diagram in 2.5 Gb/s was also presented.     

A 1.1-V 270-/spl mu/A mixed-signal hearing aid chip

This paper presents a single-chip mixed-signal IC for a hearing aid system. The IC consumes 270 /spl mu/A of supply current at a 1.1-V battery voltage. The presented circuit and architectural design techniques reduce the total IC power to 297 /spl mu/W, a level where up to 70 days of lifetime is achieved at 10 h/day for a small zinc-air battery. The measured input referred noise for the entire channel is 2.8 /spl mu/Vrms and the average THD in the nominal operating region is 0.02%. The jitter for the on-board ring oscillator is 147 ps rms. The chip area is 12 mm/sup 2/ in a 0.6-/spl mu/m 3.3-V mixed-signal CMOS process.     

Photonic generation of continuous THz wave using uni-traveling-carrier photodiode

A uni-traveling-carrier photodiode (UTC-PD) is monolithically integrated with a wideband log-periodic toothed antenna for generating millimeter and submillimeter waves at frequencies of up to terahertz range. A module with a quasi-optical output port fabricated for practical use operates up to 1.5 THz and generates an output power of 2.3 /spl mu/W at 1.04 THz with good linearity. The output power level and the operation frequency are records for wideband PD modules operating at 1.55 /spl mu/m. An investigation of the operational characteristics of the UTC-PD reveals that the effective use of the electron-velocity overshoot in the junction depletion layer is important for maximizing the output power in the terahertz range.     

Uncooled high-temperature (130/spl deg/C) operation of InGaAs-GaAs multiple quantum-well lasers at 20 Gb/s

Short-haul fiber-optic communication systems require high-speed semiconductor lasers that can operate uncooled over a wide temperature range. In this letter, we describe high-speed short-cavity InGaAs-GaAs multiple-quantum-well lasers operating at 1.1-/spl mu/m wavelength. The Fabry-Perot lasers were fabricated in a triple-mesa geometry suitable for on-wafer probing. With 3/spl times/200 /spl mu/m/sup 2/ ridge-waveguide lasers, which showed the best compromise between high-temperature and high-speed performance, a 3-dB modulation bandwidth of 14.5 GHz at 130/spl deg/C was achieved. Uncooled 20-Gb/s operation of these lasers is presented over a wide-temperature range from 25/spl deg/C to 130/spl deg/C without automatic power control.     

Integrated FSK demodulator with very high sensitivity

This paper presents a fully integrated highly sensitive frequency-shift keying (FSK) demodulator functioning at a modulation factor of 0.5%-0.1% and below. A dual-feedback phase-locked loop approach provides both very high sensitivity and sufficiently large tuning range. Experimental results in TSMC 0.25-/spl mu/m CMOS technology demonstrate that Gaussian FSK signals of a modulation factor down to 0.06% can safely be demodulated.     

40-Gbit/s OEIC on GaAs substrate through metamorphic buffer technology

An optoelectronic integrated circuit operating in the 1.55-/spl mu/m wavelength range was realized on GaAs substrate through metamorphic technology. High indium content layers, metamorphically grown on a GaAs substrate, were used to fabricate the optoelectronic integrated circuits (OEICs) with -3 dB bandwidth of 40 GHz and 210 V/W of calculated responsivity. The analog OEIC photoreceiver consists of a 12-/spl mu/m, top-illuminated p-i-n photodiode, and a traveling wave amplifier (TWA). This receiver shows 6 GHz wider bandwidth than a hybrid photoreceiver, which was built using comparable, but stand-alone metamorphic p-i-n diode and TWA. With the addition of a buffer amplifier, the OEIC shows 7 dB more gain than the hybrid counterpart. To our knowledge, this is the first 40 Gbit/s OEIC achieved on a GaAs substrate operating at 1.55 /spl mu/m.     

A low-power correlation-derivative CMOS VLSI circuit for bearing estimation

We present a CMOS integrated circuit (IC) for bearing estimation in the low-audio range that performs a correlation derivative approach in a 0.35-/spl mu/m technology. The IC calculates the bearing angle of a sound source with a mean variance of one degree in a 360/spl deg/ range using four microphones: one pair is used to produce the indication and the other to define the quadrant. An adaptive algorithm decides which pair to use depending on the direction of the incoming signal, in such a way to obtain the best estimate. The IC contains two blocks with 104 stages each. Every stage has a delay unit, a block to reduce the clock speed, and a 10-bit UP/DN counter. The IC measures 2 mm by 2.4 mm, and dissipates 600 /spl mu/W at 3.3 V and 200 kHz. It is purely digital and uses a one-bit quantization of the input signals.     

A low-power CMOS Bluetooth RF transceiver with a digital offset canceling DLL-based GFSK demodulator

This paper presents a fully integrated 0.18-/spl mu/m CMOS Bluetooth transceiver. The chip consumes 33 mA in receive mode and 25 mA in transmit mode from a 3-V system supply. The receiver uses a low-IF (3-MHz) architecture, and the transmitter uses a direct modulation with ROM-based Gaussian low-pass filter and I/Q direct digital frequency synthesizer for high level of integration and low power consumption. A new frequency shift keying demodulator based on a delay-locked loop with a digital frequency offset canceller is proposed. The demodulator operates without harmonic distortion, handles up to /spl plusmn/160-kHz frequency offset, and consumes only 2 mA from a 1.8-V supply. The receiver dynamic range is from -78 dBm to -16 dBm at 0.1% bit-error rate, and the transmitter delivers a maximum of 0 dBm with 20-dB digital power control capability.     

A 2 V 1.8 GHz fully integrated CMOS dual-loop frequency synthesizer

A 2 V 1.8 GHz fully integrated CMOS dual-loop frequency synthesizer is designed in a standard 0.5 /spl mu/m digital CMOS process for wireless communication. The voltage-controlled oscillator (VCO) required for the low-frequency loop is designed using a ring-type VCO and achieves a tuning range of 89% from 356 to 931 MHz and a phase noise of -109.2 dBc/Hz at 600 kHz offset from 856 MHz. With an active chip area of 2000/spl times/1000 /spl mu/m/sup 2/ and at a 2 V supply voltage, the whole synthesizer achieves a tuning range from 1.8492 to 1.8698 GHz in 200 kHz steps with a measured phase noise of -112 dBc/Hz at 600 kHz offset from 1.86 GHz. The measured settling time is 128 /spl mu/s and the total power consumption is 95 mW.     

A low-power low-noise CMOS amplifier for neural recording applications

There is a need among scientists and clinicians for low-noise low-power biosignal amplifiers capable of amplifying signals in the millihertz-to-kilohertz range while rejecting large dc offsets generated at the electrode-tissue interface. The advent of fully implantable multielectrode arrays has created the need for fully integrated micropower amplifiers. We designed and tested a novel bioamplifier that uses a MOS-bipolar pseudoresistor element to amplify low-frequency signals down to the millihertz range while rejecting large dc offsets. We derive the theoretical noise-power tradeoff limit - the noise efficiency factor - for this amplifier and demonstrate that our VLSI implementation approaches this limit by selectively operating MOS transistors in either weak or strong inversion. The resulting amplifier, built in a standard 1.5-/spl mu/m CMOS process, passes signals from 0.025Hz to 7.2 kHz with an input-referred noise of 2.2 /spl mu/Vrms and a power dissipation of 80 /spl mu/W while consuming 0.16 mm/sup 2/ of chip area. Our design technique was also used to develop an electroencephalogram amplifier having a bandwidth of 30 Hz and a power dissipation of 0.9 /spl mu/W while maintaining a similar noise-power tradeoff.     

Bipolar high-gain limiting amplifier IC for optical-fiber receivers operating up to 4 Gbit/s

A monolithic integrated high-gain limiting amplifier for future optical-fiber receivers is described. It is characterized by the following features: high insertion-voltage gain (maximum 54 dB); high input dynamic range (about 52 dB) at constant output-voltage swing (400 mV/SUB p-p/); high operating speed (up to at least 4 Gb/s); low power dissipation (350 mW at 50-/spl Omega/ load); standard supply voltage (5 V); 50-/spl Omega/ output buffer; one-chip solution; and small fabrication costs by use of a 2-/spl mu/m standard bipolar technology without needing polysilicon self-aligning processes. The good values of operating speed and power consumption, which the authors believe has until now not nearly been achieved by other comparable bipolar amplifier ICs, are a result of careful circuit design and optimization. The amplifier was extended to a high-sensitivity (amplitude and time) decision circuit operating at up to 4.0 Gb/s by adding a high-speed master-slave D-flip-flop IC fabricated with the same technology.     

MQW DBR lasers with monolithically integrated external-cavity electroabsorption modulators fabricated without modification of the active region

In this letter, we report the design and operation of multiple-quantum-well distributed Bragg reflectors (MQW DBR) lasers with monolithically integrated external-cavity electroabsorption (EA) modulators without modification of the active region fabricated using only a single growth step. Devices were fabricated with operating wavelengths of 1.06, 1.07, and 1.08 /spl mu/m, which are red-shifted from the material gain peak wavelength (/spl lambda/=1.05 /spl mu/m) by 100, 200, and 300 /spl Aring/, respectively. The /spl lambda/=1.06-/spl mu/m device has a continuous-wave (CW) threshold current of 16 mA and a slope efficiency of 0.09 W/A from the modulator facet, while the /spl lambda/=1.08 /spl mu/m device has a CW threshold current of 33 mA and a slope efficiency of 0.40 W/A from the modulator facet. The /spl lambda/=1.06-, 1.07-, and 1.08-/spl mu/m device exhibits an extinction ratio of /spl ges/20 dB at a modulator bias of 1.0, 1.4, and 2 V, respectively.     

A 4-/spl mu/a quiescent-current dual-mode digitally controlled buck converter IC for cellular phone applications

This paper describes a dual-mode digitally controlled buck converter IC for cellular phone applications. An architecture employing internal power management is introduced to ensure voltage compatibility between a single-cell lithium-ion battery voltage and a low-voltage integrated circuit technology. Special purpose analog and digital interface elements are developed. These include a ring-oscillator-based A/D converter (ring-ADC), which is nearly entirely synthesizable, is robust against switching noise, and has flexible resolution control, and a very low power ring-oscillator-multiplexer-based digital pulse-width modulation (PWM) generation module (ring-MUX DPWM). The chip, which includes an output power stage rated for 400 mA, occupies an active area 2 mm/sup 2/ in 0.25-/spl mu/m CMOS. Very high efficiencies are achieved over a load range of 0.1-400 mA. Measured quiescent current in PFM mode is 4 /spl mu/A.     

A 195-gb/s 1.2-W inductive inter-chip wireless superconnect with transmit power control scheme for 3-D-stacked system in a package

A wireless interface by inductive coupling achieves aggregated data rate of 195 Gb/s with power dissipation of 1.2W among 4-stacked chips in a package where 195 transceivers with the data rate of 1 Gb/s/channel are arranged in 50-/spl mu/m pitch in 0.25-/spl mu/m CMOS technology. By thinning chip thickness to 10/spl mu/m, the interface communicates at distance of 15 /spl mu/m at minimum and 43 /spl mu/m at maximum. A low-power single-end transmitter achieves 55% power reduction for multiple connections. The transmit power is dynamically controlled in accordance with communication distance to reduce not only power dissipation but also crosstalk.     

A CMOS ultra-wideband impulse radio transceiver for 1-mb/s data communications and /spl plusmn/2.5-cm range finding

A CMOS ultra-wideband impulse radio (UWB-IR) transceiver was developed in 0.18-/spl mu/m CMOS technology. It can be used for 1-Mb/s data communications as well as for precise range finding within an error of /spl plusmn/2.5 cm. The power consumptions of the transmitter and receiver for data communication are 0.7 and 4.0 mW, respectively. When an LNA operates intermittently through bias switching, the power consumption of the transceiver is only 1 mW. The range for data communication is 1 m with BER of 10/sup -3/. For ranging applications, the transmitter can reduce the power to 0.7 /spl mu/W for 1k pulses per second, and the receiver consumes little power. The transceiver design, all-digital transmitter, and intermittent circuit operation at the receiver reduce the power consumption dramatically, which makes the transceiver well suited for applications like sensor networks. The electronic field intensity is lower than 35 /spl mu/V/m, and thus the UWB system can be operated even under the current Japan radio regulations.     

On-chip high speed localized cooling using superlattice microrefrigerators

In this paper, we addressed heating problems in integrated circuits (ICs) and proposed a thin-film thermionic cooling solution using Si/SiGe superlattice microrefrigerators. We compared our technology with the current most common solution, thermoelectric coolers, by strengthening the advantages of its compatible fabrication process as ICs for easy integration, small footprint in the order of /spl sim/ 100/spl times/100 /spl mu/m/sup 2/, high cooling power density, 600W/cm/sup 2/ and fast transient response less than 40 /spl mu/s. The thermoreflectance imaging also demonstrated its localized cooling. All these features combined together to make these microrefrigerators a very promising application for on-chip temperature control, removing hot spots inside IC.     

Optimized second-harmonic generation in quantum cascade lasers

Optimized second-harmonic generation (SHG) in quantum cascade (QC) lasers with specially designed active regions is reported. Nonlinear optical cascades of resonantly coupled intersubband transitions with giant second-order nonlinearities were integrated with each QC-laser active region. QC lasers with three-coupled quantum-well (QW) active regions showed up to 2 /spl mu/W of SHG light at 3.75 /spl mu/m wavelength at a fundamental peak power and wavelength of 1 W and 7.5 /spl mu/m, respectively. These lasers resulted in an external linear-to-nonlinear conversion efficiency of up to 1 /spl mu/W/W/sup 2/. An improved 2-QW active region design at fundamental and SHG wavelengths of 9.1 and 4.55 /spl mu/m, respectively, resulted in a 100-fold improved external linear-to-nonlinear power conversion efficiency, i.e. up to 100 /spl mu/W/W/sup 2/. Full theoretical treatment of nonlinear light generation in QC lasers is given, and excellent agreement with the experimental results is obtained. For the best structure, a second-order nonlinear susceptibility of 4.7/spl times/10/sup -5/ esu (2/spl times/10/sup 4/pm/V) is calculated, about two orders of magnitude above conventional nonlinear optical materials and bulk III-V semiconductors.     

Design and analysis of a low power passive UHF RFID transponder IC

This paper presents a low power passive UHF RFID transponder IC, which is compatible with ISO/IEC 18000-6B Standard, operating at the 915 MHz ISM band with the total supply current consumption less than 10 μA. The fully integrated passive transponder, whose reading distance more than 3 m at 4 W (36 dBm) EIRP with an antenna gain less than 1.5 dBi, is powered by the received RF energy. There are no external components, except for the antenna. The transponder IC includes matching network, rectifier, regulator, power on reset circuit, local oscillator, bandgap reference, AM demodulator, backscatter, control logic and memory. The IC is fabricated using Chartered 0.35 μm two-poly four-metal CMOS process with Schottky diodes and EEPROM supported. The die size is 1.5 mm × 1.0 mm.