Low-voltage, high-speed CMOS analog latched voltage comparator using the “flipped voltage follower” as input stage

The design and characterization of a low-voltage, high-speed CMOS analog latched voltage comparator based on the flipped voltage follower (FVF) cell and input signal regeneration is presented. The proposed circuit consists of a differential input stage with a common-mode signal detector, followed by a regenerative latch and a Set-Reset (S-R) latch. It is suitable for successive-approximation type’s analog-to-digital converters (ADC), but can also be adapted for use in flash-type ADCs. The circuit was fabricated using 0.18 μm CMOS technology, and its measured performance shows 12-bit resolution at 20 MHz comparison rate and 1 V single supply voltage, with a total power consumption of 63.5 μW.     

Enhanced source-degenerated CMOS differential transconductor

A simple technique to improve the output resistance and the linearity of a source-degenerated differential CMOS transconductor is presented, useful even under low supply voltage. It combines the utilization of a super-transistor as a unity-gain buffer and the use of the weak inversion region to optimize a regulated cascode source. Using a standard 0.13 μm CMOS technology with 1.5 V supply voltage, simulation results show the transconductor attains more than 1 GΩ as differential output resistance and a third-order harmonic distortion factor less than −110 dB at 1 kHz for a 0.35 V_pp differential input signal. Other performances are 126 μW power consumption and 65 MHz bandwidth.     

A novel ultra-high compliance, high output impedance low power very accurate high performance current mirror

In this paper a novel ultra-high compliance, low power, very accurate and high output impedance current mirror/source is proposed. Deliberately composed elements and a good combination (for a mutual auto control action) of negative and positive feedbacks in the proposed circuit made it unique in gathering ultra-high compliances, high output impedance and high accuracy ever demanded merits. The principle of operation of this unique structure is discussed, its most important formulas are derived and its outstanding performance is verified by HSPICE simulation in TSMC 0.18 μm CMOS, BSIM3 and Level49 technology. Simulation results with 1 V power supply and 8 μA input current show an input and output minimum voltages of 0.058 and 0.055 V, respectively, which interestingly provide the highest yet reported compliances for current mirrors implemented by regular CMOS technology. Besides an input resistance of 13.3 Ω, an extremely high output resistance of 34.3 GΩ and −3 dB cutoff frequency of 210 MHz are achieved for the proposed circuit while it consumes only 42.5 μW and its current transfer error (at bias point) is the excellent value of 0.02%.     

A high-speed current conveyor based current comparator

In this paper, a new high-speed current mode comparator based on inherent current conveyor and positive feedback properties is presented. This novel approach has resulted in major reduction of the response time and hence a wide band application of the circuit. Simulation results using HSPICE and 0.18 μm CMOS technology with 1.8 V supply confirms a propagation delay of less than 0.4 ns in the high frequency range of 700 MHz with 158 μw power dissipation. Under the above conditions, the accuracy of the input current is as low as 50 nA.     

Low‐Voltage CMOS Current Feedback Operational Amplifier and Its Application

A novel low‐voltage CMOS current feedback operational amplifier (CFOA) is presented. This realization nearly allows rail‐to‐rail input/output operations. Also, it provides high driving current capabilities. The CFOA operates at supply voltages of ±0.75 V with a total standby current of 304 µA. The circuit exhibits a bandwidth better than 120 MHz and a current drive capability of ±1 mA. An application of the CFOA to realize a new all‐pass filter is given. PSpice simulation results using 0.25 µm CMOS technology parameters for the proposed CFOA and its application are given.     

A dual mode UHF EPC Gen 2 RFID tag in 0.18 μm CMOS

A dual mode UHF RFID transponder in 0.18 μm CMOS conforming to the EPC Gen 2 standard is presented. Low voltage design of the analog and digital blocks enables the chip to operate with a 1 V regulated voltage and thus to reduce the power consumption. The novel dual mode architecture enables the chip to work in passive and battery-assisted modes controlled by the reader. A custom Gen 2 based command switches the operation mode of the circuit. By using a special clock calibration method the chip operates from 1.2 to 5 MHz clock frequency. Several low power techniques are employed to reduce the power consumption of the chip which is essential in passive RFID tags. Measurement results show that the chip consumes 12 μW at 1 V supply voltage when it communicates with the reader. The chip is fabricated in 0.18 μm standard CMOS technology and occupies 0.95 mm² die area.     

A fully integrated CMOS voltage regulator for supply-noise-insensitive charge pump PLL design

In this paper, a new design of on-chip CMOS voltage regulator, which provides two stable power supplies to charge pump and voltage controlled oscillator (VCO) in charge pump phase-locked loop (PLL), is presented. A power supply noise rejection (PSNR) whose peaking is less than −40 dB is achieved over the entire frequency spectrum for VCO supply. The voltage regulator provides maximum 14 mA current, and static current is about 780 μA at 3.3 V. Based on the proposed voltage regulator, a PLL clock generator has been developed and measured in the AMS 0.35 μm CMOS process. Operating at 160 MHz, a period jitter of 13.64 ps was measured under a clean power supply, while period jitter became 16.24 ps under a power supply modulated with a 400 mV, 10 kHz square wave.     

Novel low-voltage low-power high-precision CCII± based on bulk-driven folded cascode OTA

This paper presents possible approaches to the design of a novel low-voltage, low-power, and high-precision current conveyor of the second generation (CCII±) based on the bulk-driven folded cascode operational transconductance amplifier (OTA) with extended input common-mode voltage range. This CCII± utilizes bulk-driven differential pairs to obtain a nearly rail-to-rail input stage at a low supply voltage. The proposed conveyor operates at a low supply voltage of ±400 mV with a reduced power consumption of only 64 μW. A current-mode multifunction filter is presented as an application of the CCII±. This filter provides five transfer functions simultaneously, namely low-pass, band-pass, high-pass, notch, and all-pass. The filter has the following properties and advantages: it employs three bulk-driven current conveyors BD-CCII±, three grounded resistors, and two grounded capacitors, which is suitable for integrated circuit implementation. Furthermore, the input signal is connected to the low-impedance X terminal of the BD-CCII± whereas the output signals are taken from the high-impedance output terminals Z+ and Z−. Finally, the pole frequency and quality factor of the designed filter are tunable independent of each other. PSpice simulation results using the 0.18 μm CMOS technology are included to prove the results.     

A novel current reference based on subthreshold MOSFETs with high PSRR

A novel current reference based on subthreshold MOSFETs with high power supply rejection ratio (PSRR) is presented. The proposed circuit takes full advantages of the I-V transconductance characteristics of MOSFET operating in the subthreshold region and the enhancement pre-regulator with the high gain negative feedback loop for the current reference core circuit. The proposed circuit, designed with the SMIC 0.18 μm standard CMOS logic process technology, exhibits a stable current of about 1.701 μA with much low temperature coefficient of 2.5×10⁻⁴ μA/°C in the temperature range of −40 to 150 °C at 1.5 V supply voltage, and also achieves a best PSRR over a broad frequency. The PSRR is about −126 dB at dc frequency and remains −92 dB at the frequency higher 1 MHz. The proposed circuit operates stably at the supply voltage higher 1.2 V and has good process compatibility.     

A 1-V 4-GHz wide tuning range voltage-controlled ring oscillator in 0.18 μm CMOS

A new differential delay cell with complementary current control to extend the control voltage range as well as the operation frequency is proposed for low voltage and wide tuning range voltage-controlled ring oscillator (VCRO). The complementary current control can get rid of the restriction that control voltage is unable to cover the full range of power supply voltage in a conventional VCRO. A three-stage VCRO chip working with 1 V power supply voltage is constructed using 0.18 μm 1P6M CMOS process for verifying the efficacy of the proposed differential delay cell. Measured results of the VCRO chip show that a wide range of operation frequency from 4.09 GHz to 479 MHz, a tuning range of 88%, is achieved for the full range of control voltage from 0 to 1 V. The power consumptions of the chip are 13 and 4 mW for oscillation outputs of 4.09 GHz and 479 MHz, respectively. The measured phase noise is −93.3 dBc/Hz at 1 MHz offset from 4.09 GHz center frequency. The core area of the chip is 106 μm×76.2 μm.     

High-speed CMOS unity-gain current amplifier

A high-performance CMOS unity-gain current amplifier is proposed. The solution adopts two feedback loops to reduce the input resistance and a nested-Miller technique to provide frequency compensation. A design example using a 0.8 μm process and a 2 V supply is given and SPICE simulations show a bandwidth of 75 MHz, no slew-rate limitations and a settling time better than 50 ns, irrespective of the current amplitude. Input and output resistances are better than 0.1 Ω and 15 MΩ, respectively. The input-referred white noise spectral density is .     

Ultra low voltage, high performance operational transconductance amplifier and its application in a tunable Gm-C filter

This paper presents an ultra low voltage, high performance Operational Transconductance Amplifier (OTA) and its application to implement a tunable Gm-C filter. The proposed OTA uses a 0.5 V single supply and consumes 60 μw. Employing special CMFF and CMFB circuits has improved CMRR to 138 dB in DC. Using bulk driven input stage results in higher linearity such that by applying a 500 mv_p-p sine wave input signal at 2 MHz frequency in unity gain closed loop configuration, third harmonic distortion for output voltage is −46 dB and becomes −42.4 dB in open loop state for 820 mv_p-p output voltage at 2 MHz. DC gain of the OTA is 47 dB and its unity gain bandwidth is 17.8 MHz with 20 pF capacitance load due to both deliberately optimized design and special frequency compensation technique. The OTA has been used to realize a wide tunable Gm-C low-pass filter whose cutoff frequency is tunable from 1.4 to 6 MHz. Proposed OTA and filter have been simulated in 0.18 μm TSMC CMOS technology with Hspice. Monte Carlo and temperature dependent simulation results are included to forecast the mismatch and temperature effects after fabrication process.     

A novel low-voltage low-power fully differential voltage and current gained CCII for floating impedance simulations

In this paper we present a new current-mode basic building block that we named voltage and current gained second generation current conveyor (VCG-CCII). The proposed active block allows to control and tune both the CCII current gain and the voltage gain through external control voltages. It has been designed, at transistor level in a standard CMOS technology (AMS 0.35 μm), with a low single supply voltage (2 V), as a fully differential active block. The proposed integrated solution, having both low-voltage (LV) and low-power (LP) characteristics, can be applied with success in suitable IC applications such as floating capacitance multipliers and floating inductance simulators, utilizing a minimum number of active components (one and two, respectively). Simulation results, related to floating impedance simulators, are in good agreement with the theoretical expectations.     

A systematic design approach for low-power 10-bit 100 MS/s pipelined ADC

A systematic design approach for low-power 10-bit, 100 MS/s pipelined analog-to-digital converter (ADC) is presented. At architectural level various per-stage-resolution are analyzed and most suitable architecture is selected for designing 10-bit, 100 MS/s pipeline ADC. At Circuit level a modified wide-bandwidth and high-gain two-stage operational transconductance amplifier (OTA) proposed in this work is used in track-and-hold amplifier (THA) and multiplying digital-to-analog converter (MDAC) sections, to reduce power consumption and thermal noise contribution by the ADC. The signal swing of the analog functional blocks (THA and MDAC sections) is allowed to exceed the supply voltage (1.8 V), which further increases the dynamic range of the circuit. Charge-sharing comparator is proposed in this work, which reduces the dynamic power dissipation and kickback noise of the comparator circuit. The bootstrap technique and bottom plate sampling technique is employed in THA and MDAC sections to reduce the nonlinearity error associated with the input signal resulting in a signal-to-noise-distortion ratio of 58.72/57.57 dB at 2 MHz/Nyquist frequency, respectively. The maximum differential nonlinearity (DNL) is +0.6167/−0.3151 LSB and the maximum integral nonlinearity (INL) is +0.4271/−0.4712 LSB. The dynamic range of the ADC is 58.72 dB for full-scale input signal at 2 MHz input frequency. The ADC consumes 52.6 mW at 100 MS/s sampling rate. The circuit is implemented using UMC-180 nm digital CMOS technology.     

Design tradeoffs for sub-mW CMOS biomedical limiting amplifiers

This paper presents design considerations on CMOS limiting amplifiers to be used as basic building blocks for power-efficient logarithmic amplifiers. The impact of mismatches and device-level properties on sensitivity and gain-bandwidth product is discussed. To this end, a comparison of several types of low-voltage gain cell topologies is presented. Based on statistical (Monte Carlo) results, a high-sensitivity eight-stage limiting amplifier tolerant of process spreads and devices mismatches was designed in 0.35 μm CMOS technology to operate over dc to 20 MHz bandwidth and experimentally evaluated. The proposed limiting amplifier draws 280 μA from a 2-V supply and achieves a voltage gain of 72 dB.     

A bulk-driven quasi-floating gate FVF current mirror for low voltage,low power applications

This paper introduces a new low-voltage, low-power FVF current mirror circuit. The bulk-driven (BD) technique is employed to achieve extended input voltage swing and low supply voltage. Besides, the quasi-floating gate (QFG) is used to achieve high frequency performance. The merging of (BD) and (QFG) appear as a good and attractive solution to improve the circuit performance with reduced supply voltage. Benefiting from the interesting properties of (BD-QFG) MOSFET (MOST) technique, the proposed FVF current mirror circuit exhibits superior performance compared to other previously reported works. The workability of the proposed circuit has been verified through ELDO simulator based on a 0.18 μm USMC process. It achieves an enhanced bandwidth (2.7 GHz), low power consumption (79.33 μW), a low input impedance (130 Ω), and high output impedance (9.5 G Ω) from a low supply voltage (0.8 V). Monte Carlo simulation is also carried out, which proves the robust performance of the proposed circuit against mismatches. An application of the proposed current mirror is presented in the form of the current comparator to ensure the workability of the proposed BD-QFG current mirror.     

低电压低功耗CMOS电流反馈运算放大器的设计

设计了一种低压低功耗的电流反馈运算放大器(CFOA),采用了0.18μm CMOS工艺,工作在0.9 V的电源电压下,并给出了Spectre仿真结果,功耗为245μW。输入采用了轨对轨的结构以提高输入电压摆幅,输出采用互补输出结构,使输出工作在甲乙类状态,以降低电路的功耗。     

Highly linear micropower class AB current mirrors using Quasi-Floating Gate transistors

A design approach to achieve low-voltage micropower class AB CMOS cascode current mirrors is presented. Both class AB operation and dynamic cascode biasing are based on the use of Quasi-Floating Gate transistors. They allow high linearity for large signal currents and accurately set quiescent currents without requiring extra power consumption or supply voltage requirements. Measurement results show that dynamic cascode biasing allows a wider input range and a linearity improvement of more than 23 dB with respect to the use of conventional biasing. A THD value better than −35 dB is measured for input amplitudes up to 100 times the bias currents. Two class AB current mirror topologies are proposed, with slightly different ways to achieve class AB operation and dynamic biasing. The proposed current mirrors, fabricated in a 0.5 µm CMOS technology, are able to operate with a supply voltage of 1.2 V and a quiescent power consumption of only 36 µW, using a silicon area <0.025 mm².     

Design of Sub-1 mW CMOS LC VCO based on current reused topology with Q-enhancement and body-biased technique

A CMOS LC voltage controlled oscillator (VCO) based on current reused topology with low phase noise and low power consumption is presented for IEEE 802.11a (Seller et al. A 10 GHz distributed voltage controlled oscillator for WLAN application in a VLSI 65 nm CMOS process, in: IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 3–5 June, 2007, pp. 115–118.) application. The chip1 is designed with the tail current-shaping technique to obtain the phase noise −116.1 dBc/Hz and power consumption 3.71 mW at the operating frequency 5.2 GHz under supply voltage 1.4 V. The second chip of proposed VCO can achieve power consumption Sub 1 mW and is still able to maintain good phase noise. The current reused and body-biased architecture can reduce power consumption, and better phase noise performance is obtained through raising the Q value. The measurement result of the VCO oscillation frequency range is from 5.082 GHz to 5.958 GHz with tuning range of 15.8%. The measured phase noise is −115.88 dBc/Hz at 1 MHz offset at the operation frequency of 5.815 GHz. and the dc core current consumption is 0.71 mA at a supply voltage of 1.4 V. Its figure of merit (FOM) is −191 dBc/Hz. Two circuits were taped out by TSMC 0.18 μm 1P6M process.     

Ultra-low-power temperature compensated voltage reference generator

A CMOS voltage reference generator, based on the difference between the gate-source voltages of two NMOS transistors, has been implemented with AMS 0.35 μm CMOS technology (V_thn=0.45 and at 0 °C). The minimum and maximum supply voltages that ensure the correct operation of the reference voltage generator, are 1.5 and 4.3 V, respectively. The supply current at the maximum supply voltage and at 80 °C is 2.4 μA. A temperature coefficient of 25 ppm/°C and a line sensitivity of 1.6 mV/V are achieved. The power supply rejection ratios without any filtering capacitor at 100 Hz and 10 MHz are larger than −74 and −59 dB, respectively. The occupied chip area is 0.08 mm².