Fast coupled noise estimation for crosstalk avoidance in the MCGmultichip module autorouter

A multilayer, multichip module (MCM) router, called MCG, is introduced for x-y routing. An efficient method has been derived to allow candidate routes for the nets to be considered simultaneously for compatibility rather than incrementally extending routes or routing one net at a time as in many other techniques. This allows incorporation of accurate models for determining the potential for crosstalk problems during the routing process. MCG incorporates a crosstalk avoidance procedure which facilitates correct-by-design routing in systems susceptible to noise problems. In comparisons with other routers on industrial benchmarks, the MCG router has shown substantial improvement in routing density, number of layers, number of vias, and total interconnect length over routers such as V4R and SLICE. Our test results show up to 18% improvement in via count and up to 33% improvement in the required number of routing layers for these examples over V4R. One of the benchmarks presented contains 37 VHSIC gate arrays, over 7000 nets, and over 14000 pins (pads). Routing at finer pitches with crosstalk avoidance shows a further improvement in interconnect density     

Crosstalk avoidance in MCM routing with timing considerations

A new approach to avoiding crosstalk in MCM interconnects during routing is described. Crosstalk avoidance minimises the amount of rework that must be done after routing and detailed simulation have been completed, thus speeding up physical design. Routing results on benchmark designs show significant improvements over a previously used crosstalk avoidance approach in terms of wiring density obtained     

Crosstalk and Wire Length Reduction in the Non-Manhattan Channel Routing

With the recent advances in VLSI fabrication technology, the device sizes have shrunk blow 0.1 μm. Due to the scaling down of device geometry in deep-submicron technologies, the crosstalk between adjacent nets has become a major concern in high performance VLSI circuit design. Increased crosstalk can cause signal delays, logic hazards, and even malfunctioning of circuits, and thus controlling the level of crosstalk in a chip has become an important task for IC designers. It’s well known …     

MCM routing algorithm based on a compatibility graph approach

A new algorithm for general area multichip module routing using a multi-candidate and compatibility graph approach, which maximises routing density while minimising vias and total wire length, is presented. Experimental results using standard industrial benchmarks show improved results relative to a commercial router and other previously proposed routers while offering flexibility for future incorporation of noise and delay constraints     

Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing

As VLSI technologies scale down, interconnect performance is greatly affected by crosstalk noise due to the decreasing wire separation and increased wire aspect ratio, and crosstalk has become a major bottleneck for design closure. The effectiveness of traditional buffering and spacing techniques for noise reduction is constrained by the limited available resources on chip. In this paper, we present a method for incorporating crosstalk reduction criteria into global routing under a broad power supply network paradigm. This method utilizes power/ground wires as shields between signal wires to reduce capacitive coupling, while considering the constraints imposed by limited routing and buffering resources. An iterative procedure is employed to route signal wires, assign supply shields, and insert buffers so that both buffer/routing capacity and signal integrity goals are met. In each iteration, shield assignment and buffer insertion are considered simultaneously via a dynamic programming-like approach. Our noise calculations are based on Devgan's metric, and our work demonstrates, for the first time, that this metric shows good fidelity on average. An effective noise margin inflation technique is also proposed to compensate for the pessimism of Devgan's metric. Experimental results on testcases with up to about 10000 nets point towards an asymptotic runtime that increases linearly with the number of nets. Our algorithm achieves noise reduction improvements of up to 53% and 28%, respectively, compared to methods considering only buffer insertion or only shield insertion after buffer planning.     

动态串扰优化的开关盒布线

针对超深亚微米芯片设计中的开关盒布线问题提出了可变参数的串扰优化布线算法．该算法充分利用了双层布线资源,将动态信号波形和耦合电容结合起来考虑,进一步减小了线网间的总串扰,并力求通孔数最少．实验证明,本算法能够获得更加优化的布线方案．     

Extended global routing with RLC crosstalk constraints

In this paper, we study an extended global routing problem with RLC crosstalk constraints. Considering simultaneous shield insertion and net ordering, we propose a multiphase algorithm to synthesize a global routing solution with track assignment to satisfy the RLC crosstalk constraint at each sink. The key algorithm phase is global routing synthesis with shield reservation and minimization based on prerouting shield estimation. Experiments using large industrial benchmarks show that compared to the best alternative with postrouting shield insertion and net ordering, the proposed algorithm with shield reservation and minimization reduces the congestion by 18.4% with a smaller runtime. To the best of our knowledge, this is the first in-depth study on global routing synthesis with RLC crosstalk constraints.     

多芯片组件的布线

布线是多芯片组件（ＭＣＭ）ＣＡＤ中的一个关键步骤，由于ＭＣＭ的封装密度很高，因此，因此，其布线问题也较传统的ＩＣ或ＰＣＢ布线更为困难，指出了ＭＣＭ布线中存在的问题，介绍了当前用于ＭＣＭ布线的几种方法，着重讨论了ＳＬＩＣＥ布线法和４通孔布线法，对这几种方法进行了比较，４通孔布线法可直接产生详细布线结果，有利于节省成本和提高布线效率。     

A buffer distribution algorithm for high-performance clock netoptimization

We propose a new approach for optimizing clock trees, especially for high-speed circuits. Our approach provides a useful guideline to a designer, by user-specified parameters, and three of these tradeoffs are provided in this paper. (1) First, to provide a “good” tradeoff between skew and wire length, a new clock tree routing scheme is proposed. The technique is based on a combination of hierarchical bottom-up geometric matching and minimum rectilinear Steiner tree. Our experiments complement the theoretical results. (2) For high-speed clock distribution in the transmission line mode (e.g., multichip modules) where interconnection delay dominates the clock delay, buffer congestion might exist in a layout. Using many buffers in a small wiring area results in substantial interline crosstalks as well as wirability, when the elongation of the imbalanced subtrees is necessary. Placing buffers evenly (locally or globally) over the plane at the minimum impact on wire length increase helps avoid buffer congestion and results in less crosstalk between clock wires. Thus, an effective technique for buffer distribution is proposed. Experimental results verify the effectiveness of the proposed algorithms. (3) Finally, a postprocessing step constraining on phase-delay is also proposed. The technique is based on a combination of hierarchical bottom-up geometric matching and bounded radius minimum spanning tree. The proposed algorithm has an important application in MCM clock net synthesis as well as VLSI clock net synthesis     

Dynamic RWA with FWM-induced crosstalk awareness and modulation format conversion in wavelength-routed optical networks

The constraint of signal transmission quality and network resources utilization in transparent optical networks are herein addressed through a representative cost function based upon an impairment-constraint-base routing (ICBR) approach, taking into account link capacity utilization and the nonlinear physical effect, in the primary instance due to Four-Wave Mixing (FWM)-induced crosstalk. The FWM effect is considered one of the most severe physical impairments for the future photonic networks since the accumulation of FWM crosstalk may cause a fatal degradation in the teletraffic network performance. This paper presents an added functionality to the network model design based on all-optical modulation format conversion from conventional on-off keying (OOK) to quadrature phase-shift keying (QPSK) sending more data within the same bandwidth while minimizing the blocking probability. The joint effect of physical impairment (i.e., FWM-induced crosstalk) awareness and two different modulation formats is considered through numerical simulations. The proposed scheme is expected to realize an all-optical transparent interconnection between networks that employ diverse modulation formats. Results show that the proposed FWM-aware Routing and Wavelength Assignment (RWA) algorithm leads to a more realistic system performance while giving a significant improvement on the network performance.     

A Two-Step Heuristic Algorithm for Minimum-Crosstalk Routing Resource Assignment

This brief deals with the crosstalk minimization problem in an integrated routing resource assignment stage containing several operations between global routing and detailed routing. A two-step heuristic algorithm consisting of coarse assignment and detailed assignment is proposed. In coarse assignment, shield lines are planned based on the chromatic number of a light coarse coupling graph, and the assignment of segments that are longer than a predefined threshold is solved with semidefinite programming. In detailed assignment, a strategy based on a dynamic priority queue is introduced to mitigate common problems caused by sequential routing. Experimental results on a set of benchmarks show significant reduction in coupling length between sensitive segments compared to a prevalent bipartite-matching-based algorithm     

考虑串扰效应的性能驱动全局布线器研究

提出了利用符号化矩计算模型进行性能驱动的多级布线方法.通过在模式布线阶段利用符号化矩计算模型,快速得到电路的高阶矩,并根据计算结果,采用合理的代价函数对时延串扰等性能指标进行预估,进而指导布线.实验结果显示,该算法在串扰优化方面得到较大的提高,布线结果兼顾了时延优化和信号波形质量优化.     

Energy-saving algorithm considering idle light-path prediction in SDM-EON

To effectively reduce the energy consumption,blocking rate and crosstalk between adjacent cores in a multi-core fiber for space division multiplexing elastic optical network (SDM-EON),an energy-saving algorithm considering idle light-path prediction was proposed.The extreme learning machine model was used to predict the traffic volume of each light-path in the network.Thus the idle light-path set and the maintenance time threshold of each idle light-path were obtained.Then,the actual maintenance time of the idle light-path was perceived by the prediction algorithm.Finally,in the light-paths where the actual maintenance time do not exceed the minimum maintenance time threshold and the inter-core crosstalk are lower than the crosstalk threshold,the idle light-path with the least loading energy consumption was selected to carry the new traffic.The simulation results show that compared with the traditional energy-saving algorithm,when the SDM-EON crosstalk limitation is satisfied,the proposed algorithm can lead better energy-saving while maintain the blocking rate at levels compatible.     

自组织神经网络在时延驱动的MCM系统划分中的应用

ＭＣＭ是 的一种新技术,划分是ＭＣＭ设计中极其重要的一个环节,本文应用Ｋｏｈｏｎｅｎ自组织神经网络求解以面积和时延为约束的,以芯片之间的边线代价和系统时钟周期为优化目标ＭＣＭ系统 发问题,算法用单元之间的联接度和组合逻辑单元的内部时延表示直接相联单元间的相似性,并应用模糊相似性变换建立间接相联单元间的相似性,算法将各单元映射到二维平面上,对应一个或者多个神经元,学习过程是通过单元之间有协作的移动,     

An Energy-Efficient Routing Algorithm Based on Relative Identification and Direction for Wireless Sensor Networks

In studies of wireless sensor networks (WSNs), routing protocols in network layer is an important topic. To date, many routing algorithms of WSNs have been developed such as relative direction-based sensor routing (RDSR). The WSNs in such algorithm are divided into many sectors for routing. RDSR could simply reduce the number of routes as compared to the convention routing algorithm, but it has routing loop problem. In this paper, a less complex, more efficient routing algorithm named as relative identification and direction-based sensor routing (RIDSR) algorithm is proposed. RIDSR makes sensor nodes establish more reliable and energy-efficient routing path for data transmission. This algorithm not only solves the routing loop problem within the RDSR algorithm but also facilitates the direct selection of a shorter distance for routing by the sensor node. Furthermore, it saves energy and extends the lifetime of the sensor nodes. We also propose a new energy-efficient algorithm named as enhanced relative identification and direction-based sensor routing (ERIDSR) algorithm. ERISDR combines triangle routing algorithm with RIDSR. Triangle routing algorithm exploits a simple triangle rule to determine a sensor node that can save more energy while relaying data between the transmitter and the receiver. This algorithm could effectively economize the use of energy in near-sensor nodes to further extend the lifetime of the sensor nodes. Simulation results show that ERIDSR get better performance than RDSR, and RIDSR algorithms. In addition, ERIDSR algorithm could save the total energy in near-sensor nodes more effectively.     

Reliability and wireability optimizations for chip placement on multichip modules

The chip placement problem of multichip module (MCM) designs is to map the chips properly to the chip sites on the MCM substrate. Chip placement affects not only the thermal characteristics of an MCM but also routing efficiency, which translates directly into manufacturability, performance, and cost. This paper presents a solution methodology for the optimal placement problem considering both thermal and routing design objectives simultaneously. The coupling is achieved through use of a hybrid-force model that is a combination of the traditional interconnection-force model and a novel thermal-force model. The placement procedure can be used as a design tool to place chips and then determine the tradeoffs which can be made in placing for reliability and wireability. Experiments on five examples including three benchmarks show that the present algorithm yields very high-quality results.     

Entire network load‐aware cooperative routing algorithm for video streaming over mobile ad hoc networks

In this paper, we present an entire network load‐aware cooperative routing algorithm based on IEEE 802.11 multi‐rate for video streaming over mobile ad hoc networks. The proposed routing algorithm is designed to minimize the consumed time slots while guaranteeing the required time slots at all the pairs of adjacent nodes over the route and the contention neighbors of these nodes to support the route. Furthermore, the proposed routing algorithm can distribute the network loads well over the entire network. This technology is essential because video streaming applications require stringent quality of service and even larger network resources compared with traditional data services, and these demands may dramatically increase the entire network load and/or cause network congestion. Finally, experimental results are provided to show a performance of the proposed routing algorithm. Copyright © 2011 John Wiley & Sons, Ltd.     

串扰感知的空分弹性光网络频谱转换器稀疏配置和资源分配方法

针对大容量多芯光纤空分复用弹性光网络(SDM-EON)中芯间串扰导致业务传输质量下降和阻塞率上升的问题,该文提出了节点稀疏配置频谱转换器降低芯间串扰的路由纤芯频谱分配方法。该方法根据网络中节点中介中心性稀疏配置频谱转换器。在业务路由阶段,设计综合考虑光路负载和节点频谱转换能力的光路选择的权重方法;为了降低串扰,在纤芯频谱分配阶段,设计纤芯分组和频谱分区分配方法;最后,针对串扰较大的业务,采用频谱转换以降低业务串扰和改善带宽阻塞率。仿真结果表明,所提算法能有效地提高频谱利用率,降低因芯间串扰导致的带宽阻塞率。     

基于CMRA路由协议改进算法

为了延长无线传感网络的生存时间,需要设计满足高效率、低功耗的路由算法。一种CMRA（intercluster head multi-hop routing algorithm）算法被提出来,这种算法通过节点通信能量消耗模型建立最小能量路径树,但CMRA对于簇头选择的能量分配不均衡,造成簇头结点负载过重。提出一种新的路由算法CMRA-EE（CMRA-energy efficient）,在簇头选举阶段引入节点能量参数,同时将簇头节点能量与距离作为代价参数,从而平衡了网络节点能耗。通过仿真对CMRA-EE算法进行性能分析与评价,结果显示,CMRA-EE算法在延长无线传感网有效生存时间方面比CMRA算法有了明显的改善。     

通用改进扩展Benes型光开关的控制模块设计

分析了通用改进扩展Benes型(GMDB)光开关结构的特性,提出了路由算法设计思路,并详细阐述了4×4GMDB光开关的控制和驱动电路设计。测试结果表明,设计的模块达到了控制的要求。