AN IMPLEMENTATION OF FAST ALGORITHM FOR ELLIPTIC CURVE CRYPTOSYSTEM OVER GF（p）

The design and implementation of fast algorithms related to Elliptic Curve Cryptography (ECC) over the field GF(p), such as modular addition, modular subtraction, point addition, point production, choice of embedding plaintext to a point, etc. are given. A practical software library has been produced which supports variable length implementation of the ECCbased ElGamal cryptosystem. More importantly, this scalable architecture of the design enables the ECC being used in restricted platforms as well as high-end servers based on Intel Pentium CPU. Applications such as electronic commerce security, data encryption communication, etc.are thus made possible for real time and effective ECC.     

关于Montgomery模乘迭代的可控性分析

在公钥密码实现中,Montgomery模乘扮演着非常重要的角色。本文研究Montgomery模乘(MMM)的迭代控制结构,给出了进行MMM迭代的输入边界控制条件,以及改进的MMM算法。这种扩展的迭代控制条件适合用于复杂求幂的迭代过程,在其边界控制下可直接进行一些加法、减法及乘法等基本运算,而无须模约化处理。给出的模乘迭代算法具有高度的灵活性,可利用来实现安全高效的RSA、ECC等公钥密码体制。     

可重构点乘运算的FPGA设计

文章在深入分析ECC点乘运算的FPGA实现的基础上,提出了一种参数可重构的、基于正规基有限域运算的ECC点乘运算结构。该点乘运算结构采用了复用、并行化等措施,在FPGA上实现了GF（2^191）的ECC点乘运算。在Altera FPGA上的仿真结果表明：在50Mhz时钟下,一次点乘运算只需413．28us。     

A State-of-the-art Elliptic Curve Cryptographic Processor Operating in the Frequency Domain

We propose a novel area/time efficient elliptic curve cryptography (ECC) processor architecture which performs all finite field arithmetic operations in the discrete Fourier domain. The proposed architecture utilizes a class of optimal extension fields (OEF) GF(q ^m ) where the field characteristic is a Mersenne prime q = 2 ⁿ  − 1 and m = n. The main advantage of our architecture is that it achieves extension field modular multiplication in the discrete Fourier domain with only a linear number of base field GF(q) multiplications in addition to a quadratic number of simpler operations such as addition and bitwise rotation. We achieve an area between 25k and 50k equivalent gates for the implementations over OEFs of size 169, 289 and 361 bits. With its low area and high speed, the proposed architecture is well suited for ECC in small device environments such as sensor networks. The work at hand presents the first hardware implementation of a frequency domain multiplier suitable for ECC and the first hardware implementation of ECC in the frequency domain.

Hardware Elliptic Curve Cryptographic Processor Over$rm GF(p)$

A novel hardware architecture for elliptic curve cryptography (ECC) over$ GF(p)$is introduced. This can perform the main prime field arithmetic functions needed in these cryptosystems including modular inversion and multiplication. This is based on a new unified modular inversion algorithm that offers considerable improvement over previous ECC techniques that use Fermat's Little Theorem for this operation. The processor described uses a full-word multiplier which requires much fewer clock cycles than previous methods, while still maintaining a competitive critical path delay. The benefits of the approach have been demonstrated by utilizing these techniques to create a field-programmable gate array (FPGA) design. This can perform a 256-bit prime field scalar point multiplication in 3.86 ms, the fastest FPGA time reported to date. The ECC architecture described can also perform four different types of modular inversion, making it suitable for use in many different ECC applications.     

Flexible Hardware Processor for Elliptic Curve Cryptography Over NIST Prime Fields

Exchange of private information over a public medium must incorporate a method for data protection against unauthorized access. Elliptic curve cryptography (ECC) has become widely accepted as an efficient mechanism to secure sensitive data. The main ECC computation is a scalar multiplication, translating into an appropriate sequence of point operations, each involving several modular arithmetic operations. We describe a flexible hardware processor for performing computationally expensive modular addition, subtraction, multiplication, and inversion over prime finite fields $GF(p)$ . The proposed processor supports all five primes $p$ recommended by NIST, whose sizes are 192, 224, 256, 384, and 521 bits. It can also be programmed to automatically execute sequences of modular arithmetic operations. Our field-programmable gate-array implementation runs at 60 MHz and takes between 4 and 40 ms (depending on the used prime) to perform a typical scalar multiplication.      

A Secure Modular Division Algorithm Embedding with Error Detection and Low-Area ASIC Implementation

Modular division operation has important application in public-key cryptosystems. It is the most complex and time-consumed operation in RSA and ECC. Its secure and efficient implementation greatly affects the secure and performance of these cryptosystems. In this paper, a modular division algorithm embedding with error detection is proposed. Four computing types of ASIC implementation architectures (Type-8, Type-16, Type-32, Type-64) are explored to seek the optimal tradeoff among error detection ratio, time overhead and hardware overhead. These implementation architectures are modeled in Verilog language and synthesized using Synopsys Design Compiler with OSU 90 nm CMOS standard cell library. Experiment results show that the proposed Type-64 can get almost 100% error detection probability with an average of 24.71% extra area overhead and 0.52% time overhead. In addition, for the implementation of single modular division module, the proposed Type-64 architecture saves 60.74% area overhead on average with a slight decrease of throughput rate compared with the state-of-the-art re- search. This implementation not only greatly reduces the area overhead of modular division but also improves the security of modular division implementation.     

Customizable elliptic curve cryptosystems

This paper presents a method for producing hardware designs for elliptic curve cryptography (ECC) systems over the finite field GF(2/sup m/), using the optimal normal basis for the representation of numbers. Our field multiplier design is based on a parallel architecture containing multiple m-bit serial multipliers; by changing the number of such serial multipliers, designers can obtain implementations with different tradeoffs in speed, size and level of security. A design generator has been developed which can automatically produce a customised ECC hardware design that meets user-defined requirements. To facilitate performance characterization, we have developed a parametric model for estimating the number of cycles for our generic ECC architecture. The resulting hardware implementations are among the fastest reported: for a key size of 270 bits, a point multiplication in a Xilinx XC2V6000 FPGA at 35 MHz can run over 1000 times faster than a software implementation on a Xeon computer at 2.6 GHz.     

Efficient Implementation of Elliptic Curve Cryptography (ECC) for Personal Digital Assistants (PDAs)

Wireless devices are characterized by low computational power and memory. In addition to this wireless environment are inherently less secure than their wired counterparts, as anyone can intercept the communication. Hence they require more security. One way to provide more security without adding to the computational load is to use elliptic curve cryptography (ECC) in place of the more traditional cryptosystems such as RSA. As ECC provides the same level of security for far less key sizes, as compared to the traditional cryptosystems, it is ideal for wireless security. In this thesis we will investigate the different ways of implementing ECC on wireless devices such as personal digital assistants (PDAs). We will present our findings and compare the different implementations. In our implementation ECC over the field F ⁿ ₂ using optimal normal basis representation gives the best results.     

基于VLIW体系结构的椭圆曲线密码专用指令处理器

The requirement of the flexible and effective implementation of the Elliptic Curve Cryptography (ECC) has become more and more exigent since its dominant position in the public-key cryptography application. Based on analyzing the basic structure features of Elliptic Curve Cryptography (ECC) algorithms, the parallel schedule algorithm of point addition and doubling is presented. And based on parallel schedule algorithm, the Application Specific Instruction-Set Co-Processor of ECC that adopting VLIW architecture is also proposed in this paper. The coprocessor for ECC is implemented and validated using Altera’s FPGA. The experimental result shows that our proposed coprocessor has advantage in high performance and flexibility.     

基于有符号数字系统的Montgomery模逆算法及其硬件实现

 在椭圆曲线密码中,模逆运算是有限域运算中最复杂、最耗时且硬件实现难度最大的运算.本文在Kaliski算法的基础上,提出了基于有符号数字系统的Montgomery模逆算法,它支持素数域和二进制域上任意多精度参数的求模逆运算.据此算法,设计了相应的硬件结构方案,并给出了面积复杂度和时间复杂度分析.仿真结果表明,相比于其它模逆算法硬件设计方案,本文提出的基于有符号数字系统的Montgomery模逆算法在运算速度、电路面积、灵活性等方面具有显著的优越性.     

Elliptic curve cryptography on embedded multicore systems

The increasing use of network-connected embedded devices and online transactions creates a growing demand of network security for embedded systems. The security requirements, such as authentication, confidentiality and integrity, always make computationally intensive processes and can easily become the bottleneck of the related applications. In this paper we implement Elliptic Curve Cryptography (ECC) (Miller in Lecture Notes in Computer Science, vol. 218, pp. 417–426, 1985; Koblitz in Math. Comput. 48:203–209, 1987) on an embedded multicore system, and explore the task scheduling methods in different levels. First, we propose an instruction scheduling method that utilizes all the cores to perform one modular operation in parallel. Second, we perform multiple modular operations with multiple cores in parallel. The performance of those two implementations is compared and a scheduling method combining these two types of parallelism is proposed. We discuss the details of our proposed method by using an FPGA implementation of ECC over a prime field.     

Design and characterization of an error-correcting code for theSONET STS-1 tributary

The authors have designed and characterized a single-error-correcting (SEC), double-error-detecting (DED) code applicable to the STS-1 SONET format. They show that if two of the presently unallocated bytes in the path overhead field of STS-1 are assigned for error-correction coding (ECC), a {6208, 6195} shortened extended Hamming code can be implemented using as few as 660 gates plus a 1-kbyte RAM IC, achieving (O8.6×10^-3 P ₂²) BER reduction with 139 μs of signal delay. The authors explain how the existing BIP-8 error-monitoring byte of the STS-1 format could be integrated with the proposed ECC so that a net allocation of only one new STS-1 overhead byte is required for both error monitoring and error correction. The implementation method is such that all path, line, and section overhead functions in SONET can be performed at intermediate sites without requiring ECC decoding. The authors consider application alternatives and describe the forward-error-correction (FEC) circuit design and trial results. System issues are covered, including network delay, effects of error extension on BER, addition of double-error detection, performance monitoring, and options for intelligent network control and management of FEC functions. Codes related to their path-level design that are applicable to a number of other strategies for applying FEC in SONET are presented     

SATOH算法及快速实现技术研究

随着椭圆曲线公钥密码的广泛应用,怎样生成安全的椭圆曲线是椭圆曲线密码的研究重点,而怎样快速计算椭圆曲线的阶（有理点的个数）是椭圆曲线密码的关键,安全的椭圆曲线密码参数是椭圆曲线密码本身安全的基础,否则会遭受基于Pollard-ρ攻击,反常曲线等安全隐患。公开的文献上主要介绍了SATOH算法的原理,对具体的实现和算法的提升没有做详细的介绍,这里详细介绍了SATOH算法的原理和快速实现方法。     

高性能可扩展公钥密码协处理器研究与设计

 本文提出了一种高效的点乘调度策略和改进的双域高基Montgomery模乘算法,在此基础上设计了一种新型高性能可扩展公钥密码协处理器体系结构,并采用0.18μm 1P6M标准CMOS工艺实现了该协处理器,以支持RSA和ECC等公钥密码算法的计算加速.该协处理器通过扩展片上高速存储器和使用以基数为处理字长的方法,具有良好的可扩展性和较强的灵活性,支持2048位以内任意大数模幂运算以及576位以内双域任意椭圆曲线标量乘法运算.芯片测试结果表明其具有很好的加速性能,完成一次1024位模幂运算仅需197μs、GF(p)域192位标量乘法运算仅需225μs、GF(2^m)域163位标量乘法运算仅需200.7μs.     

一种适用于多种公钥密码算法的模运算处理器

文章设计了一种能够实现多种公钥密码算法（如RSA、ECC、DSA等）的协处理器。通过分析几种常用的公钥密码算法，归纳了一组最常用的基本模运算指令。基于基本指令，设计优化了处理器硬件结构。用微代码循环调用执行这些基本指令，实现其他各种模运算指令。基于这些模运算指令，处理器可实现多种公钥密码算法的运算。该处理器支持从106位到2048位多种长度的模运算。采用流水线结构设计，处理速度较快。处理器占用芯片面积小，核心电路等效门数约为26000门，适用于智能卡等对芯片面积有严格限制的应用。     

Design and implementation of UWB CMOS LC filters LNA for carrier less impulse radio receivers

The design and the implementation of Ultra-wide-band (UWB) CMOS LC filter LNA for Ultra Wide Band carrier less Impulse Radio receivers is presented. Architectures for both single ended and differential ended LNA are proposed for small fractional bandwidths such as the ECC frequency band and for large fractional bandwidths such as FCC frequency band. Simple guidelines to achieve large voltage gain and low noise figure are given. The implementation in standard CMOS technologies in the context of integrated receivers is discussed and simple layout rules allowing reliable designs are proposed. Several LNA prototypes for different fractional bandwidths have been fabricated in a 0.13 μm CMOS technology. Measurement results agree well with the simulations.     

Fast Elliptic Curve Cryptography on FPGA

This paper details the design of a new high-speed pipelined application-specific instruction set processor (ASIP) for elliptic curve cryptography (ECC) using field-programmable gate-array (FPGA) technology. Different levels of pipelining were applied to the data path to explore the resulting performances and find an optimal pipeline depth. Three complex instructions were used to reduce the latency by reducing the overall number of instructions, and a new combined algorithm was developed to perform point doubling and point addition using the application specific instructions. An implementation for the United States Government National Institute of Standards and Technology-recommended curve over GF(2¹⁶³) is shown, which achieves a point multiplication time of 33.05 s at 91 MHz on a Xilinx Virtex-E FPGA-the fastest figure reported in the literature to date. Using the more modern Xilinx Virtex-4 technology, a point multiplication time of 19.55 s was achieved, which translates to over 51120 point multiplications per second.     

A Highly Efficient Cipher Processor for Dual-Field Elliptic Curve Cryptography

This brief presents a high-throughput dual-field elliptic-curve-cryptography (ECC) processor that features all ECC functions with the programmable field and curve parameters over both the prime and binary fields. The proposed architecture is parallel and scalable. Using 0.13-$muhbox{m}$ CMOS technology, the core size of the processor is 1.44 $hbox{mm}^{2}$ . The measured results show that our ECC processor can perform one 160-bit point scalar multiplication with coordinate conversion over the prime field in 608 $muhbox{s}$ at 121 MHz with only 70.0 mW and the binary field in 372 $muhbox{s}$ at 146 MHz with 82.1 mW. The ECC processor chip outperforms other ECC hardware designs in terms of functionality, scalability, performance, cost effectiveness, and power consumption. In addition, the system analysis shows that our design is very efficient, compared with the software implementation for realistic security applications.      

素数域上椭圆曲线快速实现技术研究

随着椭圆曲线公钥密码的广泛应用,怎样快速实现椭圆曲线密码一直是业界关注的重点,在一些应用场景下,如移动、无线领域的应用,对椭圆曲线的实现速度要求较高,目前有许多快速实现椭圆曲线的算法,其性能各有差异.文章全面地研究素数域上的椭圆曲线快速实现技术,如Mersenne素数运算、Fermat定理、Euclidean方法等,并分析了这些方法.在此基础上,给出了详细的素数域上的椭圆曲线完整的实现细节及其关键技术的详细分析和实现方法.用该方法,能快速实现素数域上的椭圆曲线.