Biasing a differential pair in low-voltage analog circuits: a systematic approach

This paper deals with a systematic approach to the common mode and the differential mode biasing of a differential transistor pair. Four different variants will be shown, two of these variants show practical importance; a practical circuit of one of these variants turns out to be the traditional long-tailed pair. This variant is mainly suited, if the input signal operates at voltage level, whereas another variant has great advantages if operation at current level occurs. Besides, the latter variant turns out to be very favorable in circuits operating with a single low supply voltage. Two practical circuits based on this variant are given.     

Analog Switches in Programmable Analog Devices: Quiescent Defective Behaviours

Analog Switches (AS) play an essential role in a large number of Mixed-Signal circuits. Depending on the use of AS, designers have optimised their topology to meet the needs of each specific switching function. Furthermore, the success of Field Programmable devices in the digital domain (FPGAs) has motivated some manufacturers to explore similar solutions to fast prototype in the Analog and Mixed Signal domains. In this work, we explore the defective behaviours of programmable AS under realistic catastrophic and parametric defects. A classification of the DC defective behaviours for bridging and open defects is presented. This classification shows that the simple fault model with faulty state of permanently transistor stuck-on or stuck-off is not sufficient to reflect the real behaviour of a defective switch. It has also been found that parametric defects such as threshold voltage variations are not DC testable, and would therefore require additional AC tests.     

Perspectives on Analytical Modeling of Small Geometry MOSFETs in SPICE for Low Voltage/Low Power CMOS Circuit Design

The present state of the art in analytical MOSFET modeling for SPICE circuit simulation is reviewed, with emphasis on the circuit design usage of these models. It is noted that the model formulation represents an upper limit of what is possible from any type of model, but that good parameter extraction is required to most closely approach that limit. The individual model types presently in common use are examined, with discussion of the behavior of each model, its strengths and weaknesses, its applicability to certain types of circuits, and criteria that a circuit design consumer can employ to judge a model before using it for circuit design. Some related issues, such as node charge and gate capacitance modeling, charge conservation, and statistical simulation of process variations, are also evaluated. Finally, new trends, directions, and requirements of MOSFET modeling for circuit simulation are considered.     

RF CMOS Cells for Wireless Applications

There is increasing interest in the use of CMOS circuits for high frequency highly integrated wireless telecommunications systems. This paper presents the results of on-going work into the development of a cell library that includes many of the circuit elements required for the high frequency sub-systems of communications integrated circuits. The cell library studied included an RF control element, single ended Class A amplifier, RF isolator, and Gilbert cell mixer circuit topologies. Circuit design criteria and measurement results are presented. All cells were fabricated using standard 2.0, 1.2, and 0.8 m CMOS integrated circuit fabrication processes with no post-processing performed. The results indicate that 2.0 m CMOS can be used successfully up to approximately 250 MHz with 0.8 m cells useful up to approximately 1000 MHz.     

A 640 by 480 Pixels Readout Circuit for IR Imaging

A readout circuit for a 640 × 480 pixels FPA (focal plane array) has been successfully designed, fabricated and tested. The circuit solution is based on a per pixel source-follower direct injection (SFDI) pre-amplifier. Signal multiplexing is performed in both X and Y direction. The pixel size is 25 m × 25m. The chip is optimized for a QWIP (quantum well infrared photodetector) operating at a temperature of 70 K. The circuit has been realized in a standard 0.8 m CMOS process.     

On the structure of the privacy hierarchy

An N argument function f(x ₁,...,x _N ) is called t-private if a protocol for computing f exists so that no coalition of at most t parties can infer any additional information from the execution, other than the value of the function. The motivation of this work is to understand what levels of privacy are attainable. So far, only two levels of privacy are known for N argument functions which are defined over finite domains: functions that are N-private and functions that are (N – 1)/2-private but not N/2-private.In this work we show that the privacy hierarchy for N-argument functions which are defined over finite domains, has exactly (N + 1)/2 levels. We prove this by constructing, for any N/2 t N – 2, an N-argument function which is t-private but not (t + 1)-private.This research was supported by US-Israel Binational Science Foundation Grant 88-00282.     

Diagnostic simulation of stuck-at faults in combinational circuits

Two faults are said to be equivalent, with respect to a test set , iff they cannot be distinguished by any test in . The sizes of the corresponding equivalence classes of faults are used as a basis for comparing the diagnostic capability of two given test sets. A novel algorithm, called multiway list splitting, for computing the Equivalence Classes of stuck-at faults, in combinational (full scan) circuits, with respect to a given test set is presented. Experimental results presented show the algorithm to be more efficient than previously known algorithms based on decision diagrams and diagnosibility matrix.Portions of this work were presented in [1].Research Supported by NFS Grant No. MIP9102509.Research Supported by SRC Grant 93-DP-109.     

Noise considerations for mixed‐signal RF IC transceivers

This paper discusses design tradeoffs for mixedsignal radio frequency integrated circuit (RF IC) transceivers for wireless applications in terms of noise, signal power, receiver linearity, and gain. During air wave transmission, the signal is corrupted by channel noise, adjacent interfering users, image signals, and multipath fading. Furthermore, the receiver corrupts the incoming signal due to RF circuit nonlinearity (intermodulation), electronic device noise, and digital switching noise. This tutorial paper gives an overview of the design tradeoffs needed to minimize RF noise in an integrated wireless transceiver. Fundamental device noise and the coupling of switching noise from digital circuits to sensitive analog sections and their impact on RF circuits such as frequency synthesizers are examined. Methods to minimize mixedsignal noise coupling and to model substrate noise effects are presented.     

Gaussian radial basis functions and inner product spaces

An approximation result is given concerning Gaussian radial basis functions in a general inner product space. Applications are described concerning the classification of the elements of disjoint sets of signals, and also the approximation of continuous real functions defined on all of ⁿ using radial basis function (RBF) networks. More specifically, it is shown that an important large class of classification problems involving signals can be solved using a structure consisting of only a generalized RBF network followed by a quantizer. It is also shown that Gaussian radial basis functions defined on ⁿ can uniformly approximate arbitrarily well over all of ⁿ any continuous real functionalf on ⁿ that meets the condition that |f(x)|0 as x.     

1 V All-MOS ΣΔ A/D Converters in the Log-domain

This paper presents novel low-voltage all-MOS analog circuit techniques for the synthesis of oversampling A/D converters. The new approach exploits the possibilities of Log-domain processing by using the MOSFET in subthreshold operation. Based on this strategy, a complete set of very low-voltage (down to 1 V) low-power (below 100 W) all-MOS basic building blocks is proposed. The resulting analog circuit techniques allow the integration of A/D converters for low-frequency (below 100 KHz) applications in digital CMOS technologies. Examples are given for a standard 0.35 m VLSI process.     

Predictive Caching Strategy for On-Demand Routing Protocols in Wireless Ad Hoc Networks

Route caching strategy is important in on-demand routing protocols in wireless ad hoc networks. While high routing overhead usually has a significant performance impact in low bandwidth wireless networks, a good route caching strategy can reduce routing overheads by making use of the available route information more efficiently. In this paper, we first study the effects of two cache schemes, link cache and path cache, on the performance of on-demand routing protocols through simulations based on the Dynamic Source Routing (DSR) protocol. Since the path cache DSR has been extensively studied, we focus in this paper on the link cache DSR in combination with timer-based stale link expiry mechanisms. The effects of different link lifetime values on the performance of routing protocol in terms of routing overhead, packet delivery ratio and packet latency are investigated. A caching strategy incorporating adaptive link timeout is then proposed, which aims at tracking the optimal link lifetime under various node mobility levels by adaptively adjusting the link lifetime based on the real link lifetime statistics. The performance of the proposed strategy is then compared with the conventional path cache DSR. The results show that without a timeout mechanism, a link cache scheme may suffer severe performance degradation due to the use of broken routes, while the proposed adaptive link cache strategy achieves significantly improved performance by reducing the routing overhead when the network traffic load is high.     

Scheduling and bandwidth allocation for the distribution of archived video in VOD systems

Providing costeffective videoondemand (VOD) services necessitates reducing the required bandwidth for transporting video over highspeed networks. In this paper, we investigate efficient schemes for transporting archived MPEGcoded video over a VOD distribution network. A video stream is characterized by a timevarying traffic envelope, which provides an upper bound on the bit rate. Using such envelopes, we show that video streams can be scheduled for transmission over the network such that the perstream allocated bandwidth is significantly less than the source peak rate. In a previous work [13], we investigated stream scheduling and bandwidth allocation using global traffic envelopes and homogeneous streams. In this paper, we generalize the scheduling scheme in [13] to include the heterogeneous case. We then investigate the allocation problem under windowbased traffic envelopes, which provide tight bounds on the bit rate. Using such envelopes, we introduce three streamscheduling schemes for multiplexing video connections at a server. The performance of these schemes is evaluated under static and dynamic scenarios. Our results indicate a significant reduction in the perstream allocated bandwidth when stream scheduling is used. While this reduction is obtained through statistical multiplexing, the transported streams are guaranteed stringent, deterministic quality of service (i.e., zero loss rate and small, bounded delay). In contrast to video smoothing, our approach requires virtually no buffer at the settop box since frames are delivered at their playback rate.     

A scalable wireless virtual LAN

This paper presents a Wireless Virtual Local Area Network (WVLAN) to support mobility in IPoverATM local area networks. Mobility is handled by a joint ATMlayer handoff for connection rerouting and MAClayer handoff for location tracking, such that the effects of mobility are localized and transparent to the higherlayer protocols. Different functions, such as Address Resolution Protocol (ARP), mobile location, and ATM connection admission are combined to reduce protocol overhead and frontend delay for connectionless packet transmission in connectionoriented ATM networks. The proposed WVLAN, through the use of ATM technology, provides a scalable wireless virtual LAN solution for IP mobile hosts.     

Synthesis of arbitrary digital transfer functions using allpass-based structures derived via LBR two-pair extraction procedure

The implementation of a digital filter transfer function with all transmission zeros on the unit circle is developed via the synthesis of an appropriate allpass function. The synthesis procedure is based on the LBR-extraction approach. The resulting structure is in the form of a doubly terminated cascade of lossless (LBR) two-pairs, with each two-pair realizing a single real or a pair of complex transmission zeros. The Concepts of complete and partial 1 removals, and 1 shifting are introduced and utilized during the synthesis process. The resulting structures have several properties in common with the Gray and Markel lattice filters, but do not require tap coefficients for numerator realization. The building blocks used in this paper are similar to those in certain wave-digital filters and orthogonal filters.Work supported in part by NSF Grant Number ECS 82-18310 and in part by NSF Grant Number ECS-8508017.     

Mobility Management for Hierarchical Wireless Networks

In this paper, we consider the mobility management in large, hierarchically organized multihop wireless networks. The examples of such networks range from battlefield networks, emergency disaster relief and law enforcement etc. We present a novel network addressing architecture to accommodate mobility using a Home Agent concept akin to mobile IP. We distinguish between the physical routing hierarchy (dictated by geographical relationships between nodes) and logical hierarchy of subnets in which the members move as a group (e.g., company, brigade, battalion in the battlefield). The performance of the mobility management scheme is investigated through simulation.     

β-bit serial/parallel multipliers

A generalized -bit least-significant-digit (LSD) first, serial/parallel multiplier architecture is presented with 1n wheren is the operand size. The multiplier processes both the serial input operand and the double precision product -bits per clock cycle in an LSD first, synchronous fashion. The complete two's complement double precision product requires 2n/ clock cycles. This generalized architecture creates a continuum of multipliers between traditional bit-serial/parallel multipliers (=1) and fully-parallel multipliers (=n). -bit serial/parallel multipliers allow anoptimized integrated circuit arithmetic to be designed based on a particular application's area, power, throughput, latency, and numerical precision constraints.This project was pratically funded by the UCSD-NSF I/UCR Center on Ultra-High Speed Intergrated Circuits and Systems.     

Systematic Width-and-Length Dependent CMOS Transistor Mismatch Characterization and Simulation

This paper presents a methodology for characterizing the random component of transistor mismatch in CMOS technologies. The methodology is based on the design of a special purpose chip which allows automatic characterization of arrays of NMOS and PMOS transistors of different sizes. Up to 30 different transistor sizes were implemented in the same chip, with varying transistors width W and length L. A simple strong inversion large signal transistor model is considered, and a new five parameters MOS mismatch model is introduced. The current mismatch between two identical transistors is characterized by the mismatch in their respective current gain factors /, V _TO threshold voltages , bulk threshold parameters , and two components for the mobility degradation parameter mismatch ₀ and _e. These two components modulate the mismatch contribution differently, depending on whether the transistors are biased in ohmic or in saturation region. Using this five parameter mismatch model, an extraordinary fit between experimental and computed mismatch is obtained, including minimum length (1 m) transistors for both ohmic and saturation regions. Standard deviations for these five parameters are obtained as well as their respective correlation coefficients, and are fitted to two dimensional surfaces f(W, L) so that their values can be predicted as a function of transistor sizes. These functions are used in an electrical circuit simulator (Hspice) to predict transistor mismatch. Measured and simulated data are in excellent agreement.     

Symmetry relations in multidimensional Fourier transform pairs

A relation between the types of symmetries that exist in signal and Fourier transform domain representations is derived for continuous as well as discrete domain signals. The symmetry is expressed by a set of parameters, and the relations derived in this paper will help to find the parameters of a symmetry in the signal or transform domain resulting from a given symmetry in the transform or signal domain respectively. A duality among the relations governing the conversion of the parameters of symmetry in the two domains is also brought to light. The application of the relations is illustrated by a number of two-dimensional examples.Notation R the set of real numbers - R ^m R × R × ... × R m-dimensional real vector space - continuous domain real vector - L {¦ – _i , i = 1,2,..., m} - m-dimensional frequency vector - W { – _i ,i=1,2,..., m} - m-dimensional normalized frequency vector - _P {¦ – _i , i=1,2,...,m} - g(ol) g (₁,₂,..., _m ) continuous domain signal - () ( _{1 2},..., _m )=G (j ₁,j ₂,..., j _m ) Fourier transform ofg (ol) - (A,b,,,) parameters ofT- symmetry - N the set of integers - N ^m N × N × ... × N m-dimensional integer vector spacem-dimensional lattice - h(n) h (n ₁,.,n _m ) discrete domain signal - H() Fourier transform ofh (n) - v ₁,v ₂,..., v_m m sample-direction and interval vectors - V (v ₁ v ₂ ...v _m ) sampling basis matrix - [x]^* complex conjugate ofx - detA determinant ofA - X {x¦ – x _i , i=1,2,..., m} - A ^–t [A ^–1] ^t ,t stands for transpose This work was supported in part by the Natural Sciences and Engineering Research Council of Canada under Grant A-7739 to M. N. S. Swamy and in part by Tennessee Technological University under its Faculty Research support program to P. K. Rajan.     

Linear phase FIR approximation of magnitude response |1/ω| for maximal flatness at an arbitrary frequency ω0, 0<ω0<π*

In many signal processing situations, the desired (ideal) magnitude response of the filter is a rational function: (a digital integrator). The requirements of a linear phase response and guaranteed stable performance limit the design to a finite impulse response (FIR) structure. In many applications we require the FIR filter to yield a highly accurate magnitude response for a narrow band of frequencies with maximal flatness at an arbitrary frequency ₀ in the spectrum (0, ). No techniques for meeting such requirements with respect to approximation of are known in the literature. This paper suggests a design by which the linear phase magnitude response can be approximated by an FIR configuration giving a maximally flat (in the Butterworth sense) response at an arbitrary frequency ₀, 0<₀<^*. A technique to compute exact weights for the design has also been given.     

N-order direct form digital filters with integer arithmetic

For direct form digital filters with integer arithmetic, a characterization of the initial condition vector and state vectorX(), for a fixed, > 1, is established without the intermediate state vectors. This is used to determine initial conditions for stability and initial conditions for convergence to a limit cycle. Also, several properties of limit cycles are proven.