基于神经网络的功率放大器预失真建模

提出一种神经网络结合分离信号对功率放大器预失真建模的方法。将输入/输出信号的线性与非线性部分分开处理,利用神经网络良好的逼近能力,采用LM算法,拟合出功率放大器特性曲线,进而建立预失真模型,使非线性功率放大器的输入/输出曲线整体呈线性化。在保证输出幅度限制和输出功率最大化的前提下,与未作信号分离的神经网络建模方法、多项式建模方法以及Saleh函数模型方法相比较,发现信号分离神经网络建模方法能得到较小的归一化均方误差和误差矢量幅度。仿真结果表明,采用信号分离神经网络对功率放大器及其预失真建模,整体线性化误差较小、精度高、效果更佳。     

记忆多项式数字预失真线性化逆E类功放

采用记忆多项式模型的数字预失真器,用于线性化逆E类射频功率放大器,从而获得具有高线性和高效率的射频放大系统,使得开关型的逆E类功率放大器可以适用于具有非恒包络的调制信号的发射。文中设计了一个工作于S频段的具有10W饱和功率的逆E类功率放大器,以具有5MHz信号带宽的单载波WCDMA信号作为测试信号,使用记忆多项式的预失真器对其进行线性化。实验表明,该记忆多项式预失真器能够很好地抑制逆E类功放的动态非线性引起的带外寄生频谱,可以使逆E类功放同时工作于高线性和高效率状态。     

基于改进型径向基函数神经网络的功放线性化

提出了一种基于改进型径向基函数神经网络(MRBFNN)的数字预失真线性化模型,用于更为精确地矫正宽带射频功率放大器的动态非线性。该神经网络模型的输入层使用传统的延时抽头以补偿功放的线性记忆效应,同时对每个抽头进行级数展开用于补偿功放的非线性记忆效应,从而更好地抑制功放的动态非线性失真。文中使用WCDMA 三载波信号对一个460MHz 的Doherty 功率放大器进行数字预失真线性化实验。实验结果表明,与传统数字预失真线性化模型相比,基于改进型径向基神经网络的数字预失真线性化模型能更好地抑制宽带功放动态非线性引起的带外频谱再生,其三阶互调(IMD3)失真最多可以抑制23dB,大大提高了功放的线性度,验证了所提出的数字预失真线性化模型的有效性。     

用于5G RF PA 线性化的多频段通用数字预失真器

文中提出了一种基于独热编码与长短时期记忆 (LSTM) 神经网络的多频段通用数字预失真非线性 模型,它可以有效地对工作在多个频段的宽带射频功放进行线性化。在训练集中引入表示不同频率信号的不同独 热编码,训练后的神经网络非线性模型可以在不改变网络结构和模型参数的情况下对不同频段的功率放大器进行 预失真线性化。为了验证该方法的有效性,建立了两个分别工作于2. 6 GHz 和4. 9 GHz 的射频功放实验平台,在这 两个频段预失真非线性建模的归一化均方误差(NMSE)均可达到-40 dB,然后使用100 MHz 带宽5G NR 信号,分别 对这两个射频功放进行预失真线性化实验验证。实验结果表明,该多频段通用数字预失真器可以将这两个功放的 邻信道泄漏比(ACLR)在中心频率下偏100 MHz 处分别改善19. 42 dB 和17. 91 dB,在中心频率上偏100 MHz 处分 别改善15. 73 dB 和15. 17 dB,验证了所提非线性模型的有效性。     

基于蚁狮算法优化的BP-RBF 功放行为模型研究

为了准确描述射频功率放大器特性,在仿真过程中,建立一个良好的功放行为模型就变得极其关键。文中提出了一种基于蚁狮算法(Ant Lion Optimizer,ALO)优化的BP-RBF 级联神经网络射频功放行为模型,首先,采用飞思卡尔半导体芯片设计射频功放电路,对从设计的电路中提取出的电压数据进行处理,然后利用蚁狮种群中的多个个体并行寻优的能力,优化BP-RBF 神经网络的权值和阈值,对改进优化后的ALOBP-RBF 神经网络模型进行MATLAB 仿真,通过比较电压均方根误差验证模型精确性。仿真结果表明,相比于BP-RBF、GABP-RBF 模型,该模型具有更高的精度、更快的收敛速度,可以精确地模拟功率放大器的特性,对射频电路的建模具有重要意义。     

基于神经网络的宽带功放动态非线性行为建模

文章主要讨论了如何利用神经网络对宽带功放进行动态非线性行为建模的问题。首先简述了功放的动态非线性特性及行为建模的方法。然后回顾了基于实数时延前馈神经网络、径向基函数神经网络等浅层神经网络构建的功放动态非线性行为模型。在此基础上,针对5G/6G宽带功放具有更强的记忆效应的问题,重点分析了如何使用长短期记忆(LSTM)神经网络对功放的动态非线性进行精确的行为建模。最后展望了构建具有普适性的功放非线性行为模型将是5G/6G通信时代功放非线性建模的一个重要发展方向。     

基于动态小波神经网络非线性预测的语音编码系统

现在,所有的语音编码系统都采用线性预测技术,但对于本质非线性的语音信号而言,线性预测是不够的.因此,本文提出一种带反馈单元的动态小波神经网络并将其应用于语音编码系统,并对其函数逼近能力和学习高维函数的优越性进行分析.由于反馈单元的内部记忆能力,动态神经网络具有对长时相关的预测能力并能在一定程度上克服小波神经网络的"维数灾难"问题;在对语音信号的预测中,动态小波神经网络预测器的预测性能很好,虽然其预测阶数很低(仅为2).由于预测器较好的预测性能,当将此预测器用于语音编码系统中的后向预测时,实验结果表明:新系统的恢复语音平均分段信噪比比ITU的G.721标准提高3～4dB但二者码率相同.另外非线性预测语音编码系统的计算量是可以接受的.     

基于Volterra-Laguerre模型的D类功率放大器建模

D类功率放大器是现代电子系统的重要部件,它存在非线性特性。在D类功放中,电源噪声与输入信号互调,容易产生互调失真。文章基于Volterra-Laguerre模型研究D类功放中的这种非线性失真,应用Laguerre序列简化线性系统的原理,将Volterra级数模型拓展为Volterra-Laguerre扩展模型,该模型较传统Volterra级数模型减少了辨识量,提高了辨识速度。     

基于PSO_BP神经网络的射频功放行为模型

神经网络具有模拟任意非线性系统的优势。考虑到射频功放的非线性和记忆效应,在BP神经网络模型的基础上,提出一种基于PSO的BP神经网络射频功放行为模型。利用飞思卡尔(Freescale)半导体晶体管MRF6S21140器件模型及设计的电路,从ADS中导出输入输出数据,对模型进行了仿真实现,得出输出电压幅度的拟合曲线以及均方根误差,并与BP神经网络模型进行比较。仿真结果表明,所提模型具有较高的精度和较好的逼近能力,可以精确模拟功率放大器的特性,对系统仿真的构建具有重要的应用价值。     

有记忆效应的功放实数延时模糊神经网络模型

描述了一种基于实数延时模糊神经网络的有记忆效应的功率放大器模型.该模糊神经系统即自适应模糊神经推理系统,采用模糊c类均值聚类方法来减少模型的规则数目和简化模型结构.在训练过程中,采用最小二乘和反向传播相结合的高效算法提取模型参数.在测试平台上用三载波WCDMA宽带信号对射频功率放大器进行测试,并借助矢量信号分析仪采样功率放大器输入和输出数据,成功地对模型进行了训练和验证.通过和实数延时神经网络模型(RVTDNN)比较,该模型的收敛速度远快于这些前馈结构的神经网络模型.比较和分析时域和频域结果表明模型有很好的性能,其归一化均方误差达-38dB.     

Boost bridge amplifier

A novel boost bridge amplifier which inherently doubles the power supply voltage, thus providing up to four times higher peak output power than a comparable state-of-the-art class-D amplifier, is proposed. The efficiency and the total harmonic distortion of both amplifiers during the amplification of a music signal are shown to be similar     

An integrated 200-W class-D audio amplifier

An integrated stereo class-D audio power amplifier realized in a silicon-on-insulator (SOI)-based BCD technology is presented. The amplifier is capable of delivering 2/spl times/100 W in two 4-/spl Omega/ loads at a supply voltage of 60 V. A second-order feedback loop is used to suppress supply ripple and pulse-shape errors in the switching power stage. The limiting factor in the performance of any class-D amplifiers is the quality of the switching power stage. A high-speed low-current levelshifter and a robust deadtime control arrangement are proposed that enable the realization of a robust high-quality switching power stage. Some practical issues with respect to robustness and electromagnetic compatibility are discussed.     

Performance comparison of integrated fully-differential filterless class-D amplifiers with different feedback techniques

Two integrated stereo fully differential filterless class-D amplifiers are presented in this paper. The object is to develop a modulation of a class-D audio amplifier with high power efficiency in this paper. The traditional H-bridge class-D audio amplifier has a shortcoming of large signal distortion which is worse than realized. However, the proposed circuit improves the drawback and provides high power efficiency at the same time. The circuit implements a modified scheme of pulse-width modulation. In this paper, we presented two class-D amplifiers, compared their differences and explained why the efficiency and distortion performance can be modified. The increase in total harmonic distortion (THD) is due to non-linearity in the triangle wave. To overcome this problem, a negative feedback from the output of the switching power stage is adopted to reduce the THD. When a 0.7-V_PP and 1 kHz sine wave is used as an input signal, the minimum THD is 0.029 % and the maximum power efficiency is 83 %. The fully differential class-D audio amplifier is implemented with a TSMC 0.35-μm 2P4M CMOS process, and the chip area is 2.57 × 2.57 mm² (with PADs).     

A 280 mW, 0.07% THD+N class-D audio amplifier using a frequency-domain quantizer

Pulse density modulation (PDM) based class-D amplifiers can reduce non-linearity and tonal content due to carrier signal in pulse width modulation based amplifiers. However, their low-voltage analog implementations also require a linear loop filter and a quantizer. A PDM based class-D audio amplifier using a frequency-domain quantization is presented. The digital intensive frequency-domain approach achieves high linearity under low supply regimes. An analog comparator and a single-bit quantizer are replaced with a current controlled oscillator (ICO) based frequency discriminator. By using the ICO as a phase integrator, a third-order noise shaping is achieved using only two analog integrators. A single-loop, single-bit, class-D audio amplifier is presented with an H-bridge switching power stage, which is designed and fabricated on a 0.18???m CMOS process with 6 layers of metal achieving a total harmonic distortion plus noise (THD+N) of 0.065% and a peak power efficiency of 80% while driving a 4-?? loudspeaker load. The amplifier can deliver the output power of 280 mW.     

A THD-reduction high-efficiency audio amplifier using inverter-based OTAs with filter-output feedback

This paper presents an integrated low-voltage THD-reduction high-efficiency class-D audio amplifier using inverter-based operational transconductance amplifiers (OTAs). We propose a negative feedback loop which can compensate for external perturbations and improving output precision. The compensator increases the audio-frequency loop gain, and leads to a better rejection of audio-frequency disturbances. The use of inverter-based OTA and comparator provides low-voltage operation and low-power dissipation. The audio amplifier operates with a 1.5 V supply voltage with maximum power efficiency of 90%. The proposed class-D amplifier was implemented using a TSMC 0.18-μm 1P6M CMOS process, and the active chip area is 1.87 mm².     

A design methodology for high-order class-D audio amplifiers

This paper presents a design methodology for high-order class-D amplifiers, based on their similarity with sigma–delta ( $\Upsigma\Updelta$ ) modulators, for which established theory and toolboxes are available. The proposed methodology, which covers the entire design flow, from specifications to component sizing, is validated with three design examples, namely a second-order, a third-order, and a fourth-order class-D amplifier. Moreover, the third-order class-D amplifier has been integrated on silicon and characterized, further confirming the validity of the whole design flow. The achieved results demonstrate that high-order class-D amplifiers can achieve total-harmonic-distortion (THD) performance compatible with the specifications of high-end audio applications (THD  ≈ 90 dB), which would be unfeasible with conventional first-order class-D amplifiers.     

CMOS Outphasing Class-D Amplifier With Chireix Combiner

This letter presents a CMOS outphasing class-D power amplifier (PA) with a Chireix combiner. Two voltage-mode class-D amplifiers used in the outphasing system were designed and implemented with a 0.18-mum CMOS process. By applying the Chireix combiner technique, drain efficiency of the outphasing PA for CDMA signals was improved from 38.6% to 48% while output power was increased from 14.5 to 15.4 dBm with an adjacent channel power ratio of -45 dBc.