基于螺旋谐振环结构的UWB同步开关噪声抑制电源平面

针对目前印制电路板中采用的同步开关噪声抑制方法抑制带宽较窄、全向性较差、电源平面有效使用面积小、结构复杂及对信号质量影响大的问题,提出了一种基于螺旋谐振环结构的超宽带同步开关噪声抑制平面,具有结构简单、阻带宽、抑制方向具有全向性、无需周期性电磁带隙结构的特点。通过研究其等效电路模型,使用三维有限元法( FEM)对所设计的结构提取了S参数,并进行了频域与时域分析与仿真。仿真结果表明：所提出的结构其同步开关噪声抑制深度在-40 dB时,阻带范围为0.13~20 GHz,抑制带宽达到19.87 GHz,有效降低了带隙中心频率;当注入噪声电压为1 V时,可将噪声电压抑制到0.25 mV;对比UC-EBG和Planar EBG结构,在-40 dB抑制深度时,抑制带宽分别提高了16.97 GHz和17.73 GHz。     

介质型EBG结构对同步开关噪声抑制的有限元分析

研究了介质型电磁带隙结构对高速电路中电源/ 地平面间同步开关噪声的抑制作用。该介质型电磁带隙结构在抑制同步开关噪声的同时未破坏高速信号的电流返回路径,使高速信号的信号完整性得以保持。利用电磁场有限元方法将电源/地平面间同步开关噪声抑制的三维问题转化成二维问题进行处理,提高了计算效率。分析了介质型电磁带隙结构的介电常数对噪声抑制带宽的影响,利用了三维全波电磁场仿真软件HFSS对二维数值结 果进行仿真验证,仿真结果与数值计算结果基本吻合,验证了二维数值算法的正确性。     

PCB地平面的分割

一个完整的地平面能减少电路板的EMI和串扰问题。在数模混合布板时,数字电路的同步开关噪声往往会影响敏感的模拟电路。分割的地平面能够提供高的噪声隔离度,但同时也会引起另外的一些EMI问题。文章就如何正确的分割地平面以及为什么这样分割进行了讨论,并给出了地分割的相应设计原则。     

地平面的分割

一个完整的地平面能减少电路板的EMI和串扰问题。在数模混合布板时,数字电路的同步开关噪声往往会影响敏感的模拟电路。分割的地平面能够提供高的噪声隔离度,但同时也会引起另外的一些EMI问题。本文就如何正确的分割地平面以及为什么这样分割进行了讨论,并给出了地分割的相应设计原则。     

参考平面的分割

一个完整的地平面能减少电路板的EMI和串扰问题。在数模混合布板时,数字电路的同步开关噪声往往会影响敏感的模拟电路。分割的地平面能够提供高的噪声隔离度,但同时也会引起另外的一些EMI问题。文章就如何正确地分割地平面以及为什么这样分割进行了讨论,并给出了地分割的相应设计原则。     

基于ANSYS 的DDR4 SDRAM 信号完整性仿真方法研究

半导体技术快速发展,双倍数据速率同步动态随机存取存储器(Double Data Rata Synchronous Dynamic Random Access Memory, DDR SDRAM)的信号完整性问题已成为设计难点。文中提出了一种基于ANSYS 软 件和IBIS 5. 0 模型的DDR4 SDRAM 信号完整性仿真方法。利用IBIS 5. 0 模型中增加的复合电流(Composite Current) 、同步开关输出电流等数据,对DDR4 SDRAM 高速电路板的信号完整性进行更准确的仿真分析。仿真结果 表明:高速信号在经过印制板走线和器件封装后,信号摆幅和眼图都有明显恶化;在仿真电路的电源上增加去耦 电容后,信号抖动和收发端同步开关噪声(Synchronous Switching Noise, SSN)都得到明显改善;在不加去耦电容的 情况下,将输入信号由PRBS 码换成DBI 信号,接收端的同步开关噪声有所改善,器件功耗可以降为原来的一半。     

抑制SSN的新型内插L-EBG结构

本文提出的是一种基于平面型EBG (Electromagnetic Bandgap)结构的创新型结构,对于同步开关噪声(Simultaneous Switching Noise, SSN)的抑制有更优秀的特性。我们设计的这款新型EBG结构,是在周期性L-bridge EBG结构的基础上,在一些单元内插小型的L-bridge EBG。通过仿真验证,此结构具有传统型L-bridge EBG结构所不具有的超带宽抑制能力和较大的抑制深度。然后我们运用电路模型和平行板谐振腔原理分析了该结构上下变频。另外,通过3-D仿真,得到结构的IR-Drop和直流阻抗。最后,通过眼图验证该结构的信号传输特性。     

高密度陶瓷封装电设计中噪声控制研究

随着陶瓷封装电路密度、频率和速度不断提高,电信号噪声问题凸显。信号噪声本质上源于传输线本身存在的寄生电阻、电容、电感与电信号作用导致的一系列信号质量下降、参考电位不稳定等问题。高频高密度陶瓷电设计常见的信号噪声问题包括反射、串扰和同步开关噪声等。文章分析了陶瓷封装设计中三类噪声产生的原因、危害及解决措施,并基于信号/电源完整性理论,介绍了一款高频高密度陶瓷基板的封装电设计。     

一种抑制同步开关噪声的新颖电磁带隙结构

电源平面与接地平面间的同步开关噪声是现代高速、高性能数字电路应用的瓶颈之一。文中提出了一种应用于印刷电路板的新颖二维电磁带隙（MS-EBG）结构,其单位晶格由折线缝隙组合与正方形贴片桥接构成,以抑制同步开关噪声。结果表明,抑制深度为-30 dB时,与传统L-bridged EBG结构比较,新EBG结构的阻带宽度增加1.3 GHz,相对带宽提高了约10%,能够有效抑制0.6～5.9 GHz的同步开关噪声。     

同步开关噪声抑制的分析与研究

目前,数字集成电路朝着高功率,低电压的方向发展,电源地平面上的同步开关噪声成为高速设计的主要瓶颈之一。文章阐述了同步开关噪声的形成原理和产生问题,详细分析了现有抑制SSN的主要方法,最后通过结构图和仿真效果图重点介绍电磁带隙结构（EBG）的设计方法、研究思路和最新发展趋势.为今后的实际应用研究提供一定的参考指导。     

Electromagnetic interference (EMI) reduction from printed circuit boards (PCB) using electromagnetic bandgap structures

As digital circuits become faster and more powerful, direct radiation from the power bus of their printed circuit boards (PCB) becomes a major concern for electromagnetic compatibility engineers. In such multilayer PCBs, the power and ground planes act as radiating microstrip patch antennas, where radiation is caused by fringing electric fields at board edges. In this paper, we introduce an effective method for suppressing PCB radiation from their power bus over an ultrawide range of frequencies by using metallo-dielectric electromagnetic band-gap structures. More specifically, this study focuses on the suppression of radiation from parallel-plate bus structures in high-speed PCBs caused by switching noise, such as simultaneous switching noise, also known as Delta-I noise or ground bounce. This noise consists of unwanted voltage fluctuations on the power bus of a PCB due to resonance of the parallel-plate waveguiding system created by the power bus planes. The techniques introduced here are not limited to the suppression of switching noise and can be extended to any wave propagation between the plates of the power bus. Laboratory PCB prototypes were fabricated and tested revealing appreciable suppression of radiated noise over specific frequency bands of interest, thus, testifying to the effectiveness of this concept.     

A simple finite-difference frequency-domain (FDFD) algorithm for analysis of switching noise in printed circuit boards and packages

Simultaneous switching noise (SSN) compromises the integrity of the power distribution structure on multilayer printed circuit boards (PCB). Several methods have been used to investigate SSN. These methods ranged from simple lumped circuit models to full-wave (dynamic) three-dimensional Maxwell equations simulators. In this work, we present an efficient and simple finite-difference frequency-domain (FDFD) based algorithm that can simulate, with high accuracy, the capacity of a PCB board to introduce SSN. The FDFD code developed here also allows for simulation of real-world decoupling capacitors that are typically used to mitigate SSN effects at sub 1 GHz frequencies. Furthermore, the algorithm is capable of including lumped circuit elements having user-specified complex impedance. Numerical results are presented for several test boards and packages, with and without decoupling capacitors. Validation of the FDFD code is demonstrated through comparison with other algorithms and laboratory measurements.     

PCB板设计中的接地方法与技巧

本文分析PCB印刷电路板信号接地设计中产生接地噪声及电磁幅射的原因和对策.并通过单点接地、多点接地、混合接地、模拟电路接地、数字电路接地介绍了PCB印刷电路板接地的设计思路、设计方法与技巧.     

Modeling and Measurement of Interlevel Electromagnetic Coupling and Fringing Effect in a Hierarchical Power Distribution Network Using Segmentation Method With Resonant Cavity Model

A hierarchical power distribution network (PDN) consists of chip, package, and printed circuit board (PCB) level PDNs, as well as various structures such as via, ball, and wire bond interconnections, which connect the different level PDNs. When estimating the simultaneous switching noise (SSN) generation and evaluating PDN designs, PDN impedance calculation is an efficient criterion. In this paper, we introduce two new kinds of modeling approaches that are exceptionally suited to improving the accuracy of the PDN impedance estimation, especially for hierarchical PDN. First, we propose a modeling procedure to add an interlevel electromagnetic coupling effect between PDNs of different levels, based on the resonant cavity model and segmentation method. In order to effectively consider the interlevel electromagnetic coupling effect, we introduce a new concept of interlevel PDN, which is, for example, composed of a metal plate in the package-level PDN and a metal plate in the PCB-level PDN. Next, we present a modeling procedure to include the fringing field effect at the edge of small-size PDN structure, which causes a considerable shift of cavity resonance frequencies in the PDN impedance profile. In order to verify the proposed modeling approaches, we have fabricated a series of test vehicles by combining two package-level PDN designs with a PCB-level PDN design. Finally, we have successfully validated the proposed modeling approaches with a series of frequency-domain measurements in a frequency range up to 5 GHz.      

Simultaneous switching noise mitigation in PCB using cascaded high-impedance surfaces

A novel concept for ultra-wide-bandwidth suppression of simultaneous switching noise (SSN) in high-speed printed circuit boards (PCBs) is proposed and implemented. This method consists of cascading high-impedance surfaces (HIS) with different stop bands, creating rejection over a wide frequency region. A PCB with the cascaded HIS design has been successfully fabricated and tested.     

高速PCB 信号完整性仿真与分析

针对如何能缩短电路设计开发流程和提高设计人员工作效率,本文主要提出了如何有效解决信号完整性问题。 介绍了一种信号完整性分析的方法,使用IBIS 模型进行信号完整性分析,通过加载芯片的IBIS 模型对高速PCB 板进行 仿真,并对仿真结果进行优化分析,达到验证设计的目的。     

基于HyperLynx的断路器状态监测无线节点PCB信号完整性分析

信号完整性问题在断路器状态监测无线节点PCB板设计中越来越明显,解决其信号完整性问题越来越重要.本文利用HyperLynx软件针对PCB板产生的反射和串扰问题进行布线前建模仿真和PCB布线后仿真分析后,将反射产生的过冲幅值降低至约100 mV,将串扰产生的过冲幅值控制在约60 mV.仿真结果表明,建立的反射、串扰模型适...     

HDI PCB的地平面设计

高密度印制电路板(PCB)设计中,地平面直接影响着整个电路性能和电磁兼容性能.该文基于3G无线终端电路实例,深入研究了高密度互连(HDI)PCB中的地平面设计,并提出了地平面的分割和缝合法,以及全屏蔽措施.采用该设计可以降低PCB中杂散电感引起的噪声,有助于降低信号间串扰、反射和电磁干扰.     

Modeling and simulation of core switching noise for ASICs

This paper presents simulation and analysis of core switching noise for a CMOS ASIC test vehicle. The test vehicle consists of a ceramic ball grid array (CBGA) package on a printed circuit board (PCB). The entire test vehicle has been modeled by accounting for all the plane resonances using the cavity resonator method. The models included both the on-chip and off-chip decoupling capacitors. Using both time domain and frequency domain simulations, the role of plane resonances on power supply noise for fast current edge rates has been discussed. The models have been constructed to amplify certain parts of the test vehicle during simulations     

印制电路板设计与工艺对信号完整性的影响

信号完整性问题是高速数字系统的研究重点,其主要形式有反射、串扰与电磁干扰等。影响信号完整性的物理互连层包括集成电路、芯片封装、印制电路板和系统级连接四个部分,芯片和印制电路板是当前信号完整性研究的主要对象。本文主要阐述了印制电路板设计和工艺对信号完整性的影响。