多值开关级代数在MOS电路形式验证中的应用

本文讨论了ＭＯＳ电路多值开关级代数表达式的三种标准结构，给出了将多值开关级表达式转换成布尔表达式的定理，基于这些理论，提出了ＭＯＳ电路开关级形式验证的一种方法。     

A Multiple-Valued Algebra for Modeling MOS VLSI Circuits at Switch-Level

A multiple-valued algebra for modeling MOS VLSI circuits at switch-level is proposed in this paper,Its structure and properties are studied.This algebra can be used to transform a MOS digital circuit to a swith-level algebraic expression so as to generate the truth table for the circuit and to derive a Boolean expression for it.In the paper,methods to construct a switch-level algebraic expression for a circuit and methods to simplify expressions are given.This algebra provides a new tool for MOS VLSI circuit design and analysis.     

A Survey of Switch-Level Algorithms

The switch-level model provides a logical abstraction from the physical structure of a metal-oxide semiconductor(MOS) circuit to its digital behavior. At the switch level, a circuit is modeled as a network of transistor switches connecting a set of charge storage nodes. Node voltages are represented by discrete logic levels, and electrical behavior is modeled in a highly simplified way. Switch-level algorithms have been applied to such tasks as logic and fault simulation, formal hardware verification, timing analysis, and automatic test program generation. They have been implemented on sequential and parallel computers as well as by hardware simulation accelerators.     

多值开关级代数结点方程组及其求解

多值开关级代数可以在晶体管开关级为MOS电路建模,井已在分析与设计通路晶体管开关网络中取得了很好的效果。本文对多位开关级代数作了进一步研究,取得了若干新结果:(1)提出以(A#B)*G的形式来描述MOS管的双向开关特性;(2)提出以#范式及结点方程组来描述一个复杂的MOS开关网络的特性;(3)提出吸收定理,以简化并求解网络的结点方程组。     

Designing CMOS Circuits for Switch-Level Testability

Conventional testing techniques often fail to be effective for CMOS combinational circuits, since most of their switch-level faults cannot be detected by stuck-at-fault testing. The alternative is to design for testability. The design techniques presented here for fully testable CMOS combinational circuits use a three-pattern test scheme to detect both stuck-open and stuck-on switch-level faults. The circuit is implemented with specially designed gates that have no undetectable stuck-on faults. An inverting buffer is inserted between logic gates, and two FETs are added to each logic gate to make it testable for stuck-on faults.     

CMOS电路开关级测试生成的一种新算法

本文提出了一种新的CMOS电路开关级测试生成算法,该算法以Hayes模型为基础,以开关级代数为工具,充分利用CMOS电路自身的特点,生成CMOS电路的完全测试集,这种算法较之于已有的算法简单而有效,检测CMOS电路的常开型故障需一对测试码,本文给出了一种简单的求一对稳健测试码的方法,基于这种算法,我们开发了一个测试自动生成软件。     

Deviation-tolerant floating gate structures as a way to design an on-chip learning neural networks

 Hardware implementation of artificial neural networks (ANN) based on MOS transistors with floating gate (Neuron MOS or νMOS) is discussed. Choosing analog approach as a weight storage rather than digital improves learning accuracy, minimizes chip area and power dissipation. However, since weight value can be represented by any voltage in the range of supplied voltage (e.g. from 0 to 3.3 V), minimum difference of two values is very small, especially in the case of using neuron with large sum of weights. This implies that ANN using analog hardware approach is weak against V _dd deviation. The purpose of this paper is to investigate main parts of analog ANN circuits (synapse and neuron) that can compensate all kinds of deviation and to develop their design methodologies.     

An Introduction to Switch-Level Modeling

Switch-level modeling is a recently developed design and analysis methodology for MOS VLSI circuits. At the switch level, important features of MOS circuits can be directly modeled using a moderate number of discrete parameters, including switch states, resistance, capacitance, and bidirectional signals. Switch-level models, provide more accurate behavioral and structural information than gate-level logical models, while avoiding the high computational cost associated with analog electrical models.     

多阈值神经元电路设计及在多值逻辑中的应用

分析了多阈值神经元工作原理,并提出设计多阈值神经元电路的方法．首先,用两个MOS晶体管组成电压型突触电路,然后又提出一种基于BiCMOS工艺的判别转换开关电路,这种电路以压控电流作为阈值信号,并实现电压到电流的转换．在此基础上,结合限幅电压开关理论提出多阈值神经元阈值判别函数电路的开关级设计方法．最后,从开关级设计了实现三值逻辑中文字、与、或三种基本运算的多阈值神经元电路,用这三种基本运算的多阈值神经元电路可实现任意三值函数的多阈值神经网络．文章还对设计出的电路用PSPICE进行模拟,测量相关参数．模拟结果表明,该文设计的电路不仅实现了正确的逻辑功能,而且速度较快。     

VLSI电路短路和开路故障模型研究进展

本文概述了近十年来VLSI电路的短路和开路缺陷及其故障建模的研究进展。本文将VLSI电路短路缺陷分为逻辑门内部的短路和逻辑门之间的互连短路两大类,重点介绍了栅氧短路和桥接故障模型。相应地,文中将VLSI电路的开路缺陷分为逻辑门内部的开路和逻辑门之间的互连开路两大类,重点介绍了逻辑门内部的网络断开、浮栅和互连开路的故障模型。文中还讨论了故障模型与测试的关系。分析结果表明,目前已有的短路和开路故障模型还不够完善,特别需要研究故障机制对电路中其它节点动态行为的依赖性和对噪声的敏感性。     

Network recognition of an MOS integrated circuit from the topography of its masks

Technological data and geometric dimensions of mask patterns define the properties of integrated circuits. These parameters cannot, however, be used directly to analyse the circuits. The MASOB computer program can be used for recognizing the topology and parameters of a lumped-parameter network matched to the integrated circuits. The network can then be readily analysed. Silicon gate MOS technology is assumed. The paper presents the principles of the basic algorithms of the MASOB computer program, written in FORTRAN, and an example of application.     

Hazard Algebras

We introduce algebras capable of representing, detecting, identifying, and counting static and dynamic hazard pulses that can occur in the worst case on any wire in a gate circuit. These algebras also permit us to count the worst-case number of signal changes on any wire. This is of interest to logic designers for two reasons: each signal change consumes energy, and unnecessary multiple signal changes slow down the circuit operation. We describe efficient circuit simulation algorithms based on our algebras and illustrate them by several examples. Our method generalizes Eichelberger's ternary simulation and several other algebras designed for hazard detection.     

单相功率因数校正的改进预测控制算法研究

随着数字控制技术的不断发展,在电源变换领域涌现出许多全新的控制策略来弥补模拟控制的不足.文中采用改进的预测控制算法,不仅解决了数字控制系统难于实现高频化的问题,而且消除了输出电压纹波对控制系统性能的影响,使得系统的功率因数得到了进一步改善,采用这种控制策略,还可令系统的输出电压基本不受到负载变化的影响,输出电压的稳定性更好.使用Matlab/simulink仿真软件对整体控制系统进行了数字仿真实验,并取得了比较理想的控制效果.     

Development of a 14.1‐in. UXGA TFT‐LCD using LTPS technology

A 14.1‐in. UXGA low‐temperature poly‐Si TFT‐LCD has been developed using p‐MOS technology. Both the peripheral driving circuits and the pixel switches are implemented using only p‐channel TFTs. The device performance for the driving circuits and the panel design issues, such as crosstalk and flicker, were investigated. The image quality required for the notebook‐PC display has been achieved by optimizing the panel design and by improving the device performance. In addition, the redundant gate driving structure has been developed to minimize the degradation of the panel yield.     

Learning a circuit by injecting values

We propose a new model for exact learning of acyclic circuits using experiments in which chosen values may be assigned to an arbitrary subset of wires internal to the circuit, but only the value of the circuit's single output wire may be observed. We give polynomial time algorithms to learn (1) arbitrary circuits with logarithmic depth and constant fan-in and (2) Boolean circuits of constant depth and unbounded fan-in over AND, OR, and NOT gates. Thus, both AC0 and NC1 circuits are learnable in polynomial time in this model. Negative results show that some restrictions on depth, fan-in and gate types are necessary: exponentially many experiments are required to learn AND/OR circuits of unbounded depth and fan-in; it is NP-hard to learn AND/OR circuits of unbounded depth and fan-in 2; and it is NP-hard to learn circuits of constant depth and unbounded fan-in over AND, OR, and threshold gates, even when the target circuit is known to contain at most one threshold gate and that threshold gate has threshold 2. We also consider the effect of adding an oracle for behavioral equivalence. In this case there are polynomial-time algorithms to learn arbitrary circuits of constant fan-in and unbounded depth and to learn Boolean circuits with arbitrary fan-in and unbounded depth over AND, OR, and NOT gates. A corollary is that these two classes are PAC-learnable if experiments are available. Finally, we consider an extension of the model called the synchronous model. We show that an even more general class of circuits are learnable in this model. In particular, we are able to learn circuits with cycles.     

The efficiency of neuron-MOS transistors in threshold logic

 Using MOS-transistors with floating gate (Neuron MOS or νMOS) for building threshold logic is discussed. Two ways of νMOS threshold logic implimention – static and clocked – are under consideration. Methodology of νMOS circuit design is given. Majority voting gate (MVG) is used as an example of threshold gate with worst conditions for getting a large number of inputs. The possibility of implementing a MVG with a certain number of inputs is the possibility of building a threshold gate with a threshold alterable in real time (from OR to AND-function) with the sum of input weights equal to the number of MVG inputs. The maximum number of threshold gate inputs is estimated depending upon the deviations of the elements dimensions and parameters inside the chip. It is shown that it is difficult to implement a static νMOS MVG with a number of inputs more than 10. For the same conditions, the number of inputs of clocked νMOS MVG is as large as many tens. A clocked νMOS threshold gate with alterable in real-time input weights and threshold is proposed. Delay time and chip area for such a circuits are estimated.     

IMPLEMENTING COMPLEX DOMAINS OF APPLICATION IN AN EXTENDED PROLOG SYSTEM

One way to extend resolution based theorem proving is by means of unification in algebras modelling interesting domains of application. We will discuss in this paper the theoretical and practical aspects of unification in the unitarytheory of Post algebras, which cover among others boolean algebras, algebras formalizing multivalued logic and finite fields. Therefore, a theorem prover using unification in Post algebras is capable of dealing with the design of digital circuits, combinatorics, applications of multivalued logic and mathematics over finite fields.     

Experiences on developing computer vision hardware algorithms using Xilinx system generator

Computer vision is one of the areas where hardware-implemented algorithms perform clearly better than those implemented via software. Digital designers have so far optimized their designs by means of application specific integrated circuits (ASICs) or digital signal processors (DSPs). However, nowadays they are increasingly using field programmable gate arrays (FPGAs), powerful hardware devices combining the main advantages of ASICs and DSPs with the possibility of re-programming, which make them very attractive devices for rapid prototyping. This paper shows how the Xilinx system generator (XSG) environment can be used to develop hardware-based computer vision algorithms from a system level approach, which makes it suitable for developing co-design environments.     

Microfluidic integrated circuits for signal processing using analogous relationship between pneumatic microvalve and MOSFET

In this paper, a new concept and potential demonstration of functional microfluidic integrated circuits using MEMS technology are presented. The fluidic integrated circuits were constructed utilizing analogous relationship between MOSFET and pneumatic microvalve with a diaphragm structure. The signal transmitted through the circuit is the fluidic signal, that is, the pressure or the flow-rate of the fluid. The pneumatic microvalve in this study is expressed by small-signal equivalent model similar to that of a MOSFET. Small signal behavior of microfluidic integrated circuits can be expected using the model, if the parameters in the model are extracted properly from fabricated microvalves. As an example of a fluidic circuit, pressure inverting amplifiers including integrated two microvalves were fabricated and evaluated. As a result, they showed sharp pressure transfer curves similar to MOS inverter circuits. A maximum pressure gain of 32.0 dB was obtained, and it can be used for pressure amplification in analog applications. In addition, they can be used as pressure inverter logic circuits for digital applications. Although the theory and design environment of the new microvalve circuit technology have not been established yet, multifunctional fluidic analog and digital circuits can be realized for special application fields different from electronic integrated circuits.