Gate and drain currents in off-state buried-type p-channel LDDMOSFETs

The buried-type p-channel LDD MOSFETs biased at high positive gate voltage exhibit novel characteristics: (1) the ratio of the drain to gate currents is about 1×10^-3 to 5×10^-3; and (2) the gate and drain currents both are functions of only the gate voltage minus the n-well bias. Such characteristics are addressed based on the formation of the surface n ⁺ inversion layer due to the punchthrough of the buried channel to the underlying shallow p-n junction. The measured gate current is due to the Fowler-Nordheim tunneling of electrons from this inversion layer surface and the holes generated within the high-field oxide constitute the drain current. The n⁺ inversion layer surface potential is found to be equal to the n-well bias plus 0.55 V. As a result, both the oxide field and the gate and drain currents are independent of drain voltage     

Effects of neutral buried p-layer on high-frequency performance ofGaAs MESFETs

Fully ion-implanted n⁺ self-aligned GaAs MESFETs with Au/WSiN refractory metal gates have been fabricated by adopting neutral buried p-layers formed by 50-keV Be-implantation. S-parameter measurements and equivalent circuit fittings are discussed. When the Be dose is increased from 2×10¹² cm^-2 to 4×10¹² cm^-2, the maximum value of the cutoff frequency with a 0.2-μm gate falls off from 108 to 78 GHz. This is because a neutral buried player makes the intrinsic gate-source capacitance increase markedly, while its influence on gate-drain capacitance and gate-source fringing capacitance is negligible. The maximum oscillation frequency recovers, however, due primarily to the drain conductance suppression by the higher-concentration buried p-layer. An equivalent value of over 130 GHz has been obtained for both 0.2-μm-gate GaAs MESFETs     

n+/p+ Gate Bulk FinFETs With Locally Separated Channel Structure for Sub-50-nm DRAM Cell Transistors

We proposed a new p⁺/n⁺ poly-Si gate bulk fin-type field-effect transistor that has two channel fins separated locally by a shallow trench filled with oxide or p⁺ polygate. Key device characteristics were investigated by changing the n⁺ poly-Si gate length La, the material filling the trench, and the width and length of the trench at a given gate length L_g. It was shown that the trench filled with p⁺ poly-Si gate should not be contacted with the source/drain diffusion region to achieve an excellent I_on/I_off (> 1010) that is suitable for sub-50-nm dynamic random access memory cell transistors. Based on the aforementioned device structure, we designed reasonable Ls/Lg and channel fin width W_cfin at given L_g 's of 30, 40, and 50 nm.     

Impact ionization and light emission in AlGaAs/GaAs HEMT's

Impact ionization and light emission phenomena have been studied in AlGaAs/GaAs HEMTs biased at high drain voltages by measuring the gate excess current due to holes generated by impact ionization and by analyzing the energy distribution of the light emitted from devices in the 1.1-3.1 eV energy range. The emitted spectra in this energy range can be divided into three energy regions: (i) around 1.4 eV light emission is dominated by band-to-band recombination between cold electrons and holes in GaAs; (ii) in the energy range from 1.5 to 2.6 eV energy distribution of the emitted photons is approximately Maxwellian; and (iii) beyond 2.6 eV the spectra are markedly distorted due to light absorption in the n⁺ GaAs cap layer. The integrated intensity of photons with energies larger than 1.7 eV is proportional to the product of the drain and gate currents. This suggests recombination of channel electrons with holes generated by impact ionization as the dominant emission mechanism of visible light     

$hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ Channel MOSFETs With Self-Aligned InAs Source/Drain Formed by MEE Regrowth

Abstract-We report Al₂O₃Zln_0.53Ga_0.47As MOSFETs having both self-aligned in situ Mo source/drain ohmic contacts and self-aligned InAs source/drain n⁺ regions formed by MBE regrowth. The device epitaxial dimensions are small, as is required for 22-nm gate length MOSFETs; a 5-nm In_0.53Ga_0.47As channel with an In_0.4sAl_0.52As back confinement layer and the n⁺⁺ source/drain junctions do not extend below the 5-nm channel. A device with 200-nm gate length showed I_D = 0.95 mA/mum current density at V_GS = 4.0 V and g_m = 0.45 mS/mum peak transconductance at V_DS = 2.0 V.     

A novel MESFET fabricated by a simple internal interconnectiontechnique

A new type of internal interconnection of devices has been developed by implanting a buried horizontal n⁺ layer and vertical n⁺ columns inside semi-insulating GaAs. Based on this technique, a novel MESFET with small intrinsic gate-source resistance has been fabricated and tested     

The Characteristics of New n-Type Polycrystalline Silicon Thin-Film Transistors Employing Alternating Magnetic-Field-Enhanced Rapid Thermal Annealing

We fabricated a new top-gate n-type depletion-mode polycrystalline silicon (poly-Si) thin-film transistor (TFT) employing alternating magnetic-field-enhanced rapid thermal annealing. An n⁺ amorphous silicon (n⁺ a-Si) layer was deposited to improve the contact resistance between the active Si and source/drain (S/D) metal. The proposed process was almost compatible with the widely used hydrogenated amorphous silicon (a-Si:H) TFT fabrication process. This new process offers better uniformity when compared to the conventional laser-crystallized poly-Si TFT process, because it involves nonlaser crystallization. The poly-Si TFT exhibited a threshold voltage (V_TH) of -7.99 V at a drain bias of 0.1 V, a field-effect mobility of 7.14 cm²/V ldr s, a subthreshold swing (S) of 0.68 V/dec, and an ON/OFF current ratio of 107. The diffused phosphorous ions (P⁺ ions) in the channel reduced the V_TH and increased the S value.     

Spectral response of an SIT image sensor with an improved structure

A static-induction-transistor (SIT) image sensor with an n⁺ buried drain region is discussed. This region acts as a filter to eliminate the optical information at longer wavelengths. As a result, a spectral response close to that of the human eye is obtained. This result is also proved theoretically     

An ITLDD CMOS process with self-aligned reverse-sequenceLDD/channel implantation

An advanced inverse-T LDD (ITLDD) CMOS process has been developed. This process features self-aligned lightly-doped-drain/channel implantation for improved hot-carrier protection. Selective polysilicon deposition is used to define the thick polysilicon gate regions with a thin polysilicon gate regions overlying the lightly doped n^- and p⁺ regions. Since the thick poly gate regions are defined by nitride sidewall spacers, optical lithography can be used to define sub-half-micrometer gate length MOSFETs. The LDD implants are performed after the n⁺ and p⁺ implants are annealed, resulting in MOSFET's with improved short-channel behavior due to the smaller lateral source/drain diffusion     

A self-aligned retrograde twin-well structure with buried p+-layer

A self-aligned retrograde twin-well structure with a buried p⁺-layer surrounding the n-well is presented. The retrograde twin well and buried p⁺-layer are fabricated by a single lithographic step using high-energy ion implantation. The retrograde n-well is self-aligned to the retrograde p-well regions, and the channel stop processes are eliminated by using tight spatial distributions of retrograde n- and p-wells. This simple process is compatible with both local oxidation of silicon (LOCOS) and trench isolation processes and allows a scalable CMOS structure for very tight n⁺-to-p⁺ spacing. The present CMOS structure provides high latchup immunity at 1.5-μm n⁺-to-p⁺ spacing and good isolation characteristics without additional n- and p-channel stop dopings     

A new p-channel MOSFET with large-tilt-angle implanted punchthroughstopper (LATIPS)

A buried-channel p-MOSFET with a large-tile-angle implanted punchthrough stopper (LATIPS) is described. In this device the n⁺ LATIPS region was successfully realized adjacent to the p⁺ source/drain, even without a sidewall spacer, by taking advantage of the n⁺ large-tilt-angle implant. In spite of the relatively deep p⁺ junction of 0.2-μm depth and the low n-well concentration of 1×10¹⁶ cm^-3, the 0.5-μm LATIPS device (with corresponding channel length of 0.3 μm) achieved high punchthrough resistance, e.g. a low subthreshold swing of 95 mV/decade with a high transconductance of 135 mS/mm     

Disposable polysilicon LDD spacer technology

An advanced 0.5-μm CMOS disposable lightly doped drain (LDD) spacer technology has been developed. This 0.5-μm CMOS technology features surface-channel LDD NMOS and PMOS devices, n⁺/p⁺ poly gates, 125-A-thick gate oxide, and Ti-salicided source/drain/gate regions. Using only two masking steps, the NMOS and PMOS LDD spacers are defined separately to provide deep arsenic n⁺ regions for lower salicided junction leakage, while simultaneously providing shallow phosphorus n^- and boron p^- regions for improved device short-channel effects. Additionally, the process allows independent adjustment of the LDD and salicide spacers to optimize the LDD design while avoiding salicide bridging of source/drain to gate regions. The results indicate extrapolated DC hot-carrier lifetimes in excess of 10 years for a 0.3-μm electrical channel-length NMOS device operated at a power-supply voltage of 3.3 V     

Schottky-clamped NMOS transistors implemented in a conventional0.8-μm CMOS process

An 0.8-μm n-channel MOSFET with a TiSi₂-Si Schottky clamped drain-to-body junction (SCDR) and an n⁺ implanted standard source structure have been fabricated in a conventional 0.8-μm salicide CMOS process without any process modifications. The SCDR should be useful for reducing susceptibility for latch-up in integrated CMOS RF power amplifiers and switches where drain to p-substrate junctions can be forward biased during normal operations. Output I-V characteristics of the devices are the same as those of conventional MOSFETs, while parasitic lateral n⁺-drain/p-substrate/n⁺-source bipolar transistor measurements showed significantly reduced current gains because the Schottky barrier diode which does not inject minority carriers (electrons) to the p-substrate base clamps the n⁺ drain-to-p-substrate guard-ring diode connected in parallel     

Recombination measurement of n-type heavily doped layer in high/lowsilicon junctions

The hole lifetime within a heavily doped n⁺ region has been determined using a measurement technique which evaluates the effective recombination velocity of n-n⁺ interfaces. The recombination model of a high/low junction is reviewed. The experiment is described. The measurement results are presented and discussed. Measurements of n⁺ layers of different types, like substrates, implanted buried layers, and diffused layers, suggest that the minority-carrier lifetime of such regions can be strongly degraded by the device fabrication processes. Results are consistent with the Shockley-Reed-Hall (SRH) lifetime value, which is two orders of magnitude lower than previously published values for bulk material     

Characterization of double pulse-doped channel GaAs MESFETs

The fabrication and characterization of a double pulse-doped (DPD) GaAs MESFET grown by organometallic vapor phase epitaxy (OMVPE) are reported. The electron mobility of a DPD structure with a carrier concentration of 3×10¹⁸/cm³ was 2000 cm²/V-s, which is about 20% higher than that of a pulse-doped (PD) structure. Implementing the DPD structure instead of the conventional PD structure as a GaAs MESFET channel, the drain breakdown voltage, current gain cutoff frequency, and maximum stable gain (MSG) increase. The maximum transconductance of 265 mS/mm at a drain current density of 600 mA/mm, a current gain cutoff frequency of 40 GHz, and an MSG of 11 dB at 18 GHz were obtained for a 0.3 μm n⁺ self-aligned DPD GaAs MESFET     

Gate Workfunction Engineering in Bulk FinFETs for Sub-50-nm DRAM Cell Transistors

We proposed a new bulk FinFET that has a p⁺/n⁺ poly-Si gate consists of p⁺ region near the source and n⁺ region near the drain and analyzed current-voltage characteristics and electric field profiles of 50-nm devices by changing the n⁺ poly-Si gate length (L_s). For given gate length (L_gles50 nm) and fin body width (W_finles30 nm), L_s was designed to satisfy the I _off requirement (i.e., 1 fA) of DRAM cell. Optimum L_s /L_g of 30-nm device was ~0.4 at a W_fin of 10 nm and ~0.2 at a W_fin of 15 nm     

A new MOSFET with large-tilt-angle implanted drain (LATID)structure

The LATID device features the elimination of the sidewall spacer and self-alignment of n^- large tilt angle (LAT) and n⁺ implants to the same gate edge. Even without a spacer and a heavy drive-in, the LATID can achieve both a sufficiently long L_n- and an n⁺ gate overlap. The LATID achieves improved current drive by more than 50% and improved hot-carrier lifetime by more than three orders of magnitude as compared with a conventional lightly doped drain. The LATID technique is most promising for applications to submicrometer ULSI under 5-V operation     

0.3-μm advanced SAINT FET's having asymmetricn+-layers for ultra-high-frequency GaAs MMIC's

Improvements in the microwave performance and noise performance of buried p-layer self-aligned gate (BP-SAINT) FETs are discussed. Specifically, a self-aligned gate electrode and an asymmetric n⁺ -layer structure are investigated. The self-aligned gate electrode reduces parasitic gate capacitances by 0.13 to 0.23 pF/mm compared with a conventional BP-SAINT FET. The asymmetric n⁺-layer structure reduces short-channel effects (drain conductance, threshold voltage shift, etc.) and gate-drain capacitance. A 0.3-μm gate-length FET was realized without an increase of short-channel effects by using an asymmetric n⁺-layer structure (advanced SAINT). Improvement of microwave performance is confirmed in this FET structure     

A device model for the amorphous-silicon staggered-electrodethin-film transistor

A model for the amorphous-silicon (a-Si) staggered-electrode thin-film transistor (TFT) that incorporates gate-voltage dependent mobility for channel current and space-charge-limited current effects for the source and drain contacts is discussed. This model is in excellent agreement with TFT data over a wide range of applied voltages and for various channel lengths. For the devices measured, the TFT current depends more sensitively on effective channel mobility than on space-charge-limited current through the a-Si layer, but the latter is responsible for current crowding at low drain voltage. Because of the two-dimensional current flow under the contacts, their equivalent lumped element model exhibits a different power law behaviour than that for one-dimensional current flow in an n⁺-i-n⁺ structure. It also shows that a peak in the differential conductance curve at low drain voltage is a sensitive indicator of current crowding and implies a superlinear equivalent lumped element in series with the intrinsic TFT     

A self-aligned retrograde twin-well structure with buried p+-layer

The retrograde twin wells and buried p⁺ layer are fabricated by a single lithographic step using high-energy ion implantation. The retrograde n-well is self-aligned to the retrograde p-well regions. This simple process allows a scalable CMOS structure for the very tight n⁺-to-p⁺ spacing. It provides latch-up immunity at the 1.5-μm n⁺-to-p⁺ spacing and good isolation characteristics without additional n- and p-channel stops