Effects of the electrical stress on the conduction characteristics of metal gate/MgO/InP stacks

The degradation dynamics and post-breakdown current–voltage (I–V) characteristics of magnesium oxide (MgO) layers grown on n and p-type indium phosphide (InP) substrates subjected to electrical stress were investigated. We show that the current–time (I–t) characteristics during degradation can be described by a power-law model I(t) = I₀t^−α, where I₀ and α are constants. It is reported that the leakage current associated with the soft breakdown (SBD) failure mode follows the typical voltage dependence I = aV^b, where a and b are constants, for both injection polarities but in a wider voltage range compared with the SiO₂/Si system. It is also shown that the hard breakdown (HBD) current is remarkably high, involving large ON–OFF fluctuations that resemble the phenomenon of resistive switching previously observed in a wide variety of metal oxides.     

Extracting the relative dielectric constant for “high-κ layers” from CV measurements – Errors and error propagation

The paper pursues an investigation of the errors associated with the extraction of the dielectric constant (i.e., κ value) from capacitance–voltage measurements on metal oxide semiconductor capacitors. The existence of a transition layer between the high-κ dielectric and the silicon substrate is a factor that affects – in general – the assessment of the electrical data, as well as the extraction of κ. A methodology which accounts for this transition layer and the errors related to other parameters involved in the κ value extraction is presented; moreover, we apply this methodology to experimental CV results on HfO₂/SiO_x/Si structures produced in different conditions.     

Impact of defects on the high-κ/MG stack: The electrical characterization challenge

The integration of high-κ dielectrics in MOSFET devices is beset by many problems. In this paper a review on the impact of defects in high-κ materials on the MOSFET electrical characteristics is presented. Beside the quality of the bulk of the dielectric itself, the interfaces between the high-κ and the interfacial oxide layer and the gate electrode are of crucial importance. When poly-Si is used as gate electrode, the defects at the poly-Si/high-κ interface control the band alignment as well as the gate depletion. The quality and thickness of the interfacial SiO₂ controls both the carrier mobility in the channel as well as the kinetics of charging and discharging of pre-existing high-κ defects. The quality of the interfacial layer has also important consequences for reliability specifications like negative bias instability and dielectric breakdown.     

Effects of oxygen partial pressure on structural and electrical characteristics of HfAlO high-k gate dielectric grown on strained SiGe by pulsed-laser deposition

Dependence of oxygen partial pressures on structural and electrical characteristics of HfAlO (Hf:Al=1:1) high-k gate dielectric ultra-thin films grown on the compressively strained Si₈₃Ge₁₇ by pulsed-laser deposition were investigated. The microstructure and the interfacial structure of the HfAlO thin films grown under different oxygen partial pressures were studied by transmission electron microscopy, and the their electrical properties were characterized by capacitance–voltage (C−V) and conductance–voltage measurements. Dependence of interfacial layer thickness and C–V characteristics of the HfAlO films on the growth of oxygen pressure was revealed. With an optimized oxygen partial pressure, an HfAlO film with an effective dielectric constant of 16 and a low interface state density of 2.1×10¹⁰ cm⁻² eV⁻¹ was obtained.     

Potential remedies for the VT/Vfb-shift problem of Hf/polysilicon-based gate stacks: a solution-based survey

In this paper, we report on several different approaches that were implemented on both capacitor and scaled planar MOS transistor devices in order to prevent or undo the commonly observed V_T/V_fb-shift and –instability for Hf-based high-κ gate stacks in conjunction with a poly-Si electrode. While the latter issue can eventually be mitigated, the V_T-shift problem jeopardizes initial high-κ integration with poly-Si for the 65 nm and also for the 45 nm node. The different attempts to circumvent this problem include (1) bulk modifications of the high-κ stack/process, (2) the use of various thin capping layers at the poly/high-κ interface and (3) chemical and process modifications of the gate electrode deposition. We have observed that, although considerable improvements have been made in terms of e.g. yield, performance and instability, none of these techniques succeeded in obtaining V_T-values in line with the ITRS device specifications, i.e. avoiding Fermi Level Pinning to occur for poly-Si/Hf(Si)O(N) stacks.     

An investigation of electrical and structural properties of Ni-germanosilicided Schottky diode

Ni-germanosilicided Schottky barrier diode has been fabricated by annealing the deposited Ni film on strained-Si and characterized electrically in the temperature range of 125 K–300 K. The chemical phases and morphology of the germanosilicided films were studied by using scanning electron microscopy (SEM), cross-sectional transmission electron microscopy (TEM) and energy dispersive spectroscopy (EDS). The Schottky barrier height (_b), ideality factor (n) and interface state density (D_it) have been determined from the current–voltage (I–V) and capacitance–voltage (C–V) characteristics. The current–voltage characteristics have also been simulated using SEMICAD device simulator to model the Schottky junction. An interfacial layer and a series resistance were included in the diode model to achieve a better agreement with the experimental data. It has been found that the barrier height values extracted from the I–V and C–V characteristics are different, indicating the existence of an in-homogeneous Schottky interface. Results are also compared with bulk-Si Schottky diode processed in the same run. The variation of electrical properties between the strained- and bulk-Si Schottky diodes has been attributed to the presence of out-diffused Ge at the interface.     

Observation and mechanism explanation of the parasitic charge pumping current

A parasitic charge pumping current (I_PCP) is observed and extracted properly. While charge pumping current after correction (I_COCP) contributes to threshold voltage shift, this transient I_PCP does not contribute and should be extracted from CP current (I_CP). This I_PCP is shown to be unable to be extracted by conventional low–high multi-frequency CP method (LHMF). It could only be extracted effectively enough by a high–high multi-frequency charge pumping (CP) method (HHMF). In HHMF, a high frequency is employed to measure I_PCP; while in LHMF, a low frequency is used to measure the current out of I_COCP. Without eliminating I_PCP, large noise tail in LHMF method distorts the shape of I_COCP curve and even masks maximum I_COCP current (I_CPmax). This is because I_PCP is due to transient charge-trapping and -detrapping. Therefore, I_PCP is frequency dependent and its value can be obtained sufficiently only when frequency is no lower than 1 MHz. Regarding both the value of I_CPmax and the shaping of I_COCP curve, HHMF is more recommended for CMOS devices with SiON and high-κ dielectrics with high transient trap density.     

On the SILC mechanism in MOSFET’s with ultrathin oxides

In this paper, n-channel MOSFET’s with oxides 1.2, 1.5 and 1.8 nm thick are studied. In such devices the trap assisted tunnelling (TAT) current required to fit the gate current vs. gate voltage, I_g(V_g), characteristics is thought to flow through Si–SiO₂ interface traps. After stress, it becomes a stress induced leakage current (SILC) which should allow to obtain interface trap density variations with stress. The TAT mechanism is discussed. Then, the Si–SiO₂ interface trap densities extracted using the SILC and charge pumping (CP) are compared. Much larger trap creation rates are viewed by the SILC with regard to CP, questioning the occurrence of the SILC through interface traps. To answer this question the interaction between SILC and CP measurements is investigated.     

Electrical measurements of voltage stressed Al2O3/GaAs MOSFET

Electrical characteristics of GaAs metal–oxide–semiconductor field effect transistor with atomic layer deposition deposited Al₂O₃ gate dielectric have been investigated. The IV characteristics were studied after various constant voltage stress (CVS) has been applied. A power law dependence of the gate leakage current (I_g) on the gate voltage (V_g) was found to fit the CVS data of the low positive V_g range. The percolation model well explains the degradation of I_g after a high positive V_g stress. A positive threshold voltage (V_th) shift for both +1.5 V and +2 V CVS was observed. Our data indicated that positive mobile charges may be first removed from the Al₂O₃ layer during the initial CVS, while the trapping of electrons by existing traps in the Al₂O₃ layer is responsible for the V_th shift during the subsequent CVS.     

Optical and electrical characterization of hafnium oxide deposited by liquid injection atomic layer deposition

Optical and electrical properties of a set of high-k dielectric HfO₂ films, deposited by liquid injection atomic layer deposition (LI-ALD) and post deposition annealed (PDA) in nitrogen (N₂) ambient at various temperatures (400–600 °C), were investigated. The films were prepared using the cyclopentadienyl of hafnium precursor [Cp₂Hf(CH₃)₂] with water deposited at 340 °C. The spectroscopic ellipsometric (SE) results show that the characteristics of the dielectric functions of these films are strongly affected by annealing temperatures. I–V results show that N₂-based PDA enhances the average energy depth of the shallow trapping defects from Poole–Frenkel conduction fitting. This also correlated with the measured increase in MOS capacitance–voltage hysteresis.     

Precise determination of metal effective work function and fixed oxide charge in MOS capacitors with high-κ dielectric

Effective metal work function, Φ_m,eff, and oxide charge, Q_ox, were determined on MOS capacitors with slanted high-κ dielectric. Φ_m,eff and Q_ox were extracted using flat-band voltage shift versus equivalent oxide thickness data, both deduced from the capacitance–voltage measurements. Slanted HfSiO_x dielectric (initial thickness was 9 nm) was prepared by gradual etching in HF-based solution. As a metal electrode, thin Ru-films were deposited by MOCVD-derived technique—Atomic Vapor Deposition^® on the slanted HfSiO_x as well as SiO₂ dielectrics. The Φ_m,eff of Ru was found to be 4.74 and 4.81 eV for Ru/HfSiO_x and Ru/SiO₂ gate stacks, respectively. Ultraviolet photoelectron spectroscopy yields the work function of 4.62 eV in agreement with the capacitance–voltage data. We also studied the I–V characteristics of the Ru/HfSiO_x/Si MOS capacitors. The barrier height was found to be constant within the HfSiO_x bulk.     

Electrical characterization and analysis techniques for the high-κ era

Various conventional and novel electrical characterization techniques have been combined with careful, robust analysis to properly evaluate high-κ gate dielectric stack structures. These measurement methodologies and analysis techniques have enhanced the ability to separate pre-existing defects that serve as fast transient charging and discharging sites from defects generated with stress. In addition, the differentiation of electrically active bulk high-κ traps, silicon substrate interface traps, and interfacial layer traps has been effectively demonstrated.     

New electronic effects in double injection diodes with one deep level

Double injection diodes made of high resistivity semiconductors compensated with deep levels show a negative differential resistance region in the stationary I - V characteristic. At lower temperatures the injection level of free carriers can be altered within the prebreakdown region without changing the space charge situation. Therefore is valid for several orders of magnitude of the current. Furthermore, the switching of the diode from the “off state” (prebreakdown region) to the “on-state” (high injection or semiconductor regime) can be delayed by applying a corresponding voltage V >V_BD, the breakdown voltage. An exponential dependence of the delay time t_D on the applied voltage is found. The lower limit of t_D is determined by the free carrier lifetime, an upper limit does practically not exist if the temperature is low enough.     

Monte carlo study of mobility in Si devices with -based oxides

HfO₂-based high-κ dielectrics are among the most likely candidates to replace SiO₂ and the currently favoured oxinitride in the next generation of MOSFETs. High-κ materials allow the use of a thicker gate dielectric, maintaining the gate capacitance with reduced gate leakage. However, they lead to a fundamental mobility degradation due to the coupling of carriers to surface soft (low-energy) optical phonons. Comparing the vertical field dependence of the mobility for HfO₂ and SiO₂, the severe degradation in mobility in the presence of high-κ becomes evident. The introduction of a SiO₂ interfacial layer between the channel and the HfO₂ mitigates this degradation, by increasing the effective distance between the carriers and the SO phonons, thus decreasing the interaction strength, this does though lead to an increase in the equivalent oxide thickness (EOT) of the gate dielectric. The material of choice for the first commercial introduction of high-κ gate stacks is Hafnium Silicate (Si_xHf_1-xO₂). This alloy stands up better to the processing challenges and as a result suffers less from dielectric fluctuations. We show that as the fraction of Hf increases within the alloy, the inversion layer mobility is shown to decrease due to the corresponding decrease in the energy of the surface optical phonons and increase in the dielectric constant of the oxide.     

Lifetime estimation of analog circuits from the electrical characteristics of stressed MOSFETs

In this work, the impact of dielectric degradation in the MOSFET electrical characteristics after different levels of Fowler-Nordheim (FN) stress has been studied. A decrease in I_SAT and an increase of V_T have been observed. The interface trap density has been extracted from the sub-threshold slope of I_D–V_GS curves. The results show a direct relation between the generated interfacial traps and the observed changes in saturation current and threshold voltage. The wear out effects in the devices have been extrapolated to operation voltages, pointing out that the transistors can fulfill the reliability criteria, even when working in analog applications.     

Correlating gate sinking and electrical performance of pseudomorphic high electron mobility transistors

Ti interdiffusion from the Ti/Pt/Au gate into the AlGaAs Schottky barrier layer (SBL) of 0.25-μm GaAs Pseudomorphic High Electron Mobility Transistors (PHEMTs) has been studied using the accelerated life testing technique. Based on measurements and modeling, analytical expressions for quantitative correlation between the positive pinch-off voltage (V_P) shift as well as the saturation drain current (I_Dsat) decrease and the physical damage occurring during gate sinking has been developed. It is suggested that the main cause for device failure is the growth of the TiAs phase leading to the decrease in the SBL thickness. Additionally, it is suggested that V_P may be used as a better indicator for device degradation than I_Dsat since it is linearly proportional to the degrading physical characteristic – the Schottky barrier layer thickness.     

Low and high temperature device reliability investigations of buried p-channel MOSFETs of a 0.17 μm technology

The hot carrier degradation of buried p-channel MOSFETs of a 0.17 μm technology is assessed in the temperature range between −40°C and 125°C. Within this temperature range, the degradation of the electrical parameter is investigated for different drain voltages and channel lengths (0.2–0.3 μm) in the gate voltage range between V_GS=0 V and V_GS=V_DS. The analysis of the experimental results is presented and the physical processes responsible for the observed degradation at different stress conditions are discussed by reviewing previous works. Based on hot carrier modelling and lifetime extrapolation to operating conditions the stressing voltage conditions are analysed. For the experimentally investigated temperature range the worst case stress condition is identified at low temperatures for gate voltage at the maximum of the gate current (I_Gmax). In the case of V_GS corresponding to I_Gmax two activation energies are determined for low and high temperatures. For temperatures above 125°C the worst case bias condition changes from V_GS=V_GS@I_Gmax to V_GS=V_DS.     

Flat band voltage control on low Vt metal-gate/high-κ CMOSFETs with small EOT (Invited Paper)

The unwanted high threshold voltage (V_t) is the major challenge for metal-gate/high-κ CMOS especially at small equivalent-oxide-thickness (EOT). We have investigated the high V_t issue that is due to flat-band voltage (V_fb) roll-off at smaller EOT. A mechanism of charged oxygen vacancies formed by interface reaction was proposed to explain the V_fb roll-off effect. This interface reaction can be decreased by inserting a thin interfacial SiON and using novel low temperature process. The self-aligned and gate-first metal-gate/high-κ CMOSFETs using these methods have achieved low V_t and good control of V_fb roll-off at small 0.6–1.2 nm EOT.     

Ballistic electron emission microscopy studies of the temperature dependence of Schottky barrier height distribution in CoSi2/n-Si(1 0 0) diodes formed by solid phase reaction

Ballistic electron emission microscopy (BEEM) and ballistic electron emission spectroscopy have been performed on polycrystalline and epitaxial CoSi₂/n-Si(1 0 0) contacts at temperatures ranging from −144°C to −20°C. The ultra-thin CoSi₂ films (10 nm) were fabricated by solid state reaction of a single layer of Co (3 nm) or a multilayer of Ti (1 nm)/Co (3 nm)/amorphous-Si(1 nm)/Ti (1 nm) with a Si substrate, respectively. The spatial distribution of barrier height over the contact area obeys a Gaussian function at each temperature. The mean barrier height increases almost linearly with decreasing temperature with a coefficient of −0.23±0.02 meV/K for polycrystalline CoSi₂/Si diodes and −0.13±0.03 meV/K for epitaxial diodes. This is approximately equal to one or one-half of the temperature coefficient of the indirect energy gap in Si, respectively. It suggests that the Fermi level is pinned to different band positions of Si. The width of the Gaussian distribution is about 30–40 meV, without clear dependence on the temperature. The results obtained from conventional current–voltage and capacitance–voltage (I–V/C–V) measurements are compared to BEEM results.     

Electrical characterization of the hafnium oxide prepared by direct sputtering of Hf in oxygen with rapid thermal annealing

Electrical characterization of the hafnium oxide (HfO₂) gate dielectric films prepared by Hf sputtering in oxygen was conducted. By measuring the current–voltage (I–V) characteristics at temperature ranging from 300 to 500 K, several abnormalities in the I–V characteristics are recorded. For temperatures below 400 K, the current–voltage characteristics in high field region can be plotted with the Fowler–Nordheim law but a stronger temperature dependence was observed. Large flatband voltage shifts in the Al/HfO₂/Si capacitor were observed. The capacitance–voltage characteristics and flatband shifts are found to depend strongly on the post-deposition annealing temperature and duration. To study the reliability against high electric field, constant voltage stressing on the samples was conducted. We found that the trap energy levels are shallow and the oxide traps can be readily filled and detrapped at a low bias voltage.