Enhanced organic ferroelectric field effect transistor characteristics with strained poly(vinylidene fluoride-trifluoroethylene) dielectric

Poly(vinylidene fluoride-trifluoroethylene) (70–30 mol%) was used as the functional dielectric layer in organic ferroelectric field effect transistors (FeFET) for non-volatile memory applications. Thin P(VDF-TrFE) film samples spin-coated on metallized plastic substrates were stretch-annealed to attain a topographically flat-grain structure and greatly reduce the surface roughness and current leakage of semi-crystalline copolymer film, while enhancing the preferred β-phase of the ferroelectric films. Resultant ferroelectric properties (P_R = |10| μC/cm², E_C = |50| MV/m) for samples simultaneously stretched (50–70% strain) and heated below the Curie transition (70 ^oC) were comparable to those resulting from high temperature annealing (>140 ^oC). The observed enhancements by heating and stretching were studied by vibration spectroscopy and showed mutual complementary effects of both processes. Organic FeFET fabricated by thermal evaporating pentacene on the smooth P(VDF-TrFE) films showed substantial improvement of semiconductor grain growth and enhanced electrical characteristics with promising non-volatile memory functionality.     

Hybrid dual gate ferroelectric memory for multilevel information storage

Here, we report hybrid organic/inorganic ferroelectric memory with multilevel information storage using transparent p-type SnO semiconductor and ferroelectric P(VDF-TrFE) polymer. The dual gate devices include a top ferroelectric field-effect transistor (FeFET) and a bottom thin-film transistor (TFT). The devices are all fabricated at low temperatures (∼200 °C), and demonstrate excellent performance with high hole mobility of 2.7 cm² V⁻¹ s⁻¹, large memory window of ∼18 V, and a low sub-threshold swing ∼−4 V dec⁻¹. The channel conductance of the bottom-TFT and the top-FeFET can be controlled independently by the bottom and top gates, respectively. The results demonstrate multilevel nonvolatile information storage using ferroelectric memory devices with good retention characteristics.     

High current conduction with high mobility by non-radiative charge recombination interfaces in organic semiconductor devices

We report a unique non-radiative p-n-p junction structure to provide high current conduction with high mobility in organic semiconductor devices. The current conduction was improved by increasing p-n junctions made with intrinsic p-type hole transport layer and n-type electron transport layer. The excellent hole mobility of 5.3 × 10^?1 cm²/V s in this p-n-p device configuration is measured by the space charge limited current method with an electric field of 0.3 MV/cm. Enhanced current conduction of 248% at 4.0 V was observed in fluorescent blue organic light-emitting diodes with introduction of non-radiative p-n-p-n-p junction interfaces. Thereupon, the power efficiency at 1000 cd/m² was improved by 22% and the driving voltage also was reduced by 17%, compared to that of no interface device. Such high current conduction with high mobility is attributed to the carrier recombination at p-n-p interfaces through coulombic interaction. This non-radiative p-n-p junction structure suggested in this report can be very useful for many practical organic semiconductor device applications.     

Border traps and bias-temperature instabilities in MOS devices

An overview of the effects of border traps on device performance and reliability is presented for Si, Ge, SiGe, InGaAs, SiC, GaN, and carbon-based MOS devices that are subjected to bias-temperature stress, with or without exposure to ionizing radiation. Effective border-trap densities and/or energy distributions are estimated using capacitance-voltage hysteresis, low-frequency noise, charge pumping, and other electrical techniques that vary the time scale over which charge exchange between the semiconductor channel and near-interfacial dielectric. Oxygen vacancies and hydrogen impurity complexes are common border traps in a wide variety of systems subjected to bias-temperature stress. Charge trapping and emission tend to dominate observed bias-temperature instabilities for as-processed devices at higher oxide electric fields (> 4–6 MV/cm), and for irradiated devices. Hydrogen diffusion and reactions become relatively more significant in as-processed devices at lower electric fields (< 4–6 MV/cm).     

Topography engineering of ferroelectric crystalline copolymer film

Effects of surface roughness as well as crystallinity onto functionalities of crystalline copolymer films were studied using a dipping method to inject the crystalline grains into voids among crystalline nano-rods. Differently from a widely-used fabrication method such as spin-coating of solution, we achieved a smooth surface and high crystallinity in ferroelectric P(VDF-TrFE) films, simultaneously. Varying dipping temperature and time, remnant polarization and relative dielectric constant values increased by 20% and 75% with a decrease of surface roughness from 20 nm to 7 nm in root mean square value, respectively. The ferroelectric stabilities of P(VDF-TrFE) film capacitors were found to be strongly dependent on the crystallinity.     

Ferroelectric random access memory based on one-transistor–one-capacitor structure for flexible electronics

We have demonstrated a low temperature process for a ferroelectric non-volatile random access memory cell based on a one-transistor–one-capacitor (1T1C) structure for application in flexible electronics. The n-channel thin film transistors (TFTs) and ferroelectric capacitors (FeCaps) are fabricated using cadmium sulfide (CdS) as the semiconductor and poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] copolymer as the ferroelectric material, respectively. The maximum processing temperature for the TFTs is 100 °C and 120 °C for the FeCaps. The TFT shows excellent access control of the FeCap in the 1T1C memory cell, and the stored polarization signals are undisturbed when the TFT is off. The fabricated 1T1C memory cell was also evaluated in a FRAM circuit. The memory window on the bit line was demonstrated as 2.3 V, based on the 1T1C memory cell with a TFT having dimensions of 80 μm/5 μm (W/L) and a FeCap with an area of 0.2 × 10^?3 cm² using a bit line capacitor of 1 nF pre-charged at 17.2 V. The 1T1C memory cell is fabricated using photolithographic processes, allowing the integration with other circuit components for flexible electronics systems.     

Strain sensitivity of gate leakage in strained-SOI nMOSFETs: A benefit for the performance trade-off and a novel way to extract the strain-induced band offset

The impact of biaxial stress on gate leakage is investigated on fully-depleted silicon-on-insulator (FD-SOI) nMOS transistors, integrating either a standard gate stack or an advanced high-κ/metal gate stack. It is demonstrated that strained devices exhibit significantly reduced leakage currents (up to ?90% at E_ox = 11 MV/cm for σ_tensile = 2.5 GPa). This specific effect is used to extract the conduction band offset ΔEc induced by strain and is shown to be accurate enough to monitor stress in MOSFETs. This new technique is much less sensitive to gate oxide defects than the method based on the threshold voltage shift ΔV_T. This accurate experimental extraction allowed us to pick out realistic values for the deformation potentials in silicon (Ξ_u = 8.5 eV and Ξ_d = ?5.2 eV), among the published values.     

Low-voltage,high speed inkjet-printed flexible complementary polymer electronic circuits

We report the development of high-performance inkjet-printed organic field-effect transistors (OFETs) and complementary circuits using high-k polymer dielectric blends comprising poly(vinylidenefluoride-trifluoroethylene) (P(VDF-TrFE)) and poly(methyl methacrylate) (PMMA) for high-speed and low-voltage operation. Inkjet-printed p-type polymer semiconductors containing alkyl-substituted thienylenevinylene (TV) and dodecylthiophene (PC12TV12T) and n-type P(NDI2OD-T2) OFETs showed high field-effect mobilities of 0.1–0.4 cm² V^?1 s^?1 and low threshold voltages down to 5 V. These OFET properties were modified by changing the blend ratio of P(VDF-TrFE) and PMMA. The optimum blend – a 7:3 wt% mixture of P(VDF-TrFE) and PMMA – was successfully used to realize high-performance complementary inverters and ring oscillators (ROs). The complementary ROs operated at a supplied bias (V_DD) of 5 V and showed an oscillation frequency (f_osc) as high as ～80 kHz at V_DD = 30 V. Furthermore, the f_osc of the complementary ROs was significantly affected by a variety of fundamental parameters such as the electron and hole mobilities, channel width and length, capacitance of the gate dielectrics, V_DD, and the overlap capacitance in the circuit configuration.     

Perylrene-based n-type field-effect transistors prepared by the neutral cluster beam deposition method

We present the first application of the neutral cluster beam deposition (NCBD) method to prepare n-type organic thin-film transistors with a top-contact structure based on N,N′-ditridecylperylene-3,4,9,10-tetracarboxylic diimide (P13). Systematic analysis was carried out to examine the effects of surface passivation and thermal post-treatment on the morphology and crystallinity of P13 active layers and device performance, together with operational stability as a function of time. The high room-temperature field-effect mobility of 0.58 cm²/Vs for the thermally post-treated devices was obtained under ambient conditions. The comparative study of the transport mechanisms responsible for conduction of the electron carriers over a temperature range of 10–300 K indicated that surface modification and thermal post-treatment decrease total trap density and activation energy for carrier transport by reducing structural disorder.     

D–A copolymer with high ambipolar mobilities based on dithienothiophene and diketopyrrolopyrrole for polymer solar cells and organic field-effect transistors

Donor–acceptor (D–A) type conjugated polymers have been developed to absorb longer wavelength light in polymer solar cells (PSCs) and to achieve a high charge carrier mobility in organic field-effect transistors (OFETs). PDTDP, containing dithienothiophene (DTT) as the electron donor and diketopyrrolopyrrole (DPP) as the electron acceptor, was synthesized by stille polycondensation in order to achieve the advantages of D–A type conjugated polymers. The polymer showed optical band gaps of 1.44 and 1.42 eV in solution and in film, respectively, and a HOMO level of 5.09 eV. PDTDP and PC₇₁BM blends with 1,8-diiodooctane (DIO) exhibited improved performance in PSCs with a power conversion efficiency (PCE) of 4.45% under AM 1.5G irradiation. By investigating transmission electron microscopy (TEM), atomic force microscopy (AFM), and the light intensity dependence of J_SC and V_OC, we conclude that DIO acts as a processing additive that helps to form a nanoscale phase separation between donor and acceptor, resulting in an enhancement of μ_h and μ_e, which affects the J_SC, EQE, and PCE of PSCs. The charge carrier mobilities of PDTDP in OFETs were also investigated at various annealing temperatures and the polymer exhibited the highest hole and electron mobilities of 2.53 cm² V⁻¹ s⁻¹ at 250 °C and 0.36 cm² V⁻¹ s⁻¹ at 310 °C, respectively. XRD and AFM results demonstrated that the thermal annealing temperature had a critical effect on the changes in the crystallinity and morphology of the polymer. The low-voltage device was fabricated using high-k dielectric, P(VDF-TrFE) and P(VDF-TrFE-CTFE), and the carrier mobility of PDTDP was reached 0.1 cm² V⁻¹ s⁻¹ at V_d = −5 V. PDTDP complementary inverters were fabricated, and the high ambipolar characteristics of the polymer resulted in an output voltage gain of more than 25.     

Extremely low driving voltage electrophosphorescent green organic light-emitting diodes based on a host material with small singlet–triplet exchange energy without p- or n-doping layer

In order to achieve low driving voltage, electrophosphorescent green organic light-emitting diodes (OLEDs) based on a host material with small energy gap between the lowest excited singlet state and the lowest excited triplet state (ΔE_ST) have been fabricated. 2-biphenyl-4,6-bis(12-phenylindolo[2,3-a] carbazole-11-yl)- 1,3,5-triazine (PIC–TRZ) with ΔE_ST of only 0.11 eV has been found to be bipolar and used as the host for green OLEDs based on tris(2-phenylpyridinato) iridium(III) (Ir(ppy)₃). A very low onset voltage of 2.19 V is achieved in devices without p- or n-doping. Maximum current and power efficiencies are 68 cd/A and 60 lm/W, respectively, and no significant roll-off of current efficiency (58 cd/A at 1000 cd/m² and 62 cd/A at 10,000 cd/m²) have been observed. The small roll-off is due to the improved charge balance and the wide charge recombination zone in the emissive layer.     

Energy band alignment and interface states in AlGaN/4H–SiC vertical heterojunction diodes

The effects of Al_xGa_1−xN aluminum fraction x and SiC surface pre-treatment on AlGaN/4H–SiC heterojunction interfaces are experimentally investigated. From capacitance vs. voltage measurements, the conduction band offsets are found to be ΔE_C ≈ 0.30 for x ≈ 0.3 and ΔE_C ≈ 0.56 for x ≈ 0.5. Forward bias ideality factors are reasonable at 3.3 for Al_0.3Ga_0.7N diodes, but >9 for Al_0.5Ga_0.5N diodes, suggesting a higher level of interface charge related to the higher aluminum fraction. Reverse bias leakage is acceptably low, with breakdown occurring at V_A > 200 V reverse bias for all tested devices. The effect of 1500 °C hydrogen etching of the SiC substrate prior to Al_xGa_1−xN growth is also investigated, and found to have little effect for x = 0.3 but a beneficial effect for x = 0.5.     

Relationship between the ionization and oxidation potentials of molecular organic semiconductors

A relationship between the energy of the highest occupied molecular orbital (HOMO) and the oxidation potential of molecular organic semiconductors is presented. Approximating molecules as dipoles consisting of a positively charged ion core surrounded by an electron cloud, the HOMO energy (E_HOMO) is calculated as that required to separate these opposite charges in a neutral organic thin film. Furthermore, an analysis of image charge forces on spherical molecules positioned near a conductive plane formed by the electrode in an electrochemical cell is shown to explain the observed linear relationship between E_HOMO and the oxidation potential. The E_HOMO’s of a number of organic semiconductors commonly employed in thin film electronic devices were determined by ultraviolet photoemission spectroscopy, and compared to the relative oxidation potential (VCV) measured using pulsed cyclic voltammetry, leading to the relationship E_HOMO = −(1.4 ± 0.1) × (qV_CV) − (4.6 ± 0.08) eV, consistent with theoretical predictions.     

Characterization of scaled MANOS nonvolatile semiconductor memory (NVSM) devices

We have modeled and characterized scaled Metal–Al₂O₃–Nitride–Oxide–Silicon (MANOS) nonvolatile semiconductor memory (NVSM) devices. The MANOS NVSM transistors are fabricated with a high-K (K_A = 9) blocking insulator of ALD deposited Al₂O₃ (8 nm), a LPCVD silicon nitride film (8 nm) for charge-storage, and a thermally grown tunneling oxide (2.2 nm). A low voltage program (+8 V, 30 μs) and erase (?8 V, 100 ms) provides an initial memory window of 2.7 V and a 1.4 V window at 10 years for an extracted nitride trap density of 6 × 10¹⁸ traps/cm³ eV. The devices show excellent endurance with no memory window degradation to 10⁶ write/erase cycles. We have developed a pulse response model of write/erase operations for SONOS-type NVSMs. In this model, we consider the major charge transport mechanisms are band-to-band tunneling and/or trap-assisted tunneling. Electron injection from the inversion layer is treated as the dominant carrier injection for the write operation, while hole injection from the substrate and electron injection from the gate electrode are employed in the erase operation. Meanwhile, electron back tunneling is needed to explain the erase slope of the MANOS devices at low erase voltage operation. Using a numerical method, the pulse response of the threshold voltages is simulated in good agreement with experimental data. In addition, we apply this model to advanced commercial TANOS devices.     

Effects of combined NO and forming gas annealing on interfacial properties and oxide reliability of 4H-SiC MOS structures

The effects of NO and forming gas post oxidation annealing treatments on the interfacial properties and reliability of thermal oxides grown on n-type 4H-SiC (0001) Si face have been investigated in this study. The results show that forming gas annealing (FGA) treatment has limited effect on interface trap density (D_it) while it results in an improvement of the insulating properties of thermal oxide with uniform high FN barrier height (2.56 eV), high field-to-breakdown (10.71 MV/cm) and charge-to-breakdown (0.078 C/cm²). On the other hand, NO annealing causes a drastic reduction in D_it in the entire energy level, but in the case of reliability, it is not so effective as FGA, with lower barrier height (2.52 eV), field-to-breakdown (10.08 MV/cm), charge-to-breakdown (0.025 C/cm²) and worse uniformity of oxide. The combined NO&FGA treatment was also studied. It leads to a significant reduction in interface trap density further, especially in deep energy level (E_C-E_T ≥ 0.4 eV). As for reliability, it brings about uniform barrier height (2.69 eV), field-to-breakdown (10.15 MV/cm) and charge-to-breakdown (0.024 C/cm²). Taking interfacial properties and reliability into account, combined NO&FGA treatment is a promising POA technique for fabrication of high-quality SiC MOS devices.     

Effect of trap states on the electrical doping of organic semiconductors

We demonstrate that direct charge transfer (CT) from trap states of host molecules to the p-dopant molecules raises the doping effect of organic semiconductors (OS). Electrons of the trap states in 4,4′-N,N′-dicarbazolyl-biphenyl (CBP) (E_HOMO = 6.1 eV) are directly transferred to the p-dopant, 2,2′-(perfluoronaphthalene-2,6-diylidene) dimalononitrile (F6-TCNNQ) (ELUMO = 5.4 eV). This doping process enhances the conductivity of doped OS by different ways from the ordinary doping mechanism of generating free hole carriers and filling trap states of doped OS. Trap density and trap energy are analysed by impedance spectroscopy and it is shown that the direct charge transfer from deep trap states of host to dopants enhances the hole mobility of doped OS and the I–V characteristics of hole only devices.     

Investigation of deep level defects in copper irradiated bipolar junction transistor

Commercial bipolar junction transistor (2N 2219A, npn) irradiated with 150 MeV Cu¹¹⁺-ions with fluence of the order 10¹² ions cm^?2, is studied for radiation induced gain degradation and deep level defects. I–V measurements are made to study the gain degradation as a function of ion fluence. The properties such as activation energy, trap concentration and capture cross-section of deep levels are studied by deep level transient spectroscopy (DLTS). Minority carrier trap levels with energies ranging from E_C ? 0.164 eV to E_C ? 0.695 eV are observed in the base–collector junction of the transistor. Majority carrier trap levels are also observed with energies ranging from E_V + 0.203 eV to E_V + 0.526 eV. The irradiated transistor is subjected to isothermal and isochronal annealing. The defects are seen to anneal above 350 °C. The defects generated in the base region of the transistor by displacement damage appear to be responsible for transistor gain degradation.     

Inversion charge modeling in n-type and p-type Double-Gate MOSFETs including quantum effects: The role of crystallographic orientation

We have developed an advanced inversion charge model for both n-type and p-type symmetrical Double-Gate MOSFETs where quantum mechanical effects (QMEs) have been included. By doing so, the role of different crystallographic orientations was successfully taken into account. Self-consistent Poisson and Schrödinger simulators were used to check the accuracy of the model presented. As a starting point, a classical inversion charge centroid model was considered. Afterwards, an inversion charge model was developed including QMEs by means of a corrected oxide capacitance. The validity of the model was checked for the three common wafer orientations (1 0 0), (1 1 0) and (1 1 1) and for devices with different silicon layer (t_Si) and oxide (t_ox) thicknesses. As it will be shown, the model reproduces correctly the simulation data both in the subthreshold and in the strong inversion operation regime.     

Increase in hole mobility in poly (3-hexylthiophene-2,5-diyl) films annealed under electric field during the solvent drying step

Higher electrical charge carrier mobility in polymer semiconductor films is important to build electronic and opto-electronic devices with improved performance. Application of electric field of the order of 2000 V cm⁻¹ during the solvent drying step for the formation of poly (3-hexyl thiophene-2,5-diyl) (P3HT) film is shown to significantly increase the hole carrier mobility. The reasons for increase in mobility by this novel technique are investigated in this paper. The X-ray diffraction measurements confirm the increase in crystallinity of the films for electric-field annealed samples, while the analysis of the data shows increase in the size of the ‘crystallites’ in those films. The current density–voltage data corresponding to the space charge limited currents at various low temperatures for hole-only devices with P3HT film when fitted to the empirical model for electric-field annealed samples, show an increase in zero field mobility (μ₀) and correspondingly a decrease in activation energy (E_a) and the field dependence pre-factor (γ). The data fitted to the Gaussian disorder model also shows a decrease in the energetic disorder (σ) in the polymer films due to electric-field annealing – indicative of increased ordering of molecules in those films. The analysis confirms the improvement of ordering of the polymer in the film formed due to application of electric field during the solvent drying step of the film formation – a simple processing technique which may be implemented to fabricate higher mobility polymer films for building improved organic electronic devices.     

Positive bias temperature instabilities on sub-nanometer EOT FinFETs

PBTI degradation on FinFETs with HfO₂/TiN gate stack (EOT < 1 nm) is studied. Thinner TiN layer decreases interfacial oxide thickness, and reduces PBTI lifetime. This behavior is consistent with the results in planar devices. Corner rounding effect on PBTI is also analyzed. Finally, charge pumping measurements on devices with several fin widths devices apparently show a higher density of defects in the top-wall high-κ oxide than in the sidewall of the fin. This could explain more severe PBTI degradation.