High-speed low-cost read-only memory

A high-speed read-only memory is described in which the stored program may be changed easily at low cost. An access time of less than 100 ns has been achieved in an experimental 8192-bit version of the store.     

Laser coding of bipolar read-only memories

Laser beam coding of high-speed bipolar silicon integrated circuit memories is described. Coding is accomplished by the selective vaporization of Ti-Pt links connecting the contact pads of each memory cell to Ti-Pt-Au bit lines. Vaporized link resistances of >10/SUP 9/ /spl Omega/ can be consistently obtained, with no melting of the adjacent gold patterns. Parameters that have been found to be relevant to the link vaporization process are described including the number of laser pulses per link, beam spot size, thickness of the gold metallization, and pulse energy. The laser coding process is especially useful for applications where relatively small numbers of chips of each of many codes are needed, since only one photolithographic mask set is required.     

A novel high-performance bipolar monolithic memory cell

A novel memory cell is described that is used in several IBM processors. It is fast, insensitive to disturbance by reading and half-selects, and delivers a large sense signal.     

Electrically erasable buried-gate nonvolatile read-only memory

An electrically erasable buried (floating) gate memory is described. The memory is programmed by electron injection by junction avalanche. An internal voltage multiplication scheme using varactor bootstrapping is used which makes nearly 40 V available at the memory cell for programming, yet requires input voltages no higher than 25 V. Erasure takes place by modified Poole-Frenkel conduction in a Si3N4film of 700-Å thickness which overlays the buried gate. Standard silicon gate p-MOS processing is used with only minor modifications. Memory retention is excellent and is extrapolated to many years even at 150°C. Above 298 K, the time required for the charge to decay to one-half its initial value is given bylog t_{1/2} = frac{5254}{T}-frac{771}{T}√V_{E}(s)whereT(K) is the temperature and VEis the erase voltage. The endurance of the buried-gate memory is approximately 10 K write-erase cycles and is limited by electron trapping in the insulator. A fully decoded 1024-bit memory chip was designed and fabricated.     

Electrically erasable and reprogrammable read-only memory using the n-channel SIMOS one-transistor cell

The stacked-gate injection MOS transistor (SIMOS) uses a control gate stacked on the floating gate for selection of the cell during reading, programming, and erasure. Programming is achieved by the injection of hot electrons from the channel into the floating gate, resulting in a large upward shift in threshold voltage. In both states, operation is in the enhancement mode. Electrical erasure can be performed by injection of hot holes from an avalanche breakdown at the source-substrate junction and by Fowler-Nordheim electron injection from the floating gate to the source. Because the floating gate can be charged positively during the erasure, part of the channel is not covered by the floating gate, and in this way the enhancement mode of the SIMOS transistor after erasure is guaranteed. In a matrix array, the memory cell consists of the SIMOS transistor only. Decoders, read amplifiers, etc., can be integrated on the same substrate. Erasure can be performed as a block, or word-by-word. Different disturb effects on memory cells during programming and erasure are discussed. The cell area of the SIMOS memory is 850 µm². The photograph of a fully decoded 8192-bit SIMOS memory chip is presented.     

A fully decoded 2048-bit electrically programmable FAMOS read-only memory

A floating-gate avalanche-injection m.o.s. (FAMOS) charge-storage device is used as the basic nonvolatile memory element. The memory is organized as 256 words of 8 bits, it is fully TTL compatible, and can be operated in both the static or dynamic mode. The memory array was successfully fabricated with silicon gate m.o.s. technology yielding functional devices with access times of 800 ns in the static mode and 500 ns in the dynamic mode of operation. The memory chip is assembled in a 24-lead dual-in-line package.     

Small-size low-power bipolar memory cell

A d.c.-stable random-access memory cell employing n-p-n and p-n-p transistors has been designed in a concurrent circuit-layout approach. Test chips with 2/spl times/3 arrays have been processed in a standard bipolar technology. Due to the merging of devices, the area required for a cell is only 14 mil/SUP 2/. The cells have been operated at an extremely low d.c. standby power of less than 0.1 /spl mu/W/cell. In spite of this low standby power, an array access time of 10 ns has been measured on a simulated 512-bit array in a pulsed power mode.     

An 18K bipolar dynamic random access memory

A 2K/spl times/9 bipolar dynamic random access memory (RAM) experimental chip is described with a 75 ns and 300 ns access and cycle time, respectively. The design is based on a two device cell of 800 /spl mu/m/SUP 2/ size. All chip input and output signals are TTL compatible.     

Low-voltage single supply CMOS electrically erasable read-only memory

A low-voltage single supply CMOS electrically erasable read-only memory (CMOS-EEROM) is described. It combines long-term charge retention and the possibility of being read, written, and erased from a single power supply. Negative write and erase voltages are generated on-chip by voltage multipliers. It is shown that writing by avalanche injection and erasing by Fowler-Nordheim emission, are compatible with the low power output associated with these multipliers. In order to reduce the programming voltages below 40 V, injection oxide thickness is locally reduced by one additional photolithographic step compared to conventional silicon-gate CMOS technology. The influence of this oxide thickness and of polysilicon doping on write and erase characteristics, endurance, and charge retention are analyzed.     

Atmos—An electrically reprogrammable read-only memory device

An adjustable threshold MOS (Atmos) transistor is described that can be used as an electrically reprogrammable read-only memory by changing the charge content of a floating polysilicon gate. This floating gate is charged negatively (write) by means of a nonavalanche mechanism and charged positively (erase) by the avalanche breakdown of source or drain junction and subsequent hole injection into the oxide. The write time is between 10 and 100 ms, the erase time on the order of 1 s. The charge retention of the floating gate is about 90 percent after storage for 1000 h at 125°C.     

A high-speed low-power 4096 x 1 bit bipolar RAM

Describes a 4096-word by 1-bit TTL static bipolar RAM with a typical address access time of 25 ns and power dissipation of 350 mW. Emphasis is given to circuit techniques which made the high performance possible. These techniques are: variable impedance cell (VIC) with low standby current capable of fast switching of digit lines, cell margin increasing circuitry which increases the operating margin of the cell with low standby current, sharing of only one pair of read current sources by 64 pairs of digit lines, and Darlington word drivers causing fast switching of word lines. The process and device structure are mentioned briefly.     

Injection-coupled memory: A high-density static bipolar memory

The design of a new static bipolar memory comparable with dynamic FET storages in density, but superior in performance and power dissipation is discussed. The concept of direct minority carrier injection is utilized for both the cell current supply and the coupling to the read/write lines. This has led to an extremely high degree of device integration resulting in a cell size of 3.1 mil/SUP 2/ using a standard buried layer process with 5-/spl mu/ line dimensions and single layer metallization. Investigations on exploratory chips containing small arrays have fully verified the feasibility. The cells have been operated at an extremely small d.c. standby power of below 100 nW. For a 4K b chip of about 160/spl times/150 mil/SUP 2/, an access time around 50 ns can be projected from the measurements simulating a 64/spl times/64 bit array. An extrapolation of the memory cell layout with oxide isolation and self-aligned N/SUP +/ contacts has resulted in a 1.1-mil/SUP 2/ cell with 5-/spl mu/ line dimensions.     

A 400 ps bipolar 18 bit RALU using advanced PSA

Describes a bipolar 18 bit register arithmetic logic unit (RALU) with 1300-gate complexity using an advanced bipolar process named Advanced PSA (APSA). The high-performance of the Advanced PSA transistor has made it possible to achieve a 400 ps delay time with 2.5 mW for a basic low level CML (LCML) circuit. The read-modify-write cycle time is 7 ns in an 18-bit ALU operation. Furthermore, with four RALU chips, a 72-bit ALU can be set up to operate at 100 MHz owing to the improved logic implementation. A 132 pin gang-lead bonding is employed for this LSI.     

互易式只读光存储器

本文介绍了一种用计算机产生的特殊空间滤波器——互易式只读光存储器.文中简述了基本原理、存在的问题和改进的办法,最后给出了计算机模拟结果.     

A vertically integrated dynamic RAM-cell: Buried bit line memory cell with floating transfer layer

A charge injection device has been realized in which charge can be injected on to an MOS-capacitor from a buried layer via an isolated transfer layer. The cell is positioned vertically between word and bit line. LOCOS (local oxidation) is used to isolate the cells and (deep) ion implantation to realize the buried bit line and transfer layer. This isolation prevents carriers from diffusing to neighbouring cells and hence preserves stored information. The device physics has been analysed using simulation programs and bipolar modelling. It is shown that this device can be used as a dynamic RAM-cell of extreme simplicity and potentially small cell size compared to conventional DRAM cells.     

A static random-access memory with normally-off-type Schottky barrier FET's

A large-scale integrated memory with lower power consumption and high operating speed has been developed and evaluated. A fully decoded 256-b static random-access memory chip was fabricated by using the Enhancement-type Schottky Barrier gate FET's, having a threshold voltage of 0.1 V, obtained by ion-implantation. The memory chip was successfully operated with an access time of less than 150 ns, and with active power consumption of 15 mW/chip. A single power supply of -1.3 V and current mode logic input levels are additional features of the memory chip.     

A new dynamic random access memory cell using a bipolar MOS composite structure

A new dynamic random access memory (RAM) cell which incoperates an n-p-n bipolar junction transistor with an n-channel MOSFET in a composite structure, is proposed and investigated. In this novel cell called the BIMOS cell, the collector-base junction serves as a buried storage capacitor whereas the n-MOSFET as a transfer gate. The fabrication technology is simple and compatible with that of single-polysilicon CMOS IC's and a minimum cell size of 14.875F²with a minimum feature sizeFis realizable. The write, read, and standby operations of the cell are analyzed and simulated. An experimental cell is fabricated and characterized. Dynamic test is successfully performed. The investigation on the cell performance is also made. It has shown that large storage capacitance to bit-line capacitance ratio as well as fairly good packing density, soft-error immunity and leakage characteristics are expected. Furthermore, as compared to the conventional 1-transistor cell the new cell can be scaled down with less processing troubles and better performance improvements. Simple process and good scaled-down properties offer great potential for the proposed new cell to be used in the design of larger dynamic MOS RAM's.     

A high-conductivity insulated gate bipolar transistor with Schottky hole barrier contact

This letter proposes a high-conductivity insulated gate bipolar transistor (HC-IGBT) with Schottky contact formed on the p-base, which forms a hole barrier at the p-base side to enhance the conductivity modulation effect. TCAD simulation shows that the HC-IGBT provides a current density increase by 53% and turn-off losses decrease by 27% when compared to a conventional field-stop IGBT (FS-IGBT). Hence, the proposed IGBT exhibits superior electrical performance for high-efficiency power electronic systems.     

Inkjet-printed resistors with a wide resistance range for printed read-only memory applications

Inkjet-printed resistors with resistance values varying over five orders of magnitude were demonstrated on a flexible substrate. The resistivity of printed lines of poly(3,4-ethylenedioxythiophene):poly(styrene sulfonate) (PEDOT:PSS) was altered by using different ink formulations and by employing an over-print technique, while the length of the printed resistor line remained unchanged. This technique was then applied to fabricate a printed read-only memory device that consisted of an array of resistors. The concept of printing reliable, visually identical resistors with controlled resistance values provides an important building block for low cost, printed electronic circuit applications.