Extraction and evolution of Fowler-Nordheim tunneling parameters of thin gate oxides under EEPROM-like dynamic degradation

A new method is presented for the extraction of the Fowler-Nordheim (FN) tunneling parameters of thin gate oxides from experimental current-voltage characteristics of Metal-Oxide-Semiconductor (MOS) capacitors. In this technique, the classical low temperature FN current model is considered but an improved numerical procedure has been implemented for the calculation of the oxide electric field — gate voltage relationship. It is shown that this iterative method leads to an excellent fit of experimental data with theoretical curves for both p-type and n-type substrates, even in the case of high doping levels. The procedure allows the determination of both FN tunneling parameters and potential barrier heights at silicon and polysilicon interfaces with a systematic estimation of the statistical fitting errors on each parameter. It is applied here to the study of the variations of the FN tunneling parameters of thin oxides submitted to EEPROM-like dynamic degradation.     

Modeling of direct tunneling current through interfacial oxide and high-K gate stacks

In this paper, we present a computationally efficient model to calculate the direct tunneling current from an inverted p-type (1 0 0) Si substrate through interfacial SiO₂ and high-K gate stacks. This model consists of quantum mechanical calculations for the inversion layer charge density and a modified WKB approximation for the transmission probability. The modeled direct tunneling currents agree well with a self-consistent model and experimental data. For the same effective oxide thickness (EOT) of 2 nm, the direct tunneling current of a HfO₂ high-K dielectric (6.4 nm, K_f=25) overlaying a 1 nm thermal oxide is reduced by four orders of magnitude compared with a pure SiO₂ film at low gate voltages. The effects of interfacial oxide thickness, dielectric constant and barrier height on the direct tunneling current have also been studied as a function of gate voltages.     

Tunneling into interface states as reliability monitor for ultrathin oxides

This paper reports experimental data and simulations of low-voltage tunneling in ultrathin oxide MOS devices. When the substrate is very heavily doped, a thermionic barrier is present that opposes the direct tunneling of gate electrons when the applied gate voltage is between 0 V and the flatband voltage. In such conditions, we show that the measured gate current cannot be explained by direct tunneling, but features an additional, dominant component. The temperature dependence of this extra component indicates that it is due to gate electrons tunneling into the anode interface states. By comparing measurements and simulations, it is possible to exploit this extra current to estimate the interface state density within the silicon band gap. In addition, it is shown that this tunneling current component is very sensitive to electrical stress and allows a clear detection of oxide wear out even for stress at very low field. Therefore, it can be adopted as monitor of oxide degradation in ultrathin oxides where the traditional stress induced leakage current due to bulk-oxide traps is not detectable.     

Accurate determination of ultrathin gate oxide thickness andeffective polysilicon doping of CMOS devices

We present an efficient and accurate method to characterize the physical thickness of ultrathin gate oxides (down to 25 Å) and the effective polysilicon doping of advanced CMOS devices. The method is based on the model for Fowler-Nordheim (F-N) tunneling current across the gate oxide with correction in gate voltage to account for the polysilicon-gate depletion. By fitting the model to measured data, both the gate oxide thickness and the effective poly doping are unambiguously determined. Unlike the traditional capacitance-voltage (C-V) technique that overestimates thin-oxide thickness and requires large area capacitor, this approach results in true physical thickness and the measurement can be performed on a standard sub-half micron transistor. The method is suitable for oxide thickness monitoring in manufacturing environments     

Impact of tunnel currents and channel resistance on thecharacterization of channel inversion layer charge and polysilicon-gatedepletion of sub-20-Å gate oxide MOSFETs

This paper discusses the limitations on MOSFET test structures used in extracting the polysilicon gate doping from capacitance-voltage (C-V) analysis in strong inversion, especially for ultrathin gate oxides. It is shown that for sub-20-Å oxide MOS devices, transistors with channel lengths less than about 10 μm will be needed to avoid an extrinsic capacitance roll-off in strong inversion. The upper limit of the channel length has been estimated using a new simple transmission-line-model of the terminal capacitance, which accounts for the nonnegligible gate tunneling current and finite channel resistance     

An Analytical Gate Tunneling Current Model for MOSFETs Having Ultrathin Gate Oxides

In this paper, we present a completely analytical model for the gate tunneling current, which can be used to get a first-order estimate of this parameter in present-generation MOSFETs, having ultrathin gate oxides and high substrate doping concentrations. The model has been developed from first principles, and it does not use any empirical fitting and/or correction parameters. It takes into account the quantization of the electron energy levels within the inversion layer of a MOSFET, which behaves similar to a potential well. Several interesting simplifications regarding this well structure have been made, and all these assumptions have been rigorously justified, both based on physical arguments as well as through numerical quantifications. An extremely interesting and important outcome of this procedure is a nonzero value of the wavefunction at the semiconductor-insulator interface, which is physically justified, however, contrary to what other existing literatures in this area assume. This procedure also led to a closed-form analytical expression for the inversion layer thickness. The interface wavefunction was used, in association with the tunneling probability through the gate oxide, and the carriers in transit model in the gate metal, to find the resultant gate tunneling current density as a function of the applied gate-to-body voltage. The results obtained from our simple and completely analytical model were compared with the experimental results reported in the literature, and the match is found to be excellent for varying oxide thicknesses and substrate doping concentrations, which justifies the authenticity of the model developed in this work here.     

MOS C-V characterization of ultrathin gate oxide thickness (1.3-1.8nm)

An equivalent circuit approach to MOS capacitance-voltage (C-V) modeling of ultrathin gate oxides (1.3-1.8 nm) is proposed. Capacitance simulation including polysilicon depletion is based on quantum mechanical (QM) corrections implemented in a two-dimensional (2-D) device simulator; tunneling current is calculated using a one-dimensional (1-D) Green's function solver. The sharp decrease in capacitance observed for gate oxides below 2.0 nm in both accumulation and inversion is modeled using distributed voltage-controlled RC networks. The imaginary components of small-signal input admittance obtained from AC network analysis agree well with measured capacitance     

Applicability limits of the two-frequency capacitance measurementtechnique for the thickness extraction of ultrathin gate oxide

Reliable techniques for extracting the gate dielectric layer thickness from capacitance-voltage (C-V) characteristics are essential for manufacturing process quality control. Continued reduction of the dielectric layer thickness has brought about a need for new measurement procedures which can account for the direct tunneling currents through the gate insulator. We present a guideline for performing two-frequency C-V analysis of sub-2 nm gate oxides and show that it is possible to extract the dielectric layer thickness with an error of less than 4%. We show that in order to achieve this level of accuracy, it is necessary to choose the measurement frequencies and the test device size so that the dissipation remains below 1.1 at least at one of the two measurement frequencies     

Modeling and estimation of edge direct tunneling current for nanoscale metal gate (Hf/AlNx) symmetric double gate MOSFET

This paper present, the modeling and estimation of edge direct tunneling current of metal gate (Hf/AlN_x) symmetric double gate MOSFET with an intrinsic silicon channel. To model this leakage current, we use the surface potential model obtained from 2D analytical potential model for double gate MOSFET. The surface potential model is used to evaluate the electric field across the insulator layer hence edge direct tunneling current. Further, we have modeled and estimated the edge direct tunneling leakage current for high-k dielectric. In this paper, from our analysis, it is found that dual metal gate (Hf/AlN_x) material offer the optimum leakage currents and improve the performance of the device. This feature of the device can be utilized in low power and high performance circuits and systems.     

A study of the effects of tunneling currents and reliability of sub-2 nm gate oxides on scaled n-MOSFETs

This work examined various components of direct gate tunneling currents and analyzed reliability of ultrathin gate oxides (1.4–2 nm) in scaled n-metal-oxide-semiconductor field effective transistor (MOSFETs). Direct gate tunneling current components were studied both experimentally and theoretically. In addition to gate tunneling currents, oxide reliability was investigated as well. Constant voltage stressing was applied to the gate oxides. The oxide breakdown behaviors were observed and their effects on device performance were studied. The ultrathin oxides in scaled n-MOSFETs used in this study showed distinct breakdown behavior and strong location dependence. No “soft” breakdown was seen for 1.5 nm oxide with small area, implying the importance of using small and more realistic MOS devices for ultrathin oxide reliability study instead of using large area devices. Higher frequency of oxide breakdowns in the source/drain extension to the gate overlap region was then observed in the channel region. Possible explanations to the observed breakdown behaviors were proposed based on the quantum mechanical effects and point-contact model for electron conduction in the oxide during the breakdown. It was concluded that the source/drain extension to the gate overlap regions have strong effects on the device performance in terms of both gate tunneling currents and oxide reliability.     

Statistical simulation of leakage currents in MOS and flash memory devices with a new multiphonon trap-assisted tunneling model

A new physics-based model of leakage current suitable for MOS and Flash memory gate oxide is presented in this paper. This model, which assumes the multiphonon trap-assisted tunneling as conduction mechanism, calculates the total leakage current summing the contributions of the percolation paths formed by one or more aligned traps. Spatial positions and energetic levels of traps have been randomly generated within the oxide by a random number generator which has been integrated into the model. Using this model, statistical simulations of leakage currents measured from both MOS and Flash EEPROM memory tunnel oxides have been carried out. In this way, experimental leakage current distributions can be directly reproduced, thus opening a wide range of useful applications in MOS and Flash EEPROM memory reliability prediction.     

Edge hole direct tunneling leakage in ultrathin gate oxidep-channel MOSFETs

This paper examines the edge direct tunneling (EDT) of holes from p⁺ polysilicon to underlying p-type drain extensions in off-state p-channel MOSFETs having ultrathin gate oxides that are 1.2 nm-2.2 nm thick. It is for the first time found that for thinner oxides, hole EDT is more pronounced than both conventional gate-induced drain leakage (GIDL) and gate-to-channel tunneling. As a result, the induced gate and drain leakage is more accurately measured per unit gate width. Terminal currents versus input voltage are measured from a CMOS inverter with gate oxide thickness T_OX=1.23 nm, exhibiting the impact of EDT in two standby modes. For the first time, a physical model is derived for the oxide field E_OX at the gate edge by accounting for the heavy and light holes' subbands in the quantized accumulation polysilicon surface. This model relates E_OX to the gate-to-drain voltage, oxide thickness, and doping concentration of the drain extension. Once E_OX is known, an existing direct tunneling (DT) model consistently reproduces EDT current-voltage (I-V), and the tunneling path size extracted falls adequately within the gate-to-drain overlap region. The ultimate oxide thickness limit due to hole EDT is projected     

Gate current and oxide reliability in p+ poly MOScapacitors with poly-Si and poly-Ge0.3Si0.7 gatematerial

Fowler-Nordheim (FN) tunnel current and oxide reliability of PRiLOS capacitors with a p⁺ polycrystalline silicon (poly-Si) and polycrystalline germanium-silicon (poly-Ge_0.3Si_0.7 ) gate on 5.6-nm thick gate oxides have been compared. It is shown that the FN current depends on the gate material and the bias polarity. The tunneling barrier heights, φ_B, have been determined from FN-plots. The larger barrier height for negative bias, compared to positive bias, suggests that electron injection takes place from the valence band of the gate. This barrier height for the GeSi gate is 0.4 eV lower than for the Si gate due to the higher valence band edge position. Charge-to-breakdown (Q_bd) measurements show improved oxide reliability of the GeSi gate on of PMOS capacitors with 5.6 nm thick gate oxide. We confirm that workfunction engineering in deep submicron MOS technologies using poly-GeSi gates is possible without limiting effects of the gate currents and oxide reliability     

A comparative study of gate direct tunneling and drain leakagecurrents in n-MOSFET's with sub-2 nm gate oxides

This work examines different components of leakage current in scaled n-MOSFET's with ultrathin gate oxides (1.4-2.0 nm). Both gate direct tunneling and drain leakage currents are studied by theoretical modeling and experiments, and their effects on the drain current are investigated and compared. It concludes that the source and drain extension to the gate overlap regions have strong effects on device performance in terms of gate tunneling and off-state drain currents     

Investigation of the Correlation Between Temperature and Enhancement of Electron Tunneling Current Through $hbox{HfO}_{bf 2}$ Gate Stacks

A model is established to describe the temperature dependence of the electron tunneling current through HfO₂ gate stacks based on analyzing the coupling between the longitudinal and transverse components of electron thermal energy caused by the difference of the effective electron mass between the HfO₂ gate stacks and silicon. By analyzing the three-dimensional Schrodinger equation for a MOS structure with HfO₂ gate stacks, a reduction in the barrier height is resulted from the large effective electron mass mismatch between the gate oxide and the gate (substrate). The calculated electron tunneling currents agree well with the experimental data over a wide temperature range. This coupling model can explain the temperature dependence of the electron tunneling current through HfO₂ gate stacks very well. The numerical results also demonstrate that the temperature dependence of the electron tunneling current strongly depends on the effective electron mass of HfO₂. This temperature sensitivity of the electron tunneling current can be proposed as a novel method to determine the effective electron mass of the gate oxide.     

Drain-avalanche and hole-trapping induced gate leakage inthin-oxide MOS devices

Leakage current components due to band-to-band tunneling and avalanche breakdown in thin-oxide (90-160 Å) gated-diode structures are discussed. Experimental results show that while the band-to-band tunneling current is not sensitive to channel doping concentration, the avalanche current is sensitive to channel doping concentration in the range of 10¹⁶ to 10¹⁷ cm^-3. For oxides thicker than 110 Å, the gate current is found to be dominated by hot-hole injection and for oxides thinner than 110 Å the gate current is dominated by Fowler-Nordheim electron tunneling. After hot-hole injection, the gate oxide exhibits significant low-level leakage, which is explained by the barrier-lowering effect caused by the trapped holes in the oxide     

Electrical characterization of ultrathin oxides of silicon grown by N2O plasma assisted oxidation

The ultrathin (2.0–3.5 nm) oxides of silicon have gained renewed importance in view of ultra large scale integration (ULSI) of the silicon devices. In the present investigation, the ultrathin oxides are grown on (100) oriented p-type single side polished silicon using N₂0 plasma assisted oxidation in a PECVD reactor at 200°C. The oxide growth as a function of oxidation time is studied. The oxidation growth conforms to the reaction limited regime. In order to understand the electrical quality of Si/ultrathin SiO₂ interface, Al-thin SiO₂-Si tunnel capacitors are fabricated and their capacitance-voltage (C-V) and current-voltage (I–V) characteristics are studied. The effect of annealing on these oxides (termed as “post oxidation annealing”) has also been studied. The C-V characteristics of tunnel capacitors with “as grown” oxide showed a frequency dependence, possibly due to the presence of large fast interface state density. These fast interface states are observed to decrease with increasing oxidation time. The tunnel capacitors that the oxides undergone “post oxidation annealing” (POA) at 350°C in N₂ ambient for 20 minutes have shown practically no frequency dependence of the C-V characteristics; this observation along with the data on I-V characteristics confirms that POA reduces the interface state density considerably. The forward and reverse currents of POA capacitors are observed to decrease considerably indicating the reduction in the trap assisted tunneling transport process across the tunnel insulator.     

Thin tunnel oxide grown on silicon substrate pretreated by CF4 plasma

High tunneling current and large resistance against stress were the main issue of tunnel oxide for scaling down the operation voltage of EEPROMs. In this letter, thin-tunnel oxides grown on a CF₄ pretreated silicon substrate were prepared and investigated for the first time. The fabricated oxide has about three orders of tunneling current higher than that of control one; furthermore, the stress induced anomalous and low electric field leakage currents were greatly suppressed. The improvement could be contributed to F-incorporation in oxide. This type of oxide is suitable for fabricating low-voltage EEPROMs and less process complexity was added     

Tunneling Effective Mass of Electrons in Lightly N-Doped $hbox{SiO}_{x} hbox{N}_{y}$ Gate Insulators

In this paper, we study the dependence of the tunneling effective mass of electrons on gate dielectric nitrogen concentration and thickness in MOSFETs with lightly doped silicon oxynitride $(hbox{SiO}_{x}hbox{N}_{y})$ gates. The direct tunneling current is modeled by applying a SchrÖdinger–Poisson solver with one-side-open boundary condition. The dependences of the effective mass on nitrogen concentration and dielectric thickness are extracted by fitting the computation results for the gate leakage current to the experimental data that we measured for samples with different thicknesses and nitrogen concentrations. Nitrogen concentration and thickness of samples are determined using X-ray photoemission spectroscopy. The obtained results show a strong dependence of the effective mass on the sample thicknesses and nitrogen concentration. The electron effective mass is found to increase as the thickness decreases, and the higher nitrogen concentration causes a reduction in effective mass.      

Reduced electron mobility due to nitrogen implant prior to the gateoxide growth

We have found that nitrogen incorporation in the gate-oxide, by implantation into the Si, degrades the low field inversion mobility. Although submicron transistors fabricated using nitrogen implantation have been reported to show higher drive currents compared with “pure” oxides, we have measured about 20% degradation in large area transistors for a 2e14 cm^-2 nitrogen implant. These measurements were done using nMOS transistors with thin gate-oxides (<4 nm). Thickness determination was done by simulation fit to capacitance-voltage (C-V) measurements by including quantization and tunneling effects. Furthermore, we observed that the decrease in the mobility has an increased sensitivity to the channel doping concentration