纳电子器件

随着电子器件的小型化 ,器件的尺寸已经到了介观尺寸 ,传统的器件日益接近其物理机理的禁区 ,一些新的介观器件随之出现。本文根据介观系统的新特点 ,介绍了几种典型的纳电子器件 ,并简单地介绍了量子干涉器件、共振隧穿器件、单电荷转移器件 ,量子点元胞自动机的工作机理和各自所体现的介观效应     

纳电子器件

随着电子器件的小型化,器件的尺寸已经到了介观尺寸,传统的器件日益接近其物理机理的禁区,一些新的介观器件随之出现.本文根据介观系统的新特点,介绍了几种典型的纳电子器件,并简单地介绍了量子干涉器件、共振隧穿器件、单电荷转移器件,量子点元胞自动机的工作机理和各自所体现的介观效应.     

纳电子器件

随着电子器件的小型化，器件的尺寸已经到了介观尺寸，传统的器件日益接近其物理机理的禁区，一些新的介观器件随之出现。本文根据介观系统的新特点，介绍了几种典型的纳电子器件，并简单地介绍了量子干涉器件、共振隧穿器件、单电荷转移器件，量子点元胞自动机的工作机理和各自所体现的介观效应。     

半导体量子电子和光电子器件分析

文章主要阐述了半导体异质结构电子的量子特性,对半导体量子电子和光电子器件进行科学的分析,其中,对电子波输运状况、库仑阻塞效应等作出了一定分析基础上,介绍了几种较为新颖的、具有代表性的量子电子器件和量子光电子器件的物理模型,并对半导体量子电子和光电子器件运行的基本原理作出了科学的理解。     

微光电子集成芯片及其应用

一、引言目前,半导体科学技术在低维结构物理、微腔物理、光学量子器件及电学量子器件、超高速电子器件与集成电路、微光电子集成芯片、微光机电系统(MOEMS)器件等方面的研究与发展,其特征尺寸都已进入深亚微米、十纳米以至纳米量级。所研究对象的低维化和结构的微细化不仅是其性能改善的要求,更重要的是将可能导致一系列物理效应的发现     

量子器件与量子信息技术

从信息社会的发展分析提出了量子器件及量子信息技术产生和发展的必然性,介绍了谐振隧穿器件、单电子器件、电子波导晶体管等纳米电子器件及其特点,对量子激光器和量子信息技术及其性能作了简要介绍,并给出了应用前景.     

半导体量子点的器件应用

半导体量子点的生长和性质已成为当今研究的热点。以Ｓ－Ｋ生长模式已成功地生长了无缺陷的半导体量子点。由于其较强的量子效应,量子点结构的光电器件和电子器件有望比量子阱结构的器件具有更好的性能。介绍了量子点在光电器件中的一些应用,包括单电子晶体管、激光器和红外探测器等。     

半导体量子器件

概述了半导体量子微结构中的量子效应，并介绍了谐振隧道器件。评述了新的量子微结构，如单电子隧道器件，电子波衍射晶体管和量子线量子箱激光器的开发，还了量子微结构的尺寸要求和研究课题。     

探索量子微结构的新阶段

概述了超薄层量子结构中的量子效应及其器件之后，以立体量子微结构为重点，介绍了其中的电子的波动行为，例如普适的电导波动、弹性散射和声子散射的抑制等，并简要介绍了量子线和量子箱激光器以及电子波衍射晶体管，还讨论了对量子微结构的尺寸要求。     

名词木语释义——量子器件

<正> 量子器件是利用量子效应来构筑电子器件的器件总称。因为只有纳米微小结构下才能出现显著的量子效应,所以量子电子器件属于纳器件。当常规器件的特征尺寸达到与半导体中的电子平均波长(约几纳米)相当时,由于量子隧道效应,使MOSFET作为开关的功能失效,从而使其不能再成为信息处理芯片的基本单元,而量子器件则不受此限制。当前提出的各种     

Thermal instability of low voltage power-MOSFETs

This paper analyzes an anomalous failure mechanism detected on last generation low voltage power metal oxide semiconductor (MOS) devices at low drain current. Such a behavior, apparently due to a kind of second breakdown phenomenon, has been scarcely considered in literature, as well as in manufacturer data sheets, although extensive experimental tests show that it is a common feature of modern low voltage metal oxide semiconductor held effect transistor (MOSFET) devices. The paper starts by analyzing some failures, systematically observed on low voltage power MOSFET devices, inside the theoretical forward biased safe operating area. Such failures are then related to an unexpected thermal instability of the considered devices. Experimental tests have shown that in the considered devices the temperature coefficient is positive for a very wide drain current range, also including the maximum value. Such a feature causes hot spot phenomena in the devices, as confirmed by microscope inspection of the failed devices. Finally, it is theoretically demonstrated that the thermal instability is a side effect of the progressive die size and process scaling down. As a result, latest power MOSFETs, albeit more efficient and compact, are less robust than older devices at low drain currents, thus requiring specific circuit design techniques     

0.6μm MOS器件稳态总剂量损伤效应研究

合作制备了体硅0.6μm工艺直栅和环栅不同设计结构的MOS器件,开展了稳态高剂量率电离辐射总剂量效应试验。通过对实验数据进行分析,研究当器件特征尺寸达到亚微米、深亚微米时,不同设计结构、不同辐照偏置条件对实验结果的影响。分析了器件的短沟效应、窄沟效应、DIBL增强效应,为器件设计加固提供了有益的试验数据。     

A unified simulation of Schottky and ohmic contacts

The Schottky contact is an important consideration in the development of semiconductor devices. This paper shows that a practical Schottky contact model is available for a unified device simulation of Schottky and ohmic contacts. The present model includes the thermionic emission at the metal/semiconductor interface and the spatially distributed tunneling calculated at each semiconductor around the interface. Simulation results of rectifying characteristics of Schottky barrier diodes (SBD's) and resistances under high impurity concentration conditions are reasonable, compared with measurements. As examples of application to actual devices, the influence of the contact resistance on salicided MOSFETs with source/drain extension and the immunity of Schottky barrier tunnel transistors (SBTTs) from the short-channel effect (SCE) are demonstrated     

半导体器件的发展与固态纳米电子器件研究现状

简要回顾了半导体电子器件由真空电子管到固体晶体管,直至纳米电子器件的发展历程。分别比较了不同的半导体电子器件的材料、理论和所采用的制备技术。在此基础上综述了当前较热门的纳米电子学和固态纳米电子器件,并由纳米器件的分类简单介绍了当前固态纳米电子器件的三个部分,即量子点、谐振隧穿器件和单电子晶体管。最后对半导体器件的发展提出了展望。     

Super Junction LDMOS Transistors - Implementing super junction LDMOS transistors to overcome substrate depletion effects

The super junction (SJ) concept (Coe et al.) applied to power semiconductor devices is attractive due to its potential for reducing on-resistance at a given breakdown voltage. Discrete SJ vertical power devices have recently become available commercially. However, lateral SJ devices have not materialized for several years partly due to the fact that the lateral SJ structure, implemented on silicon substrates, suffers from substrate-assisted depletion effects which reduce the breakdown voltage. This article discusses the various device structures that have been proposed to eliminate the substrate-assisted depletion effects in SJ-lateral double diffused MOS LDMOS transistors (SJ-LDMOSTs). The concept of the SJ device and vertical and lateral SJ structure was summarized. The substrate-assisted depletion effects are described in detail. The alternative implementations proposed to suppress the substrate effects were then discussed. And the experimental implementation results are summarized and discussed to identify the most likely option for the implementation of lateral SJ-LDMOSTs     

SOI技术特点及晶圆材料的制备

随着微电子技术发展,要使器件水平进一步提高,除了进一步缩小芯片的特征尺寸外,采用新型材料也是有效的方法。文章介绍了SOI解决方案,阐述了SOI器件与体硅器件相比具有的明显优点。文章重点介绍了SOI晶圆材料的制备方法,目前广泛使用且较有发展前途的SOI的材料制备方法主要有注氧隔离的SIMOX（Seperation by Impolanted Oxygen）方法、硅片键合和反面腐蚀的BESOI（Bonding-Etchback SOI）方法、将键合与注入相结合的Smart Cut SOI方法。指出了SOI很有可能成为今后高性能和高可靠集成电路材料的主流。     

Fatigue phenomena of FTMIS memory transistors

Two operation modes of long endurance and their fatigue properties are described for a nonvolatile charge storage memory device which employs a floating silicon gate tunnel injection MIS (FTMIS) structure. The device is composed of an n-channel metal gate field effect transistor with a floating gate over tunnelable (20-35 Å) SiO2. The floating gate consists of highly resistive polycrystalline Si grains. Gate oxidation isolates each poly-Si grain, resulting in a structure of islands. This improves retention characteristics. The primary feature of these devices is that no fatigue phenomena are observed for 2 × 10¹²cycles continuous write-erase operation in the conventional operation mode. In addition, it is possible both to write and erase in the other operation mode with only positive pulses to the gate electrode. Furthermore, stored data is retained more than one year without any external power supply. Therefore the device is an excellent candidate for nonvolatile RAM applications as a semiconductor memory device.     

Steady-state characteristics of two terminal inversion-controlled switches

The important fabrication procedures and the direct current-voltage characteristics of metal/conducting “insulator”/semiconductor junction diodes are described. These devices generally have two impedance states. The high impedance state is associated with a steady-state deep depletion of the semi-conductor surface which permits the device to absorb a high voltage. The low-impedance state is associated with a partial inversion of the semiconductor surface which greatly increases the electric field across the insulator, even though only a low voltage exists across the device. The generality of this phenomenon is emphasized by citing results from a wide variety of combinations of insulator materials and semiconductor structures. Uniformity of conductor through the insulator and ruggedness of the device are discussed in detail. The device's I–V characteristics can either be independent or quite sensitive to ambient temperature. The temperature sensitivity is explained by the effects of temperature on those mechanisms which control the formation of inversion layers.     

半导体量子器件

概述了半导体量子微结构中的量子效应，并介绍了谐振隧道器件，评述了新的量子微结构，如单电子隧道器件，电子波衍射晶体管和量子线量子箱激光器的开发，还讨论了量子微结构的尺寸要求和研究课题。     

Analysis and modeling of floating-gate EEPROM cells

Floating-gate MOS devices using thin tunnel oxide are becoming an acceptable standard in electrically erasable nonvolatile memory. Theoretical and experimental analysis of WRITE/ERASE characteristics for this type of memory cell are presented. A simplified device model is given based on the concept of coupling ratios. The WRITE operation is adequately represented by the simplified model. The ERASE operation is complicated due to formation of depletion layers in the transistor's channel and under the tunnel oxide. Experimental investigation of these effects is described, and they are included in a detailed cell model. In certain cell structures, a hole current can flow from the drain into the substrate during the ERASE oepration. This effect is shown to be associated with positive charge trapping in the tunnel oxide and threshold window opening. An experimental investigation of these phenomena is described, and a recommendation is made to avoid them by an appropriate cell design.