Over 1000 V/30 mA operation GaN-on-Si MOSFETs fabricated on Si substrates

We demonstrated the operation of GaN-on-Si metal-oxide-semiconductor field effect transistors (MOSFETs) for power electronics components. The interface states at SiO₂/GaN were successfully improved by annealing at 800 °C for 30 min in N₂ ambient. The interface state density was less than 1 × 10¹¹ cm^-2 eV⁻¹ at E_c − 0.4 eV. The n⁺ contact layers as the source and drain regions as well as the reduced surface field (RESURF) zone were formed using a Si ion implantation technique with the activation annealing at 1200 °C for 10 s in rapid thermal annealing (RTA). As a result, we achieved an over 1000 V and 30 mA operation on GaN-on-Si MOSFETs. The threshold voltage was +2.6 V. It was found that the breakdown voltage depended upon the RESURF length and nitride based epi-layer thickness. In addition, we discussed the comparison of each performance of GaN-on-Si with -sapphire devices.     

A 0.18 μm CMOS linear-in-dB AGC post-amplifier for optical communications

This paper presents a fully integrated 10GBase-LX4 Ethernet receiver front-end automatic gain control amplifier realized in a 0.18 μm CMOS process. Based on a very compact and reliable inductorless design, the proposed differential post-amplifier, comprises three main digitally programmable gain stages, a DC offset cancellation network and an automatic gain feedback control loop. Experimental results demonstrate a −3 dB cut-off frequency above 2.3 GHz over a −3 to 33 dB linear-in-dB controlled gain range with a sensitivity of 2.0 mV_p-p with a BER of 10⁻¹² at 2.5 Gb/s. For the aforementioned standard, 3.125 Gb/s, an input dynamic range above 50 dB is achieved, from 2.5 mV_p-p to 800 mV_p-p, indicating a BER of 10⁻¹². The chip core area is 0.3 × 0.3 mm² and it consumes 58 mW with a single supply voltage of 1.8 V.     

Characterization of impact of process options in Germanium-On-Insulator (GeOI) high-k & metal gate pMOSFETs by low-frequency noise

The impact of technological processes on Germanium-On-Insulator (GeOI) noise performance is studied. We present an experimental investigation of low-frequency noise (LFN) measurements carried out on (GeOI) PMOS transistors with different process splits. The front gate is composed of a SiO₂/HfO₂ stack with a TiN metal gate electrode. The result is an aggressively reduced equivalent oxide thickness (EOT) of 1.8 nm. The buried oxide is used as a back gate for experimental purposes. Front and back gate interfaces are characterized and the slow oxide trap densities are extracted. The obtained values are comprised between 5 × 10¹⁷ and 8 × 10¹⁸ cm⁻³eV⁻¹. No correlation between front interface trap density and front interface mobility is observed. We underline a strong correlation between rear interface trap density and rear interface mobility degradation. The impact of Ge film thickness is equally studied. For thin films, the measured drain-current noise spectral density shows that LFN can be described by the carrier fluctuation model from weak to strong inversion. For thicker film devices, in weak inversion the LFN can be described by the mobility fluctuation model and in strong inversion the LFN is described by the carrier fluctuation model. The α_H parameter for these devices is 1.2 × 10⁻³. These results are significant for the future development of GeOI technologies.     

Low threading dislocation density Ge deposited on Si (1 0 0) using RPCVD

Epitaxial Ge layer growth of low threading dislocation density (TDD) and low surface roughness on Si (1 0 0) surface is investigated using a single wafer reduced pressure chemical vapor deposition (RPCVD) system. Thin seed Ge layer is deposited at 300 °C at first to form two-dimensional Ge surface followed by thick Ge growth at 550 °C. Root mean square of roughness (RMS) of ∼0.45 nm is achieved. As-deposited Ge layers show high TDD of e.g. ∼4 × 10⁸ cm⁻² for a 4.7 μm thick Ge layer thickness. The TDD is decreasing with increasing Ge thickness. By applying a postannealing process at 800 °C, the TDD is decreased by one order of magnitude. By introducing several cycle of annealing during the Ge growth interrupting the Ge deposition, TDD as low as ∼7 × 10⁵ cm⁻² is achieved for 4.7 μm Ge thick layer. Surface roughness of the Ge sample with the cyclic annealing process is in the same level as without annealing process (RMS of ∼0.44 nm). The Ge layers are tensile strained as a result of a higher thermal expansion coefficient of Ge compared to Si in the cooling process down to room temperature. Enhanced Si diffusion was observed for annealed Ge samples. Direct band-to-band luminescence of the Ge layer grown on Si is demonstrated.     

Fabrication of Ge-MOS capacitors with high quality interface by ultra-thin SiO2/GeO2 bi-layer passivation combined with the subsequent SiO2-depositions using magnetron sputtering

Ge-MOS capacitors were fabricated by a novel method of ultra-thin SiO₂/GeO₂ bi-layer passivation (BLP) for Ge surface combined with the subsequent SiO₂-depositions using magnetron sputtering. For the Ge-MOS capacitors fabricated by BLP with O₂, to decrease oxygen content in the subsequent SiO₂ deposition is helpful for improving interface quality. By optimizing process parameters of the Ge surface thermal cleaning, the BLP, and the subsequent SiO₂ deposition, interface states density of 4 × 10¹¹ cm⁻² eV⁻¹ at around mid-gap was achieved, which is approximately three times smaller than that of non-passavited Ge-MOS capacitors. On the contrary, for the Ge-MOS capacitors fabricated by BLP without O₂, interface quality could be improved by an increase in oxygen contents during the subsequent SiO₂ deposition, but the interface quality was worse compared with BLP with O₂.     

Double-gate 1T-DRAM cell using nonvolatile memory function for improved performance

We propose a double-gate (DG) 1T-DRAM cell combining SONOS type storage node on the back-gate (control-gate) for nonvolatile memory function. The cell sensing margin and retention time characteristics were systematically examined in terms of control-gate voltage (V_cg) and nonvolatile memory (NVM) function. The additional NVM function is achieved by Fowler-Nordheim (FN) tunneling electron injection into the nitride storage node. The injected electrons induce a permanent hole accumulation layer in silicon body which improves the sensing margin and retention time characteristics. To demonstrate the effect of stored electrons in the nitride layer, experimental data are provided using 0.6 μm devices fabricated on SOI wafers.     

Indium-tin-oxide,free, flexible,nonvolatile memory devices based on graphene quantum dots sandwiched between polymethylsilsesquioxane layers

Indium-tin-oxide (ITO) free, nonvolatile memory (NVM) devices based on graphene quantum dots (GQDs) sandwiched between polymethylsilsesquioxane (PMSSQ) layers were fabricated directly on polyethylene terephthalate (PET) substrates by using a solution process technique. Current-voltage (I-V) curves for the silver nanowire/PMSSQ/GQD/PMSSQ/poly(3,4-ethylenethiophene):poly(styrene sulfonate)/PET devices at 300 K showed a current bistability. The ON/OFF ratio of the current bistability for the NVM devices was as large as 1 × 10⁴, and the cycling endurance time of the ON/OFF switching for the NVM devices was above 1 × 10⁴ s. The Schottky emission, Poole-Frenkel emission, trapped-charge limited-current, and space-charge-limited current were dominantly attributed to the conduction mechanisms for the fabricated NVM devices based on the obtained I-V characteristics, and energy band diagrams illustrating the “writing” and the “erasing” processes of the devices.     

Improved characteristics for Pd nanocrystal memory with stacked HfAlO–SiO2 tunnel layer

Stacked HfAlO-SiO₂ tunnel layers are designed for Pd nanocrystal nonvolatile memories. For the sample with 1.5 nm-HfAlO/3.5 nm-SiO₂ tunnel layer, a smaller initial memory window is obtained compared to the sample with 3.5 nm-HfAlO/1.5 nm-SiO₂ tunnel layer. Owing to the thermally induced traps in HfAlO-SiO₂ films are located at a farther distance from the Si substrate and more effective blocking of charge leakage by asymmetric tunnel barrier, a larger final memory window and better retention characteristic can be obtained for Al/blocking oxide SiO₂/Pd NCs/1.5 nm-HfAlO/3.5 nm-SiO₂/Si structure. A N₂ plasma treatment can further improve the memory characteristics. Better memory characteristics can be obtained for Pd-nanocrystal-based nonvolatile memory with an adequate thickness ratio of HfAlO to SiO₂.     

Fabrication of high-Ge-fraction strained Si1−xGex/Si hole resonant tunneling diode using low-temperature Si2H6 reaction for nanometer-order ultrathin Si barriers

Low-temperature Si barrier growth with atomically flat heterointerfaces was investigated in order to improve negative differential conductance (NDC) characteristics of high-Ge-fraction strained Si_1−xGe_x/Si hole resonant tunneling diode with nanometer-order thick strained Si_1−xGe_x and unstrained Si layers. Especially to suppress the roughness generation at heterointerfaces for higher Ge fraction, Si barriers were deposited using Si₂H₆ reaction at a lower temperature of 400 °C instead of SiH₄ reaction at 500 °C after the Si_0.42Ge_0.58 growth. NDC characteristics show that difference between peak and valley currents is effectively enhanced at 11-295 K by using Si₂H₆ at 400 °C, compared with that using SiH₄ at 500 °C. Non-thermal leakage current at lower temperatures below 100 K tends to increase with decrease of Si barrier thickness. Additionally, thermionic-emission dominant characteristics at higher temperatures above 100 K suggests a possibility that introduction of larger barrier height (i.e. larger band discontinuity) enhances the NDC at room temperature by suppression of thermionic-emission current.     

Characteristics of offset-structure polycrystalline-siliconthin-film transistors

In order to reduce anomalous leakage current from n-channel polycrystalline-silicon thin-film transistors (poly-Si TFTs), an offset structure that has an n^- region between channel and n⁺ source-drain electrodes has been proposed. Drain-current measurements of the poly-Si TFT prove that the offset structure is effective in reducing the anomalous leakage current, and that the optimization of the offset length and the doping concentration in the offset region enlarge the ON/OFF current ratio. Implantation of 5×10¹³ cm^-2 phosphorus ions in the offset region makes the ON/OFF current ratio more than one order of magnitude larger than that of conventional structure TFTs     

Au and non-Au based rare earth metal-silicide ohmic contacts to p-InGaAs

The aim of this study is to improve the electrical properties of ohmic contacts that plays crucial role on the performance of optoelectronic devices such as laser diodes (LDs), light emitting diodes (LEDs) and photodetectors (PDs). The conventional (Pd/Ir/Au, Ti/Pt/Au and Pt/Ti/Pt/Au), Au and non-Au based rare earth metal-silicide ohmic contacts (Gd/Si/Ti/Au, Gd/Si/Pt/Au and Gd/Si/Pt) to p-InGaAs were investigated and compared each other. To calculate the specific contact resistivities the Transmission Line Model (TLM) was used. Minimum specific contact resistivity of the conventional contacts was found as 0.111 × 10⁻⁶ Ω cm² for Pt/Ti/Pt/Au contact at 400 °C annealing temperature. For the rare earth metal-silicide ohmic contacts, the non-Au based Gd/Si/Pt has the minimum value of 4.410 × 10⁻⁶ Ω cm² at 300 °C annealing temperature. As a result, non-Au based Gd/Si/Pt contact shows the best ohmic contact behavior at a relatively low annealing temperature among the rare earth metal-silicide ohmic contacts. Although the Au based conventional ohmic contacts are thermally stable and have lower noise in electronic circuits, by using the non-Au based rare earth metal-silicide ohmic contacts may overcome the problems of Au-based ohmic contacts such as higher cost, poorer reliability, weaker thermal stability, and the device degradation due to relatively higher alloying temperatures. To the best of our knowledge, the Au and non-Au based rare earth metal-silicide (GdSi_x) ohmic contacts to p-InGaAs have been proposed for the first time.     

Effect of rapid thermal annealing on pentacene-based thin-film transistors

The bottom contact pentacene-based thin-film transistor is fabricated, and it is treated by rapid thermal annealing (RTA) with the annealed temperature up to 240 °C for 2 min in the vacuum of 1.3 × 10⁻² torr. The morphology and structure for the pentacene films of OTFTs were examined by scanning electron microscopy and X-ray diffraction technique. The thin-film phase and a very small fraction of single-crystal phase were found in the as-deposited pentacene films. While the annealing temperature increases to 60 °C, the pentacene molecular ordering was significantly improved though the grain size only slightly increased. The device annealed at temperature of 120 °C has optimal electrical properties, being consistent with the experimental results of XRD. The post-annealing treatment results in the enhancement of field-effect mobility in pentacene-based thin-film transistors. The field-effect mobility increases from 0.243 cm²/V s to 0.62 cm²/V s. Besides, the threshold voltage of device shifts from −7 V to −3.88 V and the on/off current ratio increases from 4.0 × 10³ to 8.7 × 10³.     

High-density formation of Ge quantum dots on SiO2

We formed high-density Ge quantum dots (QDs) on an ultrathin SiO₂ layer by controlling the early stages of low-pressure chemical vapor deposition (LPCVD) with a germane gas (GeH₄) assisted by a remote plasma of pure H₂. We then characterized the electronic charged states of the QDs by an AFM/Kelvin probe technique. The formation of single crystalline Ge-QDs with an areal dot density of ∼2.0 × 10¹¹ cm⁻² was confirmed after examining the surface morphology and lattice by atomic force microscopy and transmission electron microscopy, respectively. It has been suggested that an increase in the flux of deposition precursors due to efficient decomposition of GeH₄ by a supply of hydrogen radicals and the dehydration reaction of surface OH bonds plays a role in nucleation of Ge-QDs on SiO₂. Surface passivation with hydrogen may also promote the surface migration of deposition precursors during LPCVD. The surface potential of the dots changed in a stepwise manner with respect to the tip bias due to multistep electron injection into and extraction from the Ge-QDs.     

The effect of light irradiation on electrons and holes trapping in nonvolotile memory capacitors employing sub 10 nm SiO2-HfO2 stacks and Au nanocrystals

We demonstrate the possibility to control charge trapping in the memory stacks comprised of metal nanocrystals (NCs) sandwiched between SiO₂ and high-k dielectric films by light irradiation. Non-equilibrium depletion effects in the state of the art charge trapping memories are reported for the first time. The studied nonvolatile memory devices employ Au NCs, thermal SiO₂ tunnel layer, atomic layer deposited HfO₂ blocking layer and Au/Pt metal gate. The memory windows are 3 V and 10.5 in the dark and under illumination for ±10 V programming voltages. Reliability limitations of the studied structure, in particular leakage currents and effects in high electric fields have been investigated in detail and are discussed in view of the mentioned device application. Low programming voltages and currents, and high light sensitivity make suggested NVM structures promising for developing digital imagers with ultra-low power consumption.     

Subband structure and effective mass of relaxed and strained Ge (1 1 0) PMOSFETs

Effective mass and mobility of strained Ge (1 1 0) inversion layer in PMOSFET are studied theoretically in this paper. The strain condition considered in the calculations is the intrinsic strain resulting from growing the Ge layer on the (1 1 0) Si substrate. The quantum confinement effect resulting from the vertical effective electric field is incorporated into the k · p calculation. Various effective masses, such as quantization effective mass, m_z, density of states effective mass, m_DOS, and conductivity mass, m_C, as well as the hole mobility of strained Ge (1 1 0) inversion layer for PMOS under substrate strain and various effective electric field strengths are all investigated.     

SiGe:C HBT transit time analysis based on hydrodynamic modeling using doping, composition and strained dependent SiGe:C carriers mobility and relaxation time

A global additional uniaxial stress ranging from −1 GPa to 1 GPa along different directions has been applied to SiGe HBTs in order to improve the high-frequency performance of these devices. Two transistors have been investigated: a slow one (peak f_T = 110 GHz) and a fast one (peak f_T = 750 GHz). The results from full-band Monte Carlo simulations show that the cutoff frequency of both devices can be improved by more than 30 percent under suitable stress conditions. A spherical-harmonics-expansion simulator is also used to investigate the spatial origin of this improvement, where it is found that the transit times are reduced in all regions (base, collector, emitter).     

Design and optimization of high voltage LDMOS transistors on 0.18 μm SOI CMOS technology

In this paper, we have studied the effect of systematic downscaling of MOS channel length of the performance of the hybrid GaN MOS-HEMT with numerical simulations. The improvement in on-state conduction, together with concomitant short channel effects, including drain induced barrier lowering (DIBL) is quantitatively evaluated. A specific on-resistance of 2.1 mΩ cm² has been projected for a MOS channel length of 0.38 μm. We also have assessed the impact of high-k gate dielectrics, such as Al₂O₃. In addition, we have found that adding a thin GaN cap layer on top of AlGaN barrier can help reducing short channel effects.     

RF power performance evaluation of surface channel diamond MESFETs

We experimentally investigate the large-signal radio frequency performances of surface-channel p-type diamond MESFETs fabricated on hydrogenated polycrystalline diamond. The devices under examination have a coplanar layout with two gate fingers, total gate periphery of 100 μm; in DC they exhibit a hole accumulation behavior with threshold voltage V_t ≈ 0-0.5 V and maximum drain current density of 120 mA/mm. The best small-signal radio frequency performances (maximum cutoff or transition frequency f_T and oscillation frequency f_max) were obtained close to the threshold and were of the order of 6 and 15 GHz, respectively. The power radio frequency response was characterized by driving the devices in class A at an operating frequency of 2 GHz and identifying through the active load-pull technique the optimum load for maximum power added efficiency. A power gain in linearity of 8 dB and an output power of approximately 0.2 W/mm with 22% power added efficiency were obtained on the optimum load impedance at a bias point V_DS = −14 V, V_GS = −1 V. To the best of our knowledge, these are the first large signal measurements ever reported for surface MESFET on polycrystalline diamond, and show the potential of such technology for the development of microwave power devices.     

Study of Arsenic ion implantation of patterned strained Si NWs

A systematic study of the impact of As⁺ ion implantation on strain relaxation and dopant activation of biaxially strained SSOI layers and uniaxially strained/unstrained NWs is presented. Three aspects are investigated: (i) the quality of the single crystalline layers and the NWs, (ii) strain relaxation of the implanted NWs and (iii) dopant activation of the layers and NWs. Optimization of the doping conditions resulted into very low contact resistivities of NiSi contacts on strained and unstrained 70 nm SOI layers and Si NWs. For NW contacts values as low as 1.2 × 10⁻⁸ Ω cm² for an As⁺ dose of 2 × 10¹⁵ cm⁻² were achieved, which is 20 times lower than for planar contacts made under the same implantation and annealing conditions.     

Compact model for long-channel cylindrical surrounding-gate MOSFETs valid from low to high doping concentrations

This paper presents a compact model for the electrostatic potentials and the current characteristics of doped long-channel cylindrical surrounding-gate (SRG) MOSFETs. An analytical expression of the potentials is derived as a function of doping concentration. Then, the mobile charge density is calculated using the analytical expressions of the surface potential at the surface and the difference of potentials between the surface and the center of the silicon doped layer. Using the expression obtained for the mobile charge, a drain current expression is derived. Comparisons of the modeled expressions with the simulated characteristics obtained from the 3D ATLAS device simulator for the transfer characteristics, as well for the output characteristics, show good agreement within the practical range of gate and drain voltages and for doping concentrations ranging from 10¹⁶ cm⁻³ to 5 × 10¹⁸ cm⁻³.