含两个荷控忆阻器的五阶混沌电路研究

忆阻器作为一种具有记忆功能的新型非线性元件,被广泛应用于非线性电路系统设计中。利用两个基于荷控光滑模型的忆阻器以及采用常见的线性电子元件电感、电容、负电阻等设计了一种新的五阶混沌振荡电路。采用常规的系统动力学分析方法,分析了系统平衡点稳定性、相图、李雅普诺夫指数谱和分叉图,研究了系统随电路参数和荷控忆阻器初始状态变量变化的非线性动力学特性。Matlab数值仿真结果验证了理论分析的正确性。     

基于双曲函数的通用型荷控忆阻器电路等效模型分析

目前,忆阻器模拟器的研究主要集中在磁控忆阻器,对荷控忆阻器模拟器的研究不多,双曲函数型的荷控忆阻器模拟器也很少涉及。因此,该文提出一种基于双曲函数的通用型荷控忆阻器模拟器。模拟器通过电压-电流的相互转换电路,实现电路中电压和电流信号之间的相互转换,再通过电路中对应的电路模块对产生的信号进行计算,最终得到通用型双曲荷控忆阻器模型。模拟器能够实现双曲正弦、双曲余弦以及双曲正切函数对应的荷控忆阻器模型。通用型双曲函数荷控忆阻器模拟器对应的等效电路,主要由运算放大器、电阻、电容、三极管等基本元件组成。分析模拟器在不同幅值以及不同频率的输入信号下的伏安特性曲线,得出荷控忆阻器模拟器符合记忆元件的基本特性。该文提出的通用型双曲函数荷控忆阻器模型,对忆阻器模型的发展具有一定的参考意义。     

忆阻器的建模及高精度忆阻值读写电路的设计

使用现有电路元件设计了一种荷控忆阻器的理论模型。由于把忆阻器应用于存储器、神经网络、信号处理等领域均涉及到忆阻器的读写操作,并且目前忆阻器大多是数字量0和1的操作,没有模拟量的操作。所以利用了荷控忆阻器的电荷特性,给出一种描述如何读取忆阻器的模拟忆阻值的方法。利用了荷控忆阻器的频率特性,设计了一个反馈式忆阻值写电路,该电路能够在忆阻器的阻态范围内进行任意模拟量的写操作。仿真结果验证了设计的正确性。     

第四种无源电子元件忆阻器的研究及应用进展

忆阻器是一类具有电阻记忆行为的非线性电路元件,被认为是除电阻、电容、电感外的第四个基本电路元件。综述了忆阻器和忆阻系统概念的产生与发展过程,实现忆阻功能的几种模型与机理,如边界迁移、自旋阻塞、绝缘体-金属转变、丝导电、氧化还原反应等。阐述了忆阻器和忆阻系统在模型分析、生物记忆行为仿真、基础电路和器件设计方面的应用前景。     

基于荷控忆阻器的四阶混沌电路

近年来,基于亿阻器的混沌电路受到国内外学者的广泛关注.然而现阶段的研究,大都采用通过磁控忆阻器和负电导并联构成的有源忆阻器替代蔡氏电路中蔡氏二极管的方法.而采用荷控忆阻器的混沌电路大都同时使用荷控忆阻器与磁控忆阻器构成的五阶双忆阻器混沌电路.该文在蔡氏电路的基础上,采用荷控忆阻器与电感串联的形式构造了一个新的四阶忆阻混沌电路,并提出改进的忆阻器非线性特性曲线,通过数值仿真的方法进行了验证.最后,对这个新的四阶忆阻混沌电路进行动力学特性分析,主要通过李雅普诺夫指数和吸引子在相平面的投影.     

忆阻器特性及其在电路设计中的应用

介绍了忆阻器的起源与发展历程,讨论了忆阻器的端口特性及其在电路设计中的应用,并将忆阻器的端口特性与电阻、电感、电容元件作比较;其次,讨论了目前比较常见的四种忆阻器的数学模型及其特点;最后,根据忆阻器具有的非线性特性和特殊的记忆功能,分析了其构成混沌电路、滤波电路及波形发生电路时,电路所具有的特殊性能。     

双忆阻Shinriki振荡器的超级多稳态和反单调性分析

本文通过在Shinriki振荡器中引入一个有源荷控忆阻,并且利用一个含绝对值项的磁控忆阻代替原电路中的串并联二极管回路,提出了一种含双忆阻器的Shinriki振荡器.根据电路拓扑结构图建立了忆阻振荡器的数学模型,开展了振荡器随电路元件参数变化时的共存分岔、周期-混沌状态转移等动力学特性分析.结果表明,双忆阻Shinriki振荡器对忆阻的参数值和初始条件有极大的依赖性,随着忆阻参数值和初始条件在特定域内变化,振荡器将呈现出共存反单调现象、不完全对称行为、超级多稳态等非线性动力学行为.此外,基于FPGA开发板完成了双忆阻Shinriki振荡器的数字电路仿真,在示波器上捕捉实验波形,验证了动力学分析的正确性.     

一种改进的忆阻器的SPICE模型及其仿真

忆阻器(Memristor)是一种具有记忆功能的无源电子元件,其概念由蔡少棠于1971年提出.2008年HP实验室发现了一种基于电阻开关的二端非易失记忆器件,从而证实了忆阻器的存在.在研究HP实验室发现的忆阻器的基础上,分析了目前一些忆阻器模型的优缺点,设计了一种改进的忆阻器模型.经过PSPICE仿真验证,该模型成功地模拟了HP实验室发现的忆阻器物理模型的基本特性.     

交叉杆结构忆阻器件的研究进展

忆阻器被认为是除电容器、电感器、电阻器之外的第四种无源器件,具有器件结构简单、操作速度快、功耗小等优点,是具有电阻记忆特性的非易失性的电阻元件。而交叉杆结构忆阻器件作为忆阻器的一种结构,由于其较之其他结构的忆阻器具有结构简单、集成度高、容错性和并行性优良等特性,受到了外界广泛的关注及研究。文章综述了近年来交叉杆忆阻器的兴起和发展现状,阐述了以交叉杆结构为基础的各类忆阻器的制备及应用。     

基于忆阻器的自动增益控制电路设计

忆阻器被认为是除了电阻、电容、电感之外的第四个基本电路元件,它是一种非线性二端无源器件,具有“记忆”功能.忆阻器在众多领域中具有巨大的应用潜力,有望推动整个电路理论的变革.介绍了一种改进的忆阻器SPICE模型,在此基础上,设计了一种基于忆阻器的自动增益控制电路.通过SPICE对电路进行仿真,证明该设计是可行的,完全实现了增益的自动控制.     

悬浮栅结构ISFET动态特性的HSPICE仿真

通过对ISFET敏感机理的理论分析,根据表面基模型,建立了悬浮栅结构ISFET器件的HSPICE动态行为模型,对ISFET器件的动态特性进行仿真得到时间响应曲线,并探讨了薄膜等效电阻、薄膜等效电容、互连线寄生电容和寄生电阻等因素与动态特性中延迟时间和迟滞等不理想因素的关系,为ISFET/REFET差分结构集成传感器芯片设计提供理论指导。     

On the realization of the floating simulators using only grounded passive components

In this paper, two novel circuits for realizing floating inductance, floating capacitance, floating frequency dependent negative resistance (FDNR) and grounded to floating admittance converter depending on the passive component selection are proposed. Both of the proposed simulators employ second-generation current controlled conveyors (CCCIIs) and only grounded passive elements. The non-ideal current and voltage gain as well as parasitic impedance effects on the first proposed circuit are investigated. Also, simulation results using SPICE program are given for the first introduced floating simulator to verify the theory and to exhibit the performance of the circuit.     

多隧道结单电子动态存储器的Monte Carlo模拟

本文采用Monte Carlo方法模拟了多隧道结单电子动态存储器的存储特性，考察了隧道结的个数、隧道结电容、隧道结电阻、脉冲电压幅度等参数对存储器的存储时间和饱和充电电荷的影响，并与宏观RC电路进行了比较。     

新型忆阻器混沌电路及其在图像加密中的应用

忆阻器是一种拥有记忆功能的电阻,目前忆阻器的研究热点及难点在于新模型的建立以及相关方面的应用。该文提出一种基于双曲正弦函数的新型磁控忆阻器模型,通过分析电压和电流的相轨迹关系,发现其具有典型的忆阻器电压-电流特性曲线。利用新建的忆阻器模型构造新型忆阻混沌系统,通过数值仿真绘出新系统的相轨迹图、分岔图、Lyapunov 指数谱等,分析了不同参数时系统的混沌演化过程。另外,基于电路仿真软件Multisim研制了实验仿真电路, 该电路结构简单、易于实际制作,且仿真实验与理论分析结论十分吻合,证实了提出的忆阻混沌系统电路在物理上是可以实现的。最后,利用新系统混沌序列对图像进行加密,重点分析了加密直方图、相邻像素相关性以及抗攻击能力与密钥敏感性,结果表明新系统对图像密钥及明文都非常敏感,密钥空间较大,新提出的忆阻混沌系统应用于图像加密具有较高的安全性能。     

VLSI circuit reconstruction from mask topology

This paper discusses whether and how parasitic circuit elements must be included in the circuit simulator source file to obtain reliable simulation results. In particular, attention is paid to fabrication tolerances, wire capacitance (including fringing effects), wire resistance (dispersive line effects), coupling capacitances and capacitances associated with contacts and the aspect ratio of (non-rectangular) transistors.     

An efficient memristor crossbar architecture for mapping Boolean functions using Binary Decision Diagrams (BDD)

The memristor is considered as the fourth fundamental circuit element along with resistor, capacitor and inductor. It is a two-terminal passive circuit element whose resistance value changes based on the amount of charge flowing through it. Another property of the memristor is that its resistance change is non-volatile in nature, and hence can be used for non-volatile memory applications. Researchers have been exploring memristors from various perspectives such as logic design and storage applications. In this paper, a slicing crossbar architecture for the efficient mapping of Boolean functions is proposed which exploits gate level parallelism using the memristor aided logic (MAGIC) design style. A Boolean function is first represented as a Binary Decision Diagram (BDD). The BDD nodes are expressed as netlists of NOR and NOT gates, and are mapped to the proposed slicing crossbar architecture with parallel node evaluation where possible. This is the first approach that combines BDD-based synthesis with MAGIC gate evaluation on memristor crossbar, while at the same time avoiding crossbar-related problems using a slicing architecture. Experimental evaluations on standard benchmark functions show considerable improvement in the solutions.     

Accurate analysis of parasitic current overshoot during forming operation in RRAMs

In this paper, a peculiar attention is turned towards the understanding of the current overshoot occurring during the forming operation in resistive switching memory devices. This phenomenon is attributed to the discharge of a parasitic capacitance in parallel to the resistive device in simple 1R (one resistor, no transistor/diode selector) architectures. The impact of such an overshoot is analyzed on both NiO and HfO₂-based memory elements by performing measurements with different setups (quasi-static and pulse measurements). We show that the parasitic event is more severe as the forming voltage in the memory device increases. Moreover, it is shown that the post-forming resistance cannot be simply adjusted by a current compliance available on semiconductor parameter analyzers, since this internal limiter is ineffective in the microsecond range for compliance levels lower than the current spike. The current overshoot playing a detrimental role on the electrical performances of resistive devices, it must be carefully monitored when assessing the electrical performances in simple 1R architectures.     

Capacitive effects in IGBTs limiting their reliability under short circuit

The short-circuit oscillation mechanism in IGBTs is investigated in this paper by the aid of semiconductor device simulation tools. A 3.3-kV IGBT cell has been used for the simulations demonstrating that a single IGBT cell is able to oscillate together with the external circuit parasitic elements. The work presented here through both circuit and device analysis, confirms that the oscillations can be understood with focus on the device capacitive effects coming from the interaction between carrier concentration and the electric field. The paper also shows the 2-D effects during one oscillation cycle, revealing that the gate capacitance changes according with the shape of the electric field due to the charge distribution in the n-base. It has been identified that the time-varying capacitance leads to parametric oscillations together with the stray gate inductance, which limit the reliability of the IGBT.     

A low-power inverted ladder D/a converter

Interpolating, dual resistor ladder digital-to-analog converters (DACs) typically use the fine, least significant bit (LSB) ladder floating upon the static most significant bit (MSB) ladder. The usage of the LSB ladder incurs a penalty in dynamic performance due to the added output resistance and switch matrix parasitic capacitance. Current biasing of the LSB ladder addresses this issue by employing active circuitry. We propose an inverted ladder DAC, where an MSB ladder slides upon two static LSB ladders. While using no active components this scheme achieves lower output resistance and parasitic capacitance for a given power budget. We present a 0.35-/spl mu/m, 3.3-V implementation consuming 22-/spl mu/A current with output resistance of 40 k/spl Omega/ and effective parasitic capacitance of 650 fF.