On the development of high-throughput and area-efficient multi-mode cryptographic hash designs in FPGAs

In this paper, area-efficient and high-throughput multi-mode architectures for the SHA-1 and SHA-2 hash families are proposed and implemented in several FPGA technologies. Additionally a systematic flow for designing multi-mode architectures (implementing more than one function) of these families is introduced. Compared to the corresponding architectures that are produced by a commercial synthesis tool, the proposed ones are better in terms of both area (at least 40%) and throughput/area (from 32% up to 175%). Finally, the proposed architectures outperform similar existing ones in terms of throughput and throughput/area, from 4.2× up to 279.4× and from 1.2× up to 5.5×, respectively.     

Distributed crossbar architecture for area-efficient combined data/instruction caches with multiple ports

A proposal to improve the low access bandwidth of conventional one-port caches by utilising a multi-bank structure with distributed crossbar to increase port number at small additional area cost is presented. This enables combination of data and instruction caches into a single multi-port cache as well as different wordlength for each port. Through dynamically scheduling the storage space used for data and instructions, 25% smaller storage capacity is sufficient for a given maximum cache-miss probability.     

Low-latency architectures for high-throughput rate Viterbi decoders

In this paper, a novel K-nested layered look-ahead method and its corresponding architecture, which combine K-trellis steps into one trellis step (where K is the encoder constraint length), are proposed for implementing low-latency high-throughput rate Viterbi decoders. The proposed method guarantees parallel paths between any two-trellis states in the look-ahead trellises and distributes the add-compare-select (ACS) computations to all trellis layers. It leads to regular and simple architecture for the Viterbi decoding algorithm. The look-ahead ACS computation latency of the proposed method increases logarithmically with respect to the look-ahead step (M) divided by the encoder constraint length (K) as opposed to linearly as in prior work. For a 4-state (i.e., K=3) convolutional code, the decoding latency of the Viterbi decoder using proposed method is reduced by 84%, at the expense of about 22% increase in hardware complexity, compared with conventional M-step look-ahead method with M=48 (where M is also the level of parallelism). The main advantage of our proposed design is that it has the least latency among all known look-ahead Viterbi decoders for a given level of parallelism.     

一种高吞吐率、低成本的固态硬盘数据安全方案

针对SATA-I型接口固态硬盘的数据安全问题,提出了一种高吞吐率、低成本的数据加密方案及密钥管理方法,该方法选取AES-128密码算法和CTR加密模式,利用射频识别(RFID)技术管理密钥。在Spartan3E系列FPGA上实现了加密电路,基于Mifare S50射频读写模块实现了密钥的产生、更改和保存。结果表明,本文提出的安全方案FPGA资源占用率和密钥管理成本均比较低,能够在150 MHz主频下达到1.7 Gbps吞吐率,完全满足接口通信速率要求。     

Synthesis and comparison of low-power high-throughput architectures for SAD calculation

Video applications are increasingly present in consumer electronic devices which require low-power and low-energy consumption. Sum of Absolute Differences (SAD) is the most used distortion metric in video coding implementation and consumes a relative large area in the motion estimation hardware. This paper presents the standard-cells synthesis and a comprehensive analysis of various parallel hardware architectures alternatives for SAD calculation, focusing on different design constraints such as high-performance (maximum throughput) and the tradeoff between high-performance and low-power dissipation (namely an isoperformance target). Low-power techniques supported by commercial standard-cells tools are exercised in this design, such as clock gating, multi-threshold (VT) and a combination of slow and fast standard-cells. We achieved significant power reduction for the architectures with lower frequencies and higher parallelism, slow cells and mainly with only one pipeline stage.     

An area-efficient bit-serial integer and GF(2) multiplier

This paper presents the design of a new multiplier architecture for normal integer multiplication of positive and negative numbers as well as for multiplication in finite fields of order 2ⁿ. It has been developed to increase the performance of algorithms for cryptographic and signal processing applications on implementations of the Instruction Systolic Array (ISA) parallel computer model [M. Kunde, H.W. Lang, M. Schimmler, H. Schmeck, H. Schröder, Parallel Computing 7 (1988) 25-39, H.W. Lang, Integration, the VLSI Journal 4 (1986) 65-74]. The multiplier operates least significant bit (LSB)-first for integer multiplication and most significant bit ( )-first for finite field multiplication. It is a modular bit-serial design, which on the one hand can be efficiently implemented in hardware and on the other hand has the advantage that it can handle operands of arbitrary length.     

On the design of power- and area-efficient Dickson charge pump circuits

This paper aims at investigating some methods for designing an area- and power-efficient Dickson charge pump circuit for on-chip high-voltage source generation. A comprehensive study on two conventional methods, with one of them based on optimizing the number of stage for minimum silicon area (minimum area method) and the other for maximum power efficiency (optimal power method), will be presented by considering both top- and bottom-plate parasitic capacitances. It was found that when the parasitic factors are as large as 0.1, the area and power efficiencies of the charge pumps designed with either the optimal power or minimum area method do not have much degradation. However, when the parasitic factors are small, charge pumps designed with the optimal power and minimum area methods can, respectively, result in a large area and poor power efficiency. The power efficiency of the charge pump designed with the minimum area method may be reduced by 50 %, while the area of the charge pump designed with the optimal power method can be 1–2 times larger, when the parasitic factors are 0.01. Hence, neither the optimal power nor minimum area methods should be used when the parasitic factors are small, unless the power or area is the only concern in the design. With this connection, the number of stage which leads to an area and power-efficient charge pump is suggested. Validity was proved by the good agreement between the simulated and the expected results for some designed charge pump circuits of the proposed design strategy.     

Low-power and area-efficient FIR filter implementation suitable for multiple taps

This paper describes a 32-tap finite impulse response (FIR) filter with two 16-tap macros suitable for multiple taps. The derived condition for a coded coefficient and data block shows 35% savings in power consumption and 44% improvement in occupied area compared to a typical radix-4 modified Booth algorithm. According to the condition and separated shifting-accessing clock scheme, we have implemented a 32-tap FIR filter in 0.6-/spl mu/m CMOS technology with three levels of metal. The chip that occupies 2.3/spl times/2.5 mm/sup 2/ of silicon area has an operating frequency of 20 MHz and consumes 75 mW at V/sub dd/=3.3 V.     

Low-energy and area-efficient switching scheme for SAR A/D converter

A high energy-efficiency switching scheme for low-power successive approximation resister analogue-to-digital converter is proposed. With sequence initialization, monotonic switching procedure and intermittent multiple references, the average switching energy and total capacitance of the proposed scheme are reduced by 97.7 and 87.5 % respectively compared to the conventional architecture. The applicability and superiority of the proposed scheme are proven by Matlab modeling and comparison with previous works.     

An area-efficient topology for VLSI implementation of Viterbidecoders and other shuffle-exchange type structures

A topology for single-chip implementation of computing structures based on shuffle-exchange (SE)-type interconnection networks is presented. The topology is suited for structures with a small number of processing elements (i.e. 32-128) whose area cannot be neglected compared to the area required for interconnection. The processing elements are implemented in pairs that are connected to form a ring. In this way three-quarters of the interconnections are between neighbors. The ring structure is laid out in two columns and the interconnection of nonneighbors is routed in the channel between the columns. The topology has been used in a VLSI implementation of the add-compare-select (ACS) module of a fully parallel K=7, R=1/2 Viterbi decoder. Both the floor-planning issues and some of the important algorithm and circuit-level aspects of this design are discussed. The chip has been designed and fabricated in a 2-μm CMOS process using MOSIS-like simplified design rules. The chip operates at speeds up to 19 MHz under worst-case conditions (V_DD=4.75 V and T_A=70°C). The core of the chip (excluding pad cells) is 7.8×5.1 mm² and contains approximately 50000 transistors. The interconnection network occupies 32% of the area     

High-linear,energy-efficient and area-efficient switching algorithm for high-speed SAR ADCs

Decreasing the size of DAC capacitors is a solution to achieve high-speed and low-power successive-approximation register analog-to-digital converters (SAR ADCs). But decreasing the size of capacitors directly effects the linearity performance of converter. In this paper, the effect of capacitor mismatch on linearity performance of charge redistribution SAR ADCs is studied. According to the achieved results from this investigation, a new tri-level switching algorithm is proposed to reduce the matching requirement for capacitors in SAR ADCs. The integral non-linearity (INL) and the differential non-linearity (DNL) of the proposed scheme are reduced by factor of two over the conventional SAR ADC which is the lowest compared to the previous schemes. In addition, the switching energy of the proposed scheme is reduced by 98.02% as compared with the conventional architecture which is the most energy-efficient algorithms in comparison with the previous algorithms, too. To evaluate the proposed method an 8-bit 50 MS/s SAR ADC is designed in 0.18 um CMOS process technology. According to the obtained simulation results, the designed ADC digitizes a 25-MHz input with 48.16 dB SNDR while consuming about 589 μW from a 1.2-V supply.     

Low-power and area-efficient PSK demodulator for wirelessly powered implantable command receivers

A phase shift keying demodulator featuring miniaturisation and ultra-low power is presented. By taking advantage of a high signal-to-noise ratio on wirelessly power-combined data transmission, the demodulation can be performed without the carrier recovery circuits requiring phase lock loop, making the design quite competitive with those currently demonstrated in the literature.     

Walsh code assignment and data structure for variable data rate communications

In digital communication systems, variable-length Walsh codes, also called orthogonal variable spreading factor codes, are used to support simultaneous variable-rate data transmission. This paper describes algorithms for dynamic variable- length Walsh code assignment. Optimal assignment criterion is derived and an efficient data structure for maintaining variable- length Walsh codes is introduced. The benefits of code reallocation are also studied. Performance is evaluated via simulation.     

An area-efficient and low-power 64-point pipeline Fast Fourier Transform for OFDM applications

In an orthogonal frequency division multiplexing (OFDM) based wireless systems, Fast Fourier Transform (FFT) is a critical block as it occupies large area and consumes more power. In this paper, we present an area-efficient and low power 16-bit word-width 64-point radix-2² and radix-2³ pipelined FFT architectures for an OFDM-based IEEE 802.11a wireless LAN baseband. The designs are derived from radix-2^k algorithm and adopt a Single-Path Delay Feedback (SDF) architecture for hardware implementation. To eliminate the complex multipliers and read-only memory (ROM) which is used for internal storage of twiddle factor coefficients, the proposed 64-point FFT employs a Canonical Signed Digit (CSD) complex constant multiplier using adders, multiplexers and shifters. The complex constant multiplier (CCM) is modified using common sub-expression sharing block that reduces the area of the design. The proposed radix-2² and radix-2³ pipelined FFT architectures are modeled and implemented using TSMC 180 nm CMOS technology with a supply voltage of 1.8 V. The implementation results show that the proposed architectures significantly reduces the hardware cost and power consumption in comparison to existing 64-point FFT architectures.     

Increasing data rate over wireless channels

Space-time coding (STC) is a new coding/signal processing framework for wireless communication systems with multiple transmit and multiple receive antennas. This new framework has the potential of dramatically improve the capacity and data rates. In addition, this framework presents the best trade-off between spectral efficiency and power consumption. ST codes (designed so far) come in two different types. ST trellis codes offer the maximum possible diversity gain and a coding gain without any sacrifice in the transmission bandwidth. The decoding of these codes, however, would require the use of a vector form of the Viterbi decoder. Space-time block codes (STBCs) offer a much simpler may of obtaining transmit diversity without any sacrifice in bandwidth and without requiring huge decoding complexity. In fact, the structure of the STBCs is such that it allows for very simple signal processing (linear combining) for encoding/decoding, differential encoding/detection, and interference cancellation. This new signal processing framework offered by ST codes can be used to enhance the data rate and/or capacity in various wireless applications. That is the reason many of these STC ideas have already found their way to some of the current third-generation wireless systems standards     

Heart rate indication using musical data

Heart rate data reflects various physiological states such as biological workload, stress at work and concentration on tasks, drowsiness and the active state of the autonomic nervous system. This paper proposes system to indicate heart rate using musical data. Music changes physiological states for the better by relaxing people, or contributing to patient treatment through music therapy. Information in the form of music is advantageous because it does not hinder work as does verbal information and it contains more information than warning noises. We introduce and evaluate a prototype heart rate indication system and describe evaluation results of biofeedback effects on the worker during mental workload. The prototype system sequentially inputs the instantaneous heart rate into the computer, converts the data into musical instrument digital interface, the digital music format, and outputs it from the sound source.     

Sampling, data transmission, and the Nyquist rate

The sampling theorem for bandlimited signals of finite energy can be interpreted in two ways, associated with the names of Nyquist and Shannon. 1) Every signal of finite energy and bandwidth W Hz may be completely recovered, in a simple way, from a knowledge of its samples taken at the rate of 2W per second (Nyquist rate). Moreover, the recovery is stable, in the sense that a small error in reading sample values produces only a correspondingly small error in the recovered signal. 2) Every square-summable sequence of numbers may be transmitted at the rate of 2W per second over an ideal channel of bandwidth W Hz, by being represented as the samples of an easily constructed band-limited signal of finite energy. The practical importance of these results, together with the restrictions implicit in the sampling theorem, make it natural to ask whether the above rates cannot be improved, by passing to differently chosen sampling instants, or to bandpass or multiband (rather than bandlimited) signals, or to more elaborate computations. In this paper we draw a distinction between reconstructing a signal from its samples, and doing so in a stable way, and we argue that only stable sampling is meaningful in practice. We then prove that: 1) stable sampling cannot be performed at a rate lower than the Nyquist, 2) data cannot be transmitted as samples at a rate higher than the Nyquist, regardless of the location of sampling instants, the nature of the set of frequencies which the signals occupy, or the method of construction. These conclusions apply not merely to finite-energy, but also to bounded, signals.     

XML-based data model and architecture for a knowledge-based grid-enabled problem-solving environment for high-throughput biological imaging.

High-throughput biological imaging uses automated imaging devices to collect a large number of microscopic images for analysis of biological systems and validation of scientific hypotheses. Efficient manipulation of these datasets for knowledge discovery requires high-performance computational resources, efficient storage, and automated tools for extracting and sharing such knowledge among different research sites. Newly emerging grid technologies provide powerful means for exploiting the full potential of these imaging techniques. Efficient utilization of grid resources requires the development of knowledge-based tools and services that combine domain knowledge with analysis algorithms. In this paper, we first investigate how grid infrastructure can facilitate high-throughput biological imaging research, and present an architecture for providing knowledge-based grid services for this field. We identify two levels of knowledge-based services. The first level provides tools for extracting spatiotemporal knowledge from image sets and the second level provides high-level knowledge management and reasoning services. We then present cellular imaging markup language, an extensible markup language-based language for modeling of biological images and representation of spatiotemporal knowledge. This scheme can be used for spatiotemporal event composition, matching, and automated knowledge extraction and representation for large biological imaging datasets. We demonstrate the expressive power of this formalism by means of different examples and extensive experimental results.