Thermal transient characteristics of die attach in high power LED PKG

The reliability of packaged electronics strongly depends on the die attach quality because any void or a small delamination may cause instant temperature increase in the die, leading sooner or later to failure in the operation. Die attach materials have a key role in the thermal management of high power LED packages by providing the low thermal resistance between the heat generating LED chips and the heat dissipating heat slug. In this paper, thermal transient characteristics of die attach in high power LED PKG have been studied based on the thermal transient analysis using the evaluation of the structure function of the heat flow path. With high power LED packages fabricated by die attach materials such as Ag paste, solder paste and Au/Sn eutectic bonding, we have demonstrated for characteristics such as cross-section analysis, shear test and visual inspection after shear test of die attach and how to detect die attach failures and to measure thermal resistance values of die attach in high power LED PKG. From the differential structure function of the thermal transient characteristics, we could know the result that die attach quality of Au/Sn eutectic bonding with the thermal resistance of about 3.5 K/W was much better than this of Ag paste and solder paste with the thermal resistance of about 11.5–14.2 K/W and 4.4–4.6 K/W, respectively. From this results, it is possible to fabricate high power LED with a small thermal resistance and a good die attach quality by applying Au/Sn eutectic bonding die attach with a high reliability and a good repeatability.     

Vertical InGaN light-emitting diodes with Ag paste as bonding layer

Vertical InGaN-based light-emitting diodes (LEDs) were fabricated with a Si substrate using Ag paste as bonding layer. Vertical LEDs with Ag paste bonding layer were bonded with Si substrate at a low temperature of 140 °C. In addition to the low-temperature bonding process, the soft property of Ag paste could better alleviate thermal stress compared with conventional eutectic metal bonding layer such as Au–Sn. Under the same test conditions, these two LEDs showed similar optical and electrical properties and reliability. However, LEDs with Ag-paste bonding layer were fabricated through a low-temperature bonding process. The characteristic of soft solder enables a relatively wider process window, such as bonding pressure and temperature, and a higher yield as compared with the vertical LEDs with Au–Sn eutectic bonding layer.     

Modified Face-Down Bonding of Ridge-Waveguide Lasers Using Hard Solder

A modified face-down bonding technique of ridge-waveguide laser diodes (LDs) using 80Au20Sn solder has been performed. For ease of manufacturability, a bonding window with good bonding integrity and improved optical performance was determined. Metallographical investigation showed that the solder joint comprised of a layer of delta phase compound near the solder/heatsink interface, a layer of (Au,Ni)Sn intermetallic compound (IMC) at the solder/heatsink interface, and zeta' phase Au/Sn compound at the center of the solder joint. The delta phase shifted to the interfaces after reflow was postulated by its lower surface tension than zeta' phase Au/Sn compound. Good bonding integrity was observed with LD residues still adhering onto the bond pad after die shear testing. Scanning electron microscopy (SEM)/energy dispersive X-ray (EDX) analyses of the fracture surface showed that the fracture occurred within the LD, at the GaAs/SiN interface. LDs bonded with this modified bonding process achieved an optical improvement of 2.5-3X compared to the unbonded LDs due to its good thermal management. These bonded LDs further exhibited good long-term reliability with no significant degradation in optical performance and no significant microstructure evolution in the solder joint after 500 thermal cycling test.     

Effects of Au and Pd Additions on Joint Strength, Electrical Resistivity, and Ion-Migration Tolerance in Low-Temperature Sintering Bonding Using Ag2O Paste

A new bonding process using an Ag₂O paste consisting of Ag₂O particles mixed with a triethylene glycol reducing agent has been proposed as an alternative joining approach for microsoldering in electronics assembly, which currently uses Pb-rich, high-temperature solders. Ag nanoparticles were formed at approximately 130°C to 160°C through a reduction process, sintered to one another immediately, and bonded to a metal substrate. An Au-coated Cu specimen was successfully bonded using the Ag₂O paste. The resulting joint exhibited superior strength compared with joints fabricated using conventional Pb-rich solders. To improve ion-migration tolerance, the Ag₂O paste was mixed with Au and Pd microparticles to form sintered Ag-Au and Ag-Pd layers, respectively. The additions of Au and Pd improved the ion-migration tolerance of the joint. Regarding the mechanical properties of the joints, addition of secondary Au and Pd both resulted in decreased joint strength. To match the joint strength of conventional Pb-10Sn solder, the mixing ratios of Au and Pd were estimated to be limited to 16?vol.% and 7?vol.%, respectively. The electrical resistivities of the sintered layers consisting of 16?vol.% Au and 7?vol.% Pd were lower than that of Pb-10Sn solder. Thus, the additive fractions of Au and Pd to the Ag₂O paste should be less than 16?vol.% and 7?vol.%, respectively, to avoid compromising the mechanical and electrical properties of the sintered layer relative to those of contemporary Pb-10Sn solder. Following the addition of Au and Pd to the paste, the ion-migration tolerances of the sintered layers were approximately 3 and 2 times higher than that of pure Ag, respectively. Thus, the addition of Au was found to improve the ion-migration tolerance of the sintered Ag layer more effectively and with less sacrifice of the mechanical and electrical properties of the sintered layer than the addition of Pd.     

A metallization scheme for junction-down bonding of high-power semiconductor lasers

High-power semiconductor lasers have found increasing applications in industrial, military, commercial, and consumer products. The thermal management of high-power lasers is critical since the junction temperature rise resulting from large heat fluxes strongly affects the device characteristics, such as wavelength, kink power, threshold current and efficiency, and reliability. The epitaxial-side metallization structure has significant impact on the thermal performance of a junction-down bonded high-power semiconductor laser. In this paper, the influence of the epitaxial-side metal (p-metal) on the thermal behavior of a junction-down mounted GaAs-based high-power single-mode laser is studied using finite-element analysis. It is shown that a metallization structure with thick Au layer can significantly reduce the thermal resistance by distributing the heat flow to wider area laterally, and the thermal resistance of a junction-down bonded laser with thick Au metallization is much less sensitive to the voiding in the die attachment solder interface than a laser with thin Au metallization. A metallization structure of Ti-Pt-thick Au-Ti-Cr-Au is designed and implemented, and the metallurgical stability of this metallization scheme is reported. It was found that, without a diffusion barrier, the thick Au layer in the epi-side metallization would be mostly consumed and form intermetallics with the Sn from the AuSn solder during soldering and thermal aging. The Ti-Pt-thick Au-Ti-Cr-Au metallization scheme prevents the diffusion of Sn into the thick Au layer and preserves the integrity of the metallization system. It is a promising candidate for junction-down bonding of high-power semiconductor lasers for improved thermal management and reliability.     

Fluxless Flip-Chip Solder Joint Fabrication Using Electroplated Sn-Rich Sn–Au Structures

A fluxless flip-chip bonding process in hydrogen environment using newly developed Sn-rich Sn–Au electroplated multilayer solder bumps is presented. Cr/Au dual layer is employed as the plating seed layer and the underbump metallurgy (UBM). This UBM design, seldom used in the electronic industry, is explained in some details. To realize the fluxless possibility, proper intermetallic growth over the composite structure is needed. In this connection, we like to point out that it is much harder to achieve fluxless bonding using Sn-rich Sn–Au design than the familiar Au-rich 80Au20Sn eutectic design. This is so because Sn-rich Sn–Au alloys have numerous Sn atoms on the surface that can get oxidized easily while the Au-Sn eutectic alloy at thermal equilibrium consists of only Au$_5$Sn and AuSn compounds. Intermetallic nucleation and growth mechanism of sequential electroplating of Au over thick Sn layer is studied with scanning electron microscope (SEM), energy dispersive X-ray spectroscopy (EDX), and X-ray diffraction method (XRD). It is found that Au-Sn intermetallic forms as Au is plated over the Sn layer and acts as a barrier that prevents the oxidation of the inner Sn layer, making fluxless possibility a reality. It is found that the SnAu intermetallic compounds are randomly distributed in the Sn rich joint making the joint strong. The resulting joints contain few voids as examined by an SEM and a scanning acoustic microscope (SAM) and have a remelting temperature of 217$^circ$C–222$^circ$C. The plated Sn–Au solder bumps on silicon with 50$mu$m in height are flip-chip bonded to borosilicate glass substrate. This new fluxless flip-chip bonding process is valuable in many applications where the use of flux is prohibited.     

Microstructure evolution of gold-tin eutectic solder on Cu and Ni substrates

The microstructures of the eutectic Au20Sn (wt.%) solder that developed on the Cu and Ni substrates were studied. The Sn/Au/Ni sandwich structure (2.5/3.75/2 μm) and the Sn/Au/Ni sandwich structure (1.83/2.74/5.8 μm) were deposited on Si wafers first. The overall composition of the Au and the Sn layers in these sandwich structures corresponded to the Au20Sn binary eutectic. The microstructures of the Au20Sn solder on the Cu and Ni substrates could be controlled by using different bonding conditions. When the bonding condition was 290°C for 2 min, the microstructure of Au20Sn/Cu and Au20Sn/Ni was a two-phase (Au₅Sn and AuSn) eutectic microstructure. When the bonding condition was 240°C for 2 min, the AuSn/Au₅Sn/Cu and AuSn/Au₅Sn/Ni diffusion couples were subjected to aging at 240°C. The thermal stability of Au20Sn/Ni was better than that of Au20Sn/Cu. Moreover, less Ni was consumed compared to that of Cu. This indicates that Ni is a more effective diffusion barrier material for the Au20Sn solder.     

大功率半导体激光器高可靠烧结技术研究

近几年大功率半导体激光器的应用领域越来越广,许多应用领域都要求半导体激光器能够高可靠性工作.工作焊接质量直接影响着大功率半导体激光器的可靠性,焊接缺陷会导致激光器迅速退化.目前国内普遍采用的铟焊料和锡铅焊料都是软焊料,焊层有形成晶须和热疲劳等可靠性问题.为提高烧结可靠性,采用了金锡焊料烧结激光器新技术.金锡焊料是硬焊料,焊接强度高,抗疲劳性好,对金层无浸蚀现象.通过实验研究掌握了金锡焊料的制备和烧结技术,并与铟焊料、锡铅焊料进行了对比实验.实验结果显示采用金锡焊料烧结激光器可获得更好的性能,是提高半导体激光器可靠性的有效途径.     

Pressure-assisted low-temperature sintering of silver paste as an alternative die-attach solution to solder reflow

Pressure-assisted low-temperature sintering of silver paste is shown to be a viable alternative to solder reflow as a die-attachment solution. A quasihydrostatic pressure is used to lower the sintering temperature. The effect of parameters such as temperature and pressure are investigated. Characterization of the silver-attached samples shows a significant improvement in electrical conductivity, thermal conductivity and mechanical strength of the joint. Given that silver deforms with little accumulation of inelastic strains, and given the absence of large voids in the attachment layer, it is also expected that the joint to be more resistant to fatigue failure than a solder attached junction. Due to the high melting temperature of silver, this alternative process is also suitable for high temperature packages.     

Effects of Solvents in the Polyethylene Glycol Series on the Bonding of Copper Joints Using Ag2O Paste

The effects of reducing solvents on the bonding process using silver oxide paste in a copper joint were investigated. Three solvent types were tested: diethylene glycol (DEG), triethylene glycol (TEG), and polyethylene glycol (PEG). The strength of the joints was assessed by fracturing, which occurred at the interface of the copper oxide layer and the copper substrate in DEG and TEG samples and at the bonded interface in the PEG sample. Analysis of the samples revealed that, in the DEG and TEG samples, the copper substrate was oxidized during the bonding process, which compromised the shear strength of the joints. In contrast, the PEG sample exhibited nonuniform sintering of the silver layer while retaining good shear strength. It was found that the combination of DEG and PEG produced optimum shear strength in the copper joint, as PEG suppressed the growth of copper oxide and DEG promoted the formation of a dense sintered silver layer. The bonding strength achieved was higher than that of the gold-to-gold joint made using standard Pb-5Sn solder.     

Fluxless Wafer Bonding in Vacuum Using Electroplated Sn–Ag Layers

A wafer-to-wafer bonding process using Sn-Ag solder without any flux is successfully developed. This fluxless or flux-free feature makes void-free and uniform bonding layers possible. This is in contrast to the fluxing process employed in nearly all soldering processes adapted in the electronic industry. With the use of flux, the flux or flux residues are easily trapped in the solder joint, resulting in voids and uneven solder layers. This is particularly true if the bonding area is large, such as the entire wafer. Thus, void-free wafer bonding using solders has never been reported. It is thus clear that the key to achieve void-free wafer soldering is to eliminate flux completely. The new fluxless process is performed in a vacuum furnace built in house to inhibit solder oxidation. To prevent oxidation during solder manufacturing, a thin Ag capping layer is plated over the Sn layer right after the Sn layer is plated over an entire 2-in silicon wafer having Cr/Au under bump metallurgy (UBM). This outer Ag layer is critical in preventing the inner Sn layer from oxidation when the wafer is exposed to air. The Si wafer with Cr/Au/Sn/Ag structure is bonded with another Si wafer with Cr/Au at 240degC in the vacuum furnace. To evaluate the joint quality and study the microstructure and composition, scanning acoustic microscopy (SAM), scanning electron microscopy (SEM), and energy dispersive X-ray spectroscopy (EDX) are used. A solder joint with only 1% void area is accomplished. The initial success of this process illustrates that it is indeed possible to bond entire wafers together with a thin metallic joint of high quality. This fluxless bonding technique can be extended to bonding wafers of different materials for new device and packaging applications.     

Ag–Copper Structure for Bonding Large Semiconductor Chips

Ag–copper dual-layer substrate design is presented. The Ag cladding on the copper substrate is a buffer to deal with the large mismatch in coefficient of thermal expansion (CTE) between semiconductors such as Si (3 ppm/$^{circ}$C) and Cu (17 ppm/$^{circ}$ C). Ag is chosen because of its low yield strength, only one-tenth of that of Cu and one-third of the popular Sn3.5Ag solder. Other advantages are high electrical conductivity and high thermal conductivity. To bond Si chips to the Ag layer on copper substrates, Sn-rich solder is used. A fluxless bonding process is designed and developed. The bonding media are Ni/Sn/Au multilayer solder structure plated over Ag. In this design, Ni is a diffusion barrier between Sn and Ag. The thin (100 nm) outer Au layer prevents inner Sn from oxidation. The Si chip is deposited with Cr/Au under bump metallurgy (UBM). The bonding process is performed in 50-mtorr vacuum atmosphere without any flux. Comparing to bonding in air, the oxygen content is reduced by a factor of 15 200. The resulting joints consist of three distinct layers, i.e., Sn-rich layer, Ni$_{3}$ Sn$_{4}$ intermetallic compound, and Ni. Scanning acoustic microscopy (SAM) is used to verify the quality of the joint. Microstructure and composition of the joints are studied using scanning electron microscopy (SEM) with energy dispersive X-ray spectroscopy (EDX). This technique presents an initial success in overcoming the very large mismatch in thermal expansion between silicon and copper. It can be applied to mounting numerous high-power silicon devices to Cu substrate for various applications such as hybrid automotive and high-voltage power networks.      

热界面材料对高功率LED热阻的影响

散热不良是制约大功率LED发展的主要瓶颈之一, 直接影响着大高功率LED器件的寿 命、出光效率和可靠性等。本文采用T3ster热阻测试仪和 ANSYS热学模拟的方法对LED器件进行热学分析,以三种热界面材料(金锡,锡膏,银胶)对LE D热阻及芯片结温的影响为例,分析了热界面材料的热导率、厚度对LED器件热学性能的影响 ,实验结果表明界面热阻在LED器件总热阻中所占比重较大,是影响LED结温高低的主要因素 之一;热学模拟结果表明,界面材料的热导率、厚度及界面材料的有效接触率均会影响到LE D器件结温的变化,所以在LED器件界面互连的设计中,需要综合考虑以上三个关键参数的控 制,以实现散热性能最佳化。     

Characterization of 63Sn37Pb and 80Au2OSn solder sealed opticalfiber feedthroughs subjected to repetitive thermal cycling

A highly accurate prediction of hermeticity lifetime is made for eutectic 63Sn37Pb and 80Au20Sn alloy solder sealed optical fiber-Kovar ^TM nosetube feedthroughs subjected to repetitive thermal cycling. Thermal fatigue fracture of the Sn-Pb solder/Kovar^TM interface develops when cracks, initially generated from creep deformation of the solder, propagate gradually through the junction in the axial direction. A nonlinear axisymmetric finite element analysis of the 63Sn37Pb fiber feedthrough seal is performed using a thermo-elastic creep constitutive equation, and solder joint fatigue based on accumulated strain energy associated with solder creep imposed by temperature cycling is analyzed. Additionally, thermal effective stress and plastic strain is studied for alternative 80Au20Sn solder by the finite element method with results indicating significant increase in useful life as compared to 63Sn37Pb. SEM/EDX metallurgical analysis of the solder/Ni-Au plated Kovar^TM nosetube interface indicates that AuSn₄ intermetallic formed during soldering with 63Sn37Pb also contributes to joint weakening, whereas no brittle intermetallic is observed for 80Au20Sn. Hermetic carbon coated optical fibers metallized with Ni,P-Ni underplate and electrolytic Au overplating exhibit correspondingly similar metallurgy at the solder/fiber interface. Combined hermeticity testing and metallurgical analysis carried out on 63Sn37Pb and 80Au20Sn alloy solder sealed optical fiber feedthroughs after repetitive temperature cycling between -65 and +150°C, and -40 and +125°C validated the analytical approach     

Microstructure, joint strength and failure mechanisms of SnPb and Pb-free solders in BGA packages

The microstructure, joint strength and failure mechanisms of SnPbAg, SnAg and SnAgCu solders on Cu/Ni/Au BGA pad metallization were investigated after multiple reflows or high temperature aging. In the SnPbAg system, a two-layer structure, i.e., Ni/sub 3/Sn/sub 4/ and (Au, Ni)Sn/sub 4/, was formed at the solder-substrate metallization interface after aging at 125, 150, and 175/spl deg/C. However, such structure was not present in the two Pb-free solder systems. Only a layer of Ni/sub 3/Sn/sub 4/ intermetallic compound in the SnAg system and a layer of Cu-Sn-Ni-Au intermetallic compound in the SnAgCu system were found at respective interfaces, even after the two solder systems had been heat treated for 1000 h at the afore-mentioned temperatures. The formation of the (Au, Ni)Sn/sub 4/ ternary compound in the SnPbAg system was due to re-settlement of Au at the interface which led to brittle failure in this system during ball shear testing. In contrast, SnAg and SnAgCu systems failed exclusively inside the solder ball during shear testing after aging at 150/spl deg/C for up to 1000 h. The two Pb-free solder systems showed good resistance to thermal aging with the solder ball shear strength being maintained at 1.60 to 1.70 kgf. The SnPbAg system degraded in mechanical performance with aging time and had strength as low as 1.20 kgf after aging at 150/spl deg/C for 1000 h. The growth rates of intermetallic compound layers at 125, 150, and 175/spl deg/C aging temperatures and the activation energy for the formation of different intermetallic compound layers were also determined in this investigation.     

Microstructural and thermal characterizations of light-emitting diode employing a low-temperature die-bonding material

A Sn/Bi bilayer was deposited on a hot air solder leveling (HASL)-treated metal-core printed circuit board (MCPCB) using electroplating as a low-temperature die-bonding material for light-emitting diode (LED). The eutectic feature of the Sn/Bi contact enabled the die-bonding process to accomplish through a liquid/solid reaction at 185 °C with a proper compression force. A high-temperature die-bonding structure composed of a Bi layer sandwiched by two intermetallic compounds (IMCs) formed after thermocompression. Employment of the Sn/Bi bilayer for low-temperature die-bonding prevented the LEDs from thermal stress problems, and the resulting high-temperature IMC/Bi/IMC die-bonding structure was capable of withstanding multiple bonding reactions and high temperature/current operation environment. Durability tests including mechanical, thermal, and optical performance were systematically performed and compared with other commercially available die-bonding materials (Ag paste and solder alloys).     

Fluxless Bonding of Large Silicon Chips to Ceramic Packages Using Electroplated Eutectic Au/Sn/Au Structures

A fluxless process of bonding large silicon chips to ceramic packages has been developed using a Au-Sn eutectic solder. The solder was initially electroplated in the form of a Au/Sn/Au multilayer structure on a ceramic package and reflowed at 430°C for 10 min to achieve a uniform eutectic 80Au-20Sn composition. A 9 mm × 9 mm silicon chip deposited with Cr/Au dual layers was then bonded to the ceramic package at 320°C for 3 min. The reflow and bonding processes were performed in a 50-mTorr vacuum to suppress oxidation. Therefore, no flux was used. Even without any flux, high-quality joints were produced. Microstructure and composition of the joints were studied using scanning electron microscopy with energy-dispersive x-ray spectro- scopy. Scanning acoustic microscopy was used to verify the joint quality over the entire bonding area. To employ the x-ray diffraction method, samples were made by reflowing the Au/Sn/Au structure plated on a package. This was followed by a bonding process, without a Si chip, so that x-rays could scan the solder surface. Joints exhibited a typical eutectic structure and consisted of (Au,Ni)Sn and (Au,Ni)₅Sn phases. This novel fluxless bonding method can be applied to packaging of a variety of devices on ceramic packages. Its fluxless nature is particularly valuable for packaging devices that cannot be exposed to flux such as sensors, optical devices, medical devices, and laser diodes.     

Effect of silver content on thermal fatigue life of Sn-xAg-0.5Cu flip-chip interconnects

The thermal fatigue properties of Sn-xAg-0.5Cu (x=1, 2, 3, and 4 in mass%) flip-chip interconnects were investigated to study the effect of silver content on thermal fatigue endurance. The solder joints with lower silver context (x=1 and 2) had a greater failure rate compared to those with higher silver content (x=3 and 4) in thermal fatigue testing. Cracks developed in the solders near the solder/chip interface for all joints tested. This crack propagation may be mainly governed by the nature of the solders themselves because the strain-concentrated area was similar for tested alloys independent of the silver content. From the microstructural observation, the fracture was a mixed mode, transgranular and intergranular, independent of the silver content. Higher silver content alloys (x=3 and 4) had finer Sn grains before thermal cycling according to the dispersion of the Ag₃Sn intermetallic compound, and even after the cycling, they suppressed microstructural coarsening, which degrades the fatigue resistance. The fatigue endurance of the solder joints was strongly correlated to the silver content, and solder joints with higher silver content had better fatigue resistance.     

Improvement of thermal management of high-power GaN-based light-emitting diodes

The thermal management of high-power light-emitting-diode (LED) devices employing various die-attach materials is analyzed. Three types of die-attach materials are tested, including silver paste, Sn–3 wt.% Ag–0.5 wt.% Cu (SAC305) solder, and SAC305 solder added with a small amount of carbon nanotubes (CNTs). The analysis of thermal management is performed by comparing the temperatures of the LED chips in use and the total thermal resistances of the LED devices obtained respectively from the thermal infrared images and thermal transient analysis. Due to the high thermal conductivity of CNT, the addition of CNTs into the SAC305 solder reduces the total thermal resistance and chip temperature of the LED device, and the thermal management of the LED devices is improved accordingly.     

Low-Temperature Sintered Nanoscale Silver as a Novel Semiconductor Device-Metallized Substrate Interconnect Material

A nanoscale silver paste containing 30-nm silver particles that can be sintered at 280$^circhboxC$was made for interconnecting semiconductor devices. Sintering of the paste produced a microstructure containing micrometer-size porosity and a relative density of around 80%. Electrical and thermal conductivities of around 2.6$,times 10 ^5~(Omegacdot hboxcm)^-1$and 2.4W/K-cm, respectively, were obtained, which are much higher than those of the solder alloys that are currently used for die attachment and/or flip-chip interconnection of power semiconductor devices. The sintered porous silver had an apparent elastic modulus of about 9GPa, which is substantially lower than that of bulk silver, as well as most solder materials. The lower elastic modulus of the porous silver may be beneficial in achieving a more reliable joint between the device and substrate because of increased compliance that can better accommodate stress arising from thermal expansion mismatch.