Horizontal current bipolar transistor (HCBT): a new concept ofsilicon bipolar transistor technology

A new concept of silicon bipolar transistor technology is proposed. The resulting horizontal current bipolar transistor (HCBT) is simulated assuming the 0.25 μm technology. The surface of the device is smaller than conventional super-self aligned bipolar transistors. The same doping profile as in known vertical current devices is achieved by simpler technology using single polysilicon layer, without conventional epitaxial and n⁺ buried layers and with reduced number of lithography masks and technological steps. The simulated dc and ac characteristics of HCBT are similar to the characteristics of standard SST devices     

A semi-static complementary gain cell technology for sub-1 V supplyDRAM's

A new semi-static complementary gain cell for future low power DRAM's has been proposed and experimentally demonstrated. This gain cell consists of a write-transistor and its opposite conduction type read-transistor with a heating gate as a storage node which causes a shift in the threshold voltage. This gain cell provides a two orders of magnitude larger cell signal output and higher immunity to noise on the bitlines when compared with a conventional one-transistor DRAM cell without increasing the storage capacitance even at a supply voltage of 0.8 V. The 0.87 μm² cell size is achieved by using a 0.25 μm design rule with a polysilicon thin-film transistor built in the trench and phase shifted i-line lithography     

Metal migration into polysilicon emitter after very high currentstress

TEM analyses show metal migration into the polysilicon emitter of a bipolar transistor after high current stress. At the edges of the polysilicon emitter where the current density was expected to be the highest, a metal filament was seen penetrating into the edge of the polysilicon emitter after stressing at a current density of 16.3 mA/μm² for 1.68×10⁵ s at 90°C. The metal penetration into polysilicon offers a possible cause for an electrical measurement reported by D.D. Tang et al. (1990), in which a slight lowering of the emitter contact resistance occurs after the same stress     

Crown-shaped stacked-capacitor cell for 1.5-V operation 64-Mb DRAMs

A self-aligned stacked-capacitor cell called the CROWN cell (a crown-shaped stacked-capacitor cell), used for experimental 64-Mb-DRAMs operated at 1.5 V, has been developed using 0.3-μm electron-beam lithography. This memory cell has an area of 1.28 μm². The word-line pitch and sense-amplifier pitch of this cell are 0.8 and 1.6 μm, respectively. In spite of this small cell area, the CROWN cell has a large capacitor surface area of 3.7 μm² because (1) it has a crown-shaped capacitor electrode, (2) its capacitor is on the data line, and (3) it has a self-aligned memory cell fabrication process and structure. The large capacitor area and a Ta₂O₅ film equivalent to a 2.8-nm SiO₂ film ensure a large storage charge of 33 fC (storage capacitance equals 44 fF) for 1.5-V operation. A small CROWN cell array and a memory test circuit were successfully used to achieve a basic DRAM cell operation     

Design study of AlGaAs/GaAs HBTs

The frequency performance of AlGaAs/GaAs heterojunction bipolar transistors (HBTs) having different layouts, doping profiles, and layer thicknesses was assessed using the BIPOLE computer program. The optimized design of HBTs was studied, and the high current performances of HBTs and polysilicon emitter transistors were compared. It is shown that no current crowding effect occurs at current densities less than 1×10⁵ A/cm² for the HBT with emitter stripe width S_E<3 μm, and the HBT current-handling capability determined by the peak current-gain cutoff frequency is more than twice as large as that of the polysilicon emitter transistor. An optimized maximum oscillation frequency formula has been obtained for a typical process n-p-n AlGaAs/GaAs HBT having base doping of 1×10 ¹⁹ cm^-3     

A high-performance 0.5-μm BiCMOS technology for fast 4-Mb SRAMs

A high-performance 0.5-μm BiCMOS technology has been developed. Three layers of polysilicon are used to achieve a compact four-transistor SRAM bit cell size of less than 20 μm² by creating self-aligned bit-sense and V_ss contacts. A WSi_x polycide emitter n-p-n transistor with an emitter area of 0.8×2.4 μm² provides a peak cutoff frequency (f_T) of 14 GHz with a collector-emitter breakdown voltage (BV_CFO) of 6.5 V. A selectively ion-implanted collector (SIC) is used to compensate the base channeling tail in order to increase f_T and knee current without significantly affecting collector-substrate capacitance. ECL gate delays as fast as 105 ps can be obtained with this process     

High-speed BiCMOS technology with a buried twin well structure

A buried twin well and polysilicon emitter structure is developed for high-speed BiCMOS VLSI's. A bipolar transistor of high cutoff frequency (fT= 4 GHz) and small size (500 µm²) has been fabricated on the same chip with a standard 2-µm CMOS, without degrading the device characteristics of the MOSFET. Latchup immunity is improved due to the low well resistance of the buried layer. The well triggering current is a 0.5-1.0 order of magnitude higher than that of a standard n-well CMOS. To evaluate the utility of this technology, a 15-stage ring oscillator of the 2NAND BiCMOS gate is fabricated. The gate has a 0.71-ns propagation delay time and 0.25-mW power dissipation at 0.85-pF loading capacitance and 4-MHz operation. Drive ability is 0.24 ns/pF, which is 2.5 times larger than that of the equal-area CMOS gate.     

Exponential curvature-compensated BiCMOS bandgap references

An exponential curvature compensation technique for bandgap references (BGR's) which exploits the temperature characteristics of the current gain β of a bipolar transistor is described. This technique requires no additional circuits for the curvature compensation; only a size adjustment of a bias transistor in a conventional first-order compensated BGR is required. Positive and negative versions of the exponential curvature-compensated BGR have been fabricated using a 1.5 μm BiCMOS process. Average temperature coefficients (TC's) of the negative BGR are measured as 2.4 and 6.7 ppm/°C, and those of the positive BGR are measured as 3.5 and 8.9 ppm/°C over the commercial (0~70°C) and military (-55~125°C) temperature ranges, respectively. These circuits dissipate 0.37 mW with a single 5 V supply, and occupy 270×150 μm² and 290×150 μm² , respectively     

A high-speed bipolar technology featuring self-aligned single-polybase and submicrometer emitter contacts

An experimental bipolar transistor structure with self-aligned base-emitter contacts formed using one polysilicon layer is presented with geometries and frequency performance comparable to those of double-polysilicon structures. This structure, called STRIPE (self-aligned trench-isolated polysilicon electrodes), provides a 0.2-μm emitter-base polysilicon contact separation. A 0.4-μm emitter width is achieved with conventional 0.8-μm optical lithography. Scaling of the emitter width of 0.3 μm has been performed with minimal degradation of device performance, and scaling of the emitter width pattern to 0.2 μm has been demonstrated. These dimensions are the smallest achieved in single-polysilicon structures with polysilicon base contacts and are comparable to those achieved in double-polysilicon structures. The STRIPE structure has been used to fabricate transistors with f_t as high as 33.8 GHz     

Improvement of RCA transistor using RTA annealing after theformation of interfacial oxide

A polysilicon emitter RCA transistor (an ultra-thin interfacial oxide layer exists between polysilicon and silicon emitter) is presented which can operate at 77 K for the first time. An ultra-thin (1.5 nm) interfacial oxide layer is grown deliberately between polysilicon and silicon emitter using RCA oxidation and excellent device stability is obtained after rapid thermal annealing (RTA) treatment in nitrogen atmosphere. The RCA transistor exhibits good electrical performance at very low temperature for an emitter area of 3 × 8 μm². The maximum toggle frequency of a 1:2 static divider is 1.2 GHz and 732 MHz at 300 K and 77 K, respectively     

Fully-planar AlGaAs/GaAs HBT's achieved by selective CBE regrowth

This paper describes a novel fully planar AlGaAs/GaAs heterojunction bipolar transistor (HBT) technology using selective chemical beam epitaxy (CBE). Planarization is achieved by a selective regrowth of the base and collector contact layers. This process allows the simultaneous metallization of the emitter, base and collector on top of the device. For the devices with an emitter-base junction area of 2×6 μm² and a base-collector junction area of 14×6 μm², a current gain cut off frequency of 50 GHz and a maximum oscillation frequency of 30 GHz are achieved. The common emitter current gain h_FE is 25 for a collector current density J_c of 2×10⁴ A/cm²     

Memory array architecture and decoding scheme for 3 V only sectorerasable DINOR flash memory

A memory array architecture and row decoding scheme for a 3 V only DINOR (divided bit line NOR) flash memory has been designed. A new sector organization realizes one word line driver per two word lines, which is conformable to tight word line pitch. A hierarchical negative voltage switching row decoder and a compact source line driver have been developed for 1 K byte sector erase without increasing the chip size. A bit-by-bit programming control and a low threshold voltage detection circuit provide a high speed random access time at low V_cc and a narrow program threshold voltage distribution. A 4 Mb DINOR flash memory test device was fabricated from 0.5 μm, double-layer metal, triple polysilicon, triple well CMOS process. The cell measures 1.8×1.6 μm² and the chip measures 5.8×5.0 mm ². The divided bit line structure realizes a small NOR type memory cell     

Advanced TFT SRAM cell technology using a phase-shift lithography

An advanced TFT memory cell technology has been developed for making high-density and high-speed SRAM cells. The cell is fabricated using a phase-shift lithography that enables patterns with spaces of less than 0.25 μm to be made using the conventional stepper. Cell area is also reduced by using a small cell-ratio and a parallel layout for the transistor. Despite the small cell-ratio, stable operation is assured by using advanced polysilicon PMOS TFT's for load devices. The effect of the Si₃N₄ multilayer gate insulator on the on-current and the influence of the channel implantation are also investigated. To obtain stable operation and extremely low stand-by power dissipation, a self-aligned offset structure for the polysilicon PMOS TFT is proposed and demonstrated. A leakage current of only 2 fA/cell and an on-/off-current ratio of 4.6×10⁶ are achieved with this polysilicon PMOS TFT in a memory cell, which is demonstrated in a experimental 1-Mbit CMOS SRAM chip that has an access time of only 7 ns     

A 210-GHz fT SiGe HBT with a non-self-aligned structure

A record 210-GHz f_T SiGe heterojunction bipolar transistor at a collector current density of 6-9 mA/μm² is fabricated with a new nonself-aligned (NSA) structure based on 0.18 μm technology. This NSA structure has a low-complexity emitter and extrinsic base process which reduces overall thermal cycle and minimizes transient enhanced diffusion. A low-power performance has been achieved which requires only 1 mA collector current to reach 200-GHz f_T. The performance is a result of narrow base width and reduced parasitics in the device. Detailed comparison is made to a 120-GHz self-aligned production device     

Heterojunction bipolar transistor utilising AlGaSb/GaSb alloysystem

A heterojunction bipolar transistor (HBT) has been fabricated using the AlGaSb/GaSb material system for the first time. The HBT structure of 100×100 μm² emitter size was made by mesa-etching the molecular-beam-epitaxially grown layers. The device exhibits a current gain as high as 160 at room temperature     

Extremely high peak specific transconductance AlGaAs/GaAsheterojunction bipolar transistors

Self-aligned AlGaAs/GAs heterojunction bipolar transistors with peak specific transconductances as high as 25 mS/μm² of emitter area are discussed. These are the highest specific transconductances ever reported for a bipolar transistor. These devices, which contain no indium in the emitter, display specific parasitic emitter resistances of less than 1×10^-7 Ω-cm². This low parasitic resistance is attributed to an improved n-type contact technology, in which a molybdenum diffusion barrier and a plasma-enhanced chemical vapor deposition SiO₂ overlayer are used to achieve low specific contact resistivities     

A very small bipolar transistor technology with sidewall polycidebase electrode for ECL-CMOS LSIs

Very small, high-performance, silicon bipolar transistors (SPOTEC) are developed for use in ECL-CMOS LSIs. The transistors are fabricated with a sidewall polycide base; chemical vapor deposition is used to selectively deposit tungsten on the sidewall surface of the polysilicon base. The tungsten is then silicided. This self-aligned polycide technology makes a narrow (0.4-μm wide), low-resistance (7 Ω/□) base electrode possible. Narrow U-groove isolation and narrow collector metallization techniques are used to reduce the transistor area to 10 μm². A shallow E-B junction and base layer have now been formed by using rapid-vapor-phase doping. The resulting transistors have good I-V characteristics without leakage current or high current gain. They have a high cut-off frequency of 37 GHz (53 GHz with pedestal collector ion implantation and thin epitaxial layer) and small junction capacitances. These transistors facilitate the development of very-high-speed, high-density ULSIs     

Spread-vertical-capacitor cell (SVC) for high-density dRAM's

An advanced three-dimensionally (3-D) stacked-capacitor cell, the spread-vertical-capacitor cell (SVC), was developed. SVC realized a storage capacitance (C_s) of 30 fF with a cell area of 1.8 μm², a capacitor height of 0.37 μm, and an equivalent SiO₂ film thickness of 7 nm for oxide-nitride-oxide (ONO). By extrapolating these results to 256-Mb DRAMs, a C_s of 24 fF is obtained with a cell area of 0.5 μm², a capacitor height of 0.4 μm, and an equivalent SiO₂ thickness of 5 nm, and these values satisfy the specifications for 256-Mb DRAMs. The low capacitor height of SVC makes possible a fabrication process using ArF excimer laser lithography     

Dramatic increases in latchup holding voltage for sub-0.5 μmCMOS using shallow S/D junctions

Large increases in the latchup holding voltage are demonstrated with the use of shallow source-drain junctions in a sub-0.5 μm CMOS process. Holding voltages well above the supply voltage for 2 μm n ⁺/p⁺ spacings are demonstrated without the use of complex processes such as retrograde wells or buried layers. SIMS data is presented to verify the reduction in junction depths to 0.15 μm for the p⁺/n-well and 0.14 μm for the n⁺/p-well junction. The improvement in holding voltage is attributed to reductions in parasitic bipolar transistor gains, due to the increase in base width. Well behaved transistor characteristics are presented using the shallow junction technology     

High-frequency submicrometerAl0.48In0.52As/In0.53Ga0.47As heterostructure bipolar transistors

The high speed scaling of an Al_0.48In_0.52As/In_0.53Ga_0.47 As submicrometer heterostructure bipolar transistor (HBT) is presented. Transistors with emitter dimensions of 0.5×11 and 3.5×3.5 μm² exhibit unity current-gain cutoff frequencies of 63 and 70 GHz, respectively. Emitter current density greater than 3.3×10⁵ A/cm² is demonstrated in a submicrometer AlInAs/InGaAs HBT. The analysis shows that the device speed is limited by the parasitic collector charging time