Particle deposition and removal in wet cleaning processes for ULSImanufacturing

Particle deposition on wafer surfaces in solutions can be described by the well-documented principles of colloid science. Particle concentration, solution pH, and ionic strength in solutions are all important factors which determine the number of particles which deposit on wafer surfaces immersed in liquids. maximum particle deposition is observed in high ionic strength acidic solutions and is reduced as solution pH increase. Particle removal efficiencies in various solutions were also investigated; NH₄OH-H₂O₂-H ₂O solutions were optimized in NH₄OH content around the ratio of 0.05:1.15 (0.05 part NH₄OH, 1 part H₂O₂, 5 parts H₂O). Wafer damage as measured by surface micro-roughness was not increased during NH₄ OH-H₂O₂-H₂O treatment using this ratio     

Particle-free wafer cleaning and drying technology

It is reported that an NH₄OH-H₂O₂ solution is excellent for removing particulate contaminants from VLSI silicon wafers after chemical solution treatment. The ratio of NH₄ OH in the solution can be reduced down to 1/10 of the standard ratio while keeping high removal efficiency. By decreasing the NH₄ OH content, wafer damage which appears as a so-called haze during the NH₄OH-H₂O₂ treatment is reduced. To establish a particle-free wafer drying system, a particle-generation-free isopropanol (IPA) vapor drying system has been developed. By eliminating all possible particle generation sources from the drying system, ultraclean wafer drying equipment has been realized. A number of parameters to be controlled have been thoroughly investigated. Three were found to seriously influence surface cleanliness after drying: the water content in the IPA, temperature distribution around the wafers, and the IPA vapor velocity. The optimum drying conditions in which high quality of wafer surface cleanliness can be realized were confirmed experimentally     

Novel cleaning solutions for polysilicon film post chemicalmechanical polishing

Novel cleaning solutions were developed for post-CMP process, surfactant tetra methyl ammonium hydroxide (TMAH) and/or chelating agent ethylene diamine tetra acetic acid (EDTA) were added into the diluted ammonium hydroxide (NH₄OH+H₂O) alkaline aqueous solution to enhance removal of metallic and organic contamination. From the experimental result, it is found that the particle and metal removal efficiency and the electrical characteristics are significantly improved for post-CMP cleaning     

Influence of initial wafer cleanliness on metal removal efficiencyin immersion SC-1 cleaning: limitation of immersion-type wet cleaning

When contaminated silicon wafers are immersed in an ultra-pure cleaning solution of an NH₄OH/H₂O₂/H ₂O mixture known as the RCA Standard Clean 1 (SC-1), in which the impurity concentration is negligibly low, the level of wafer-surface metallic contamination after the cleaning treatment depends on the amount of metallic impurities brought into the solution by the to-be-cleaned wafers themselves. Even if the chemicals are disposed of after each wafer cleaning, the surface metallic contamination is still dominated by the amount of impurities brought into the fresh solution by the wafers themselves. In the past, purer chemicals have been sought to improve metal removal efficiency, but after reasonably purer chemicals are obtained the efficiency is not governed by the initial chemical purity but by the initial wafer cleanliness. Because of this, scrubbing of dirty wafers-both the backand front-surfaces-before immersion-type wet cleaning is recommended. However, to meet future stricter wafer cleanliness requirements, new cleaning methods in which fresh chemicals are continuously supplied, such as single-wafer spin cleaning, will have to be employed     

Dependence of electron channel mobility on Si-SiO2interface microroughness

The effect of the Si-SiO₂ interface microroughness on the electron channel mobility of n-MOSFETs was investigated. The surface microroughness was controlled by changing the mixing ratio of NH₄ OH in the NH₄OH-H₂O₂-H₂O solution in the RCA cleaning procedure. The gate oxide was etched, following the evaluation of the electrical characteristics of MOS transistors, to measure the microroughness of the Si-SiO₂ interface with scanning tunneling microscopy (STM). As the interface microroughness increases, the electron channel mobility, which can be obtained from the current-voltage characteristics of the MOSFET, gets lower. The channel mobility is around 360 cm²/V-s when the average interface microroughness is 0.2 nm, where the substrate impurity concentration is 4.5×10¹⁷ cm^-3, i.e. the electron bulk mobility is 400 cm²/V-s. It goes down to 100 cm²/V-s when the interface microroughness exceeds 1 nm     

Development of an etchant for selectively etching TiWNxin the presence of electroplated 95%Pb-5%Sn solder

Shrinking die sizes and increasing I/O density is motivating the push toward flip chip packages. A flip chip interconnection system with a under bump metallurgy stack containing sputtered TiWN_X/sputtered Cu/electroplated Cu stud/electroplated 95%Pb-5%Sn was developed. An important step in the above process is the selective etching of the sputtered Cu bus layer and the TiWN_X barrier layer, in the presence of the Pb-Sn solder. The Cu bus layer was selectively etched using commercial etchants. However, no commercial etchants were available for selectively etching the TiWN_X layer, H₂O₂-NH₄OH based etching systems, popularly known as Standard Clean-1 cleaning solutions, have been extensively used to clean silicon wafers in front end wafer fabrication where only trace metal contamination exists. Since metals like lead, copper, titanium, tin and tungsten catalyze the heterogeneous decomposition of the peroxide, the unstable H₂O₂-NH₄OH based etching systems are rarely used to etch metal films. In this paper the development of a H ₂O₂-NH₄OH based etchant to selectively etch the sputtered TiWN_X films in the presence of electroplated 95%Pb-5%Sn solder bumps is discussed. A 2³ full factorial experiment with mid point was conducted to establish the etchant composition, as well as process temperature, that give satisfactory responses with respect to etch time, permissable undercut of the Cu stud (caused by the NH₄OH), and acceptable bump shape after reflow. Statistical analysis was used to understand the significant factors influencing the etch rate and undercut. An etchant containing 6% by volume of 30%-H₂O₂ and 0.75% by volume of 30%-NH₄OH operated at a temperature of 37°C was found to give satisfactory results     

Dependence of thin-oxide films quality on surface microroughness

The effects of silicon surface microroughness on electrical properties of thin-oxide films, such as breakdown electric field intensity (E_BD) and time-dependent dielectric breakdown (Q_BD), have been studied, where the microroughnesses of silicon and silicon dioxide surfaces are evaluated by the scanning tunneling microscope (STM) and the atomic force microscope (AFM), respectively. An increase of surface microroughness has been confirmed to severely degrade the E_BD and Q_BD characteristics of thin-oxide films with thicknesses of 8-10 nm and to simultaneously decrease channel electron mobility. An increase of surface microroughness has been demonstrated to originate mainly from wet chemical cleaning processing based on the RCA cleaning concept, particularly the ammonium-hydrogen-peroxide cleaning step. In order to keep the surface microroughness at an initial level, the content ratio of NH₄OH/H₂O₂/H₂ O solution has been set at 0.05:1:5 and the room-temperature DI water rinsing has been introduced right after the NH₄OH/H₂O₂/H₂O cleaning step in conventional RCA cleaning procedure     

Control of cleaning performance of an ammonia and hydrogen peroxidemixture (APM) on the basis of a kinetic reaction model

Ammonia and hydrogen peroxide mixtures (APM) are widely used for removing particles from substrate surfaces in semiconductor manufacturing. In the next-generation manufacturing, more precise control of the APM cleaning performance is required than what is available today. In this study, a new method for evaluating the APM cleaning performance, such as the etching rate, surface microroughness, and particle removal efficiency, was introduced based on a chemical equilibrium analysis of APM and a kinetic reaction model of a Si substrate with APM. It became clear that the etching reaction of a Si substrate proceeds along two paths (path-1, path-2) in APM. In path-1, the Si surface is oxidized by HO₂^- and then the SiO₂ layer is etched by OH^-. In path-2, the Si surface is directly etched by OH^-. Path-1 is favorable for APM cleaning because path-2 causes some problems, such as too fast etching, an increase in surface microroughness, and a decrease in particle removal efficiency. Using the contribution ratio of each path to total etching reaction, we can predict the etching rate and determine optimum APM cleaning conditions (NH₃ concentration, H₂ O₂ concentration, temperature). This method makes it possible to improve the APM cleaning performance and to decrease chemical consumption     

多结化合物电池用p型Ge抛光片清洗技术研究

对多结化合物太阳电池用的p型Ge抛光片的清洗技术做了研究.Ge抛光片的清洗可以采用酸性清洗液和碱性清洗液相结合的方式.酸性清洗液的主要作用是去除晶片表面的有机物;碱性清洗液的主要作用是去除晶片表面的颗粒.清洗液的温度和组分影响着抛光片的清洗效果.通过实验结果确定了p型Ge抛光片的清洗方案,采用这一清洗方案清洗的Ge抛光片,表面质量可以达到"开盒即用"的水平.运用晶片清洗机理分析了各种清洗液的功能和作用.     

Fracture origins of optical fibers fabricated by hybridized process

Fracture origins of single-mode optical fibers that were produced by the CIP hybridized process consisting of overcladding a VAD-derived core rod with silica glass made from commercial silica powder were studied. It was found that there were many inclusions that caused failure of the fiber at the screening test. To identify the inclusions, the EPMA technique was successfully used and new internal defects such as a Cr, a Cr-Fe, and a Zr inclusions were found. By investigating the manufacturing process precisely, stainless steel particles and Cr₂ O₃ particles in the silica powder were found to become origins of the fractures. Further, the removal of Cr₂O₃ particles by the reaction with chlorine gas at high temperature was studied, and its dependence on the reaction temperature and on the chlorine content was clarified. It was also suggested that the initial particle size of a Cr₂O₃ particle was an important factor for its elimination. The results obtained by this study should be used to remove both the Cr and the Cr-Fe inclusions     

Wafer reuse for repeated growth of III–V solar cells

The epitaxial lift‐off (ELO) technique can be used to separate a III–V solar cell structure from its underlying GaAs or Ge substrate. ELO from 4‐inch Ge wafers is shown and 2‐inch GaAs wafer reuse after lift‐off is demonstrated without degradation in performance of the subsequent thin‐film GaAs solar cells that were retrieved from it. Since a basic wet chemical smoothing etch procedure appeared insufficient to remove all the surface contamination, wafer re‐preparation is done by a chemo‐mechanical polishing procedure. Copyright © 2010 John Wiley & Sons, Ltd.     

非离子型表面活性剂结合金刚石膜电化学氧化的新型抛光后晶片清洗工艺

本文针对抛光后晶片的颗粒和有机污染物提出了一种新型清洗方法,它结合了非离子表面活性剂和掺硼金刚石膜（BDD）阳极电化学氧化的优势。非离子表面活性剂可以在抛光后晶片上形成一层保护膜,使晶片表面颗粒易于去除。颗粒去除对比实验结果通过金相显微镜观察得知,体积比为1%的非离子表面活性剂的颗粒去除效果最佳。然而表面活性剂保护膜本身属于有机物,它最终也需要被去除。金刚石膜阳极电化学氧化（BDD-EO）可以用来去除有机物,因为它可以有效降解有机物。三个有机污染物去除对比实验分别为：一是先用非离子表面活性剂再用BDD-EO,二是单纯用BDD-EO去除有机物,第三种是用传统RCA清洗技术。通过XPS检测结果表明,用BDD-EO清洗的晶片表面的有机残留明显少于传统RCA技术,并且晶片表面的非离子表面活性剂也可以有效去除。     

A new cleaning process combining non-ionic surfactant with diamond film electrochemical oxidation for polished silicon wafers

This paper presents a new cleaning process for particle and organic contaminants on polished silicon wafer surfaces.It combines a non-ionic surfactant with boron-doped diamond(BDD) film anode electrochemical oxidation. The non-ionic surfactant is used to remove particles on the polished wafer's surface,because it can form a protective film on the surface,which makes particles easy to remove.The effects of particle removal comparative experiments were observed by metallographic microscopy,which showed tha...     

Highly reliable, high-C DRAM storage capacitors with CVD TA2O5 films on rugged polysilicon

The authors report on a highly reliable stacked storage capacitor with ultrahigh capacitance using rapid-thermal-annealed low-pressure chemical vapor deposited (LPCVD) Ta₂O₅ films (~100 Å) deposited on NH₃-nitrided rugged poly-Si electrodes. Capacitances as high as 20.4 fF/μ² (corresponding to the thinnest t_ox.eff (16.9 Å) ever reported using LPCVD-Ta₂O₅ and poly-Si technologies) have been achieved with excellent leakage current and time-dependent dielectric breakdown (TDDB) characteristics. Extensive electrical characterization over a wide temperature range (~25-300°C) shows that Ta₂O ₅ films on rugged poly-Si electrodes have a better temperature stability in dielectric leakage and breakdown compared to the films on smooth poly-Si electrodes     

粘着力对化学机械抛光芯片分子去除机理影响的数学模型

基于芯片/磨粒/抛光垫的微观接触力平衡关系,建立了考虑抛光垫/磨粒大变形和粘着力效应的微观接触模型,模型预测结果表明：对于Cu和SiO2芯片而言,粘着力对磨粒所受外力具有重要影响作用;考虑粘着力的情况下,单个磨粒压入芯片的深度比未考虑粘着效应时,最大为原来的2倍和4倍。然而,即使考虑粘着效应时,磨粒压入芯片的深度仍然在分子量级。因此,认为CMP材料的去除机理为单分子层去除机理,为深入研究CMP材料原子/分子去除机理提供了一定的理论指导。     

InAlAs/InGaAs/InP MODFET's with uniform threshold voltage obtainedby selective wet gate recess

Excellent uniformity in the threshold voltage, transconductance, and current-gain cutoff frequency of InAlAs/InGaAs/InP MODFETs has been achieved using a selective wet gate recess process. An etch rate ratio of 25 was achieved for InGaAs over InAlAs using a 1:1 citric acid:H₂O₂ solution. By using this solution for gate recessing, the authors have achieved a threshold voltage standard deviation of 15 mV and a transconductance standard deviation of 15 mS/mm for devices across a quarter of a 2-in-diameter wafer. The average threshold voltage, transconductance, and current-gain cutoff frequency of 1.0-μm gate-length devices were -234 mV, 355 mS/mm, and 32 GHz, respectively     

Requirements for contamination control in the gigabit era

The effect of contamination, especially particles and organic materials in cleanrooms, on future device manufacturing was estimated. The number of particles deposited on wafer surfaces was calculated based on particle size distribution in real cleanrooms and the reported data on particle deposition velocity. DRAM yield trend was then calculated taking only particles from the cleanroom environment into account. Killer particle size is assumed to be one-third of the feature size according to the SIA roadmap. In the Gigabit era, a class 0.1-0.01 level environment will be necessary even with a shortened TAT (turn around time). The lower limit of particle density in conventional cleanroom air was estimated to be class 0.1-1 Level by particle generation by people, suggesting the use of a mini-environment fab system to produce high-grade cleanliness. A mini-environment system is also preferable for eliminating other contaminants such as organic compounds. However, box material and additions must be reexamined from the viewpoint of organic contamination control because some organic materials generated from wafer box easily adsorb on silicon surfaces and change the surface conditions     

Influence of slurry components on uniformity in copper chemical mechanical planarization

Many researchers studying copper chemical mechanical planarization (CMP) have been focused on mechanisms of copper removal using various chemicals. On the basis of these previous works, we studied the effect of slurry components on uniformity. Chemical mechanical planarization of copper was performed using citric acid (C₆H₈O₇), hydrogen peroxide (H₂O₂), colloidal silica, and benzotriazole (BTA, C₆H₄N₃H) as a complexing agent, an oxidizer, an abrasive, and a corrosion inhibitor, respectively. As citric acid was added to copper CMP slurry (pH 4) containing 3 vol% hydrogen peroxide and 3 wt% colloidal silica, the material removal (MRR) at the wafer center was higher than its edge. Hydrogen peroxide could not induce a remarkable change in the profile of MRR. Colloidal silica, used as an abrasive in copper CMP slurry containing 0.01 M of citric acid and 3 vol% of hydrogen peroxide, controlled the profile of MRR by abrading the wafer edge. BTA as a corrosion inhibitor decreased the MRR and seems to control the material removal around the wafer center. All the results of in this study showed that the MRR profile of copper CMP could be controlled by the contents of slurry components.     

有机胺碱对硅通孔铜膜化学机械抛光的影响

有机胺碱可与铜离子反应且产物在碱性条件下溶于水,这为硅通孔(TSV)铜膜的碱性化学机械抛光(CMP)提供了有利条件.研究了大分子有机胺碱对铜膜化学机械抛光的影响.首先测试了不同体积分数有机胺碱对碱性抛光液中磨料粒径和Zeta电位的影响,然后在直径3英寸(1英寸=2.54 cm)铜片上模拟了不同体积分数有机胺碱对铜去除速率的影响.实验结果表明:有机胺碱对抛光液中磨料粒径和Zeta电位没有影响;随着有机胺碱体积分数的增加,铜的去除速率先快速增加,达到一峰值后趋于稳定,最后略有下降;当有机胺碱的体积分数为5％时,TSV图形片铜膜去除速率达到最高值2.1tμm/min,剩余铜膜总厚度差减小到1.321 76 nm,实现了纳米级的化学机械抛光.     

Measurement and control of a residual oxide layer on TiSi2 films employed in ohmic contact structures

An inadvertent oxide layer is formed on a titanium disilicide (TiSi₂) film following various wet and dry processes in a manufacturing environment. The use of H₂SO₄:H₂O₂:H₂O (1:1:5) as a wet etch for excess Ti metal, prior to the high temperature anneal used to form a subsequent TiSi₂ layer, is identified as the source of the undesired oxide via multiwavelength spectroscopic ellipsometry and Auger electron spectrometry studies. This inadvertent oxide layer on TiSi₂ is shown to form bad electrical contacts and is a contributing source to large standby currents in polysilicon gate shunts. Spectroscopic ellipsometry is shown herein as a unique analytical tool to determine both the thickness and structure of this poorly structured oxide during process development. A single wavelength ellipsometer monitoring scheme for both the appearance as well as the thickness of this inadvertent oxide layer is proposed for use in high-volume manufacturing