Test generation for specification test of analog circuits using efficient test response observation methods

In this paper, a new automated test generation methodology for specification testing of analog circuits using test point selection and efficient analog test response waveform capture methods for enhancing the test accuracy is proposed. The proposed approach co-optimizes the construction of a multi-tone sinusoidal test stimulus and the selection of the best set of test response observation points. For embedded analog circuits, it uses a subsampling-based digitization method compatible with IEEE 1149.1 to accurately digitize the analog test response waveforms. The proposed specification approach uses ‘alternate test’ framework, in which the specifications of the analog circuit-under-test are computed (predicted) using statistical regression models that are constructed based on process variations and corresponding variations of test responses captured from different test observation points. The test generation process and the test point selection process aim to maximize the accuracy of specification prediction. Experimental results validating the proposed specification test approach are presented.     

Test infrastructure design for mixed-signal SOCs with wrapped analog cores

Many system-on-chips (SOCs) today contain both digital- and analog-embedded cores. Even though the test cost for such mixed-signal SOCs is significantly higher than that for digital SOCs, most prior research in this area has focused exclusively on digital cores. We propose a low-cost test development methodology for mixed-signal SOCs that allows the analog and digital cores to be tested in a unified manner, thereby minimizing the overall test cost. The analog cores in the SOC are wrapped such that they can be accessed using a digital test access mechanism (TAM). We evaluate the impact of the use of analog test wrappers on area overhead and test time. To reduce area overhead, we present an analog test wrapper optimization technique, which is then combined with TAM optimization in a cost-oriented heuristic approach for test scheduling. We also demonstrate the feasibility of using analog wrappers by presenting transistor-level simulations for an analog wrapper and a representative core. We present experimental results for three SOCs from the ITC '02 test benchmarks that have been augmented with three analog cores: an I-Q transmit path pair and an audio CODEC path used in cellular phone applications.     

Analysis of Test Application Time for Test Data Compression Methods Based on Compression Codes

We present an analysis of test application time for test data compression techniques that are used for reducing test data volume and testing time in system-on-a-chip (SOC) designs. These techniques are based on data compression codes and on-chip decompression. The compression/decompression scheme decreases test data volume and the amount of data that has to be transported from the tester to the SOC. We show via analysis as well as through experiments that the proposed scheme reduces testing time and allows the use of a slower tester. Results on test application time for the ISCAS'89 circuits are obtained using an ATE testbench developed in VHDL to emulate ATE functionality.     

Test of a switched-capacitor ADC by a built-in charge sensor

A test methodology for switched capacitor circuits is described. The test approach uses a built-in sensor to analyze the charge transfer inside the circuit under test (CUT). The test methodology is applied to a 10-bit algorithmic analog to digital converter to obtain the static linearity and to the simulated fault coverage figures taking into account a catastrophic fault model. The goodness of the charge sensor has been experimentally evaluated with an SC integrator for fault detection and built-in sensor influence on the CUT performance.     

Statistical Tolerance Analysis for Assured Analog Test Coverage

Increasing numbers of analog components in today's systems necessitate system level test composition methods that utilize on-chip capabilities rather than solely relying on costly DFT approaches. We outline a tolerance analysis methodology for test signal propagation to be utilized in hierarchical test generation for analog circuits. A detailed justification of this proposed novel tolerance analysis methodology is undertaken by comparing our results with detailed SPICE Monte-Carlo simulation data on several combinations of analog modules. The results of our experiments confirm the high accuracy and efficiency of the proposed tolerance analysis methodology.     

Automated System-Level Test Development for Mixed-Signal Circuits

While in the digital domain, test development is primarily conducted with the use of automated tools, knowledge-based, ad hoc test methods have been in use in the analog domain. High levels of design integration and increasing complexity of analog blocks within a system necessitate automated system-level analog test development tools. We outline a methodology for specification-based automated test generation and fault simulation for analog circuits. Test generation is targeted at providing the highest coverage for each specified parameter. The flexibility of assigning analog test attributes is utilized for merging tests leading to test time reduction with no loss in test coverage. Further optimization in test time is obtained through fault simulations by selecting tests that provide adequate coverage in terms of several components and dropping the ones that do not provide additional coverage. A system-level test set target in the given set of specifications, along with fault and yield coverages in terms of each targeted parameter, and testability problems are determined through the proposed methodology.     

Test Generation for Mixed-Signal Devices Using Signal Flow Graphs

We describe a new reverse simulation approach to analog and mixed-signal circuit test generation that parallels digital test generation. We invert the analog circuit signal flow graph, reverse simulate it with good and bad machine outputs, and obtain test waveforms and component tolerances, given circuit output tolerances specified by the functional test needs of the designer. The inverted graph allows backtracing to justify analog outputs with analog input sinusoids. Mixed-signal circuits can be tested using this approach, and we present test generation results for two mixed-signal circuits and four analog circuits, one being a multiple-input, multiple-output circuit. This analog backtrace method can generate tests for second-order analog circuits and certain non-linear circuits. These cannot be handled by existing methods, which lack a fault model and a backtrace method. Our proposed method also defines the necessary tolerances on circuit structural components, in order to keep the output circuit signal within the envelope specified by the designer. This avoids the problem of overspecifying analog circuit component tolerances, and reduces cost. We prove that our parametric fault tests also detect all catastrophic faults. Unlike prior methods, ours is a structural, rather than functional, analog test generation method.     

On Using Exponential-Golomb Codes and Subexponential Codes for System-on-a-Chip Test Data Compression

We examine the use of exponential-Golomb codes and subexponential codes can be used for the compression of scan test data in core-based system-on-a-chip (SOC) designs. These codes are well-known in the data compression domain but their application to SOC testing has not been explored before. We show that these codes often provide slighly higher compression than alternative methods that have been proposed recently.     

SOC芯片并行测试中几个值得关注的问题

介绍了提高测试效率的SOC芯片在片测试的两种并行测试方法,结合上海集成电路技术与产业促进中心的多个实际的SOC芯片测试项目中所积累的成功经验,针对多工位测试和多测试项目平行测试这两种并行测试方法,主要阐述了在SOC芯片的并行测试中经常遇到的影响测试系统和测试方法的问题,提出了在SOC芯片在片测试中的直流参数测试、功能测试、模数/数模转换器(ADC/DAC)测试的影响因素和解决方案,并对SOC芯片在测试过程中经常遇到的干扰因素进行分析,尽可能保证SOC芯片在片测试获得的各项性能参数精确、可靠.     

A Statistical Sampler for a New On-Line Analog Test Method

This work shows a new strategy to the on-line test of analog circuits. The technique presents a very low analog overhead and it is completely digital. In the System-on-Chip (SoC) environment the on-line test can be developed by using processing power already available in the system. As all the signal processing is done in the digital domain, it allows use of a purely digital tester or a digital BIST technique. The main principle of operation is based on the observation of statistical properties of the circuit under test. Since it has low analog power and performance overhead, the proposed technique can be used to analyze the output of several stages of complex analog systems without the use of switches or analog multiplexors for reconfiguration, and no additional AD converter is needed. This paper presents the fundamentals of the proposed test method and some experimental results illustrating the operation of the Statistical Sampler concerning linear analog systems.     

Enhancement of test data compression with multistage encoding

In this paper, we present two multistage compression techniques to reduce the test data volume in scan test applications. We have proposed two encoding schemes namely alternating frequency-directed equal-run-length (AFDER) coding and run-length based Huffman coding (RLHC). These encoding schemes together with the nine-coded compression technique enhance the test data compression ratio. In the first stage, the pre-generated test cubes with unspecified bits are encoded using the nine-coded compression scheme. Later, the proposed encoding schemes exploit the properties of compressed data to enhance the test data compression. This multistage compression is effective especially when the percentage of do not cares in a test set is very high. We also present the simple decoder architecture to decode the original data. The experimental results obtained from ISCAS'89 benchmark circuits confirm the average compression ratio of 74.2% and 77.5% with the proposed 9C-AFDER and 9C-RLHC schemes respectively.     

Capture-power-aware test data compression using selective encoding

Ever-increasing test data volume and excessive test power are two of the main concerns of VLSI testing. The “don’t-care” bits (also known as X-bits) in given test cube can be exploited for test data compression and/or test power reduction, and these techniques may contradict to each other because the very same X-bits are likely to be used for different optimization objectives. This paper proposes a capture-power-aware test compression scheme that is able to keep capture-power under a safe limit with low test compression ratio loss. Experimental results on benchmark circuits validate the effectiveness of the proposed solution.     

A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores

We have introduced a low-cost at-speed BIST architecture that enables conventional microprocessors and DSP cores to test their functional blocks and embedded SRAMs in system-on-a-chip architectures using their existing hardware and software resources. To accommodate our proposed new test methodology, minor modifications should be applied to base processor within its test phase. That is, we modify the controller to interpret some of the instructions differently only within the initial test mode. In this paper, we have proposed a fuctional self-test methodology that is deterministic in nature. In our proposed architecture, a self test program called BIST Program is stored in an embedded ROM as a vehicle for applying tests. We first start with testing processor core using our proposed architedture. Once the testing of the processor core is completed, this core is used to test the embedded SRAMs. A test algorithm which utilizes a mixture of existing memory testing techniques and covers all important memory faults is presented in this paper. The proposed memory test algorithm covers 100% of the faults under the fault model plus a data retention test. The hardware overhead in the proposed architecture is shown to be negligible. This architecture is implemented on UTS-DSP (University of Tehran and Iran Communicaton Industries (SAMA)) IC which has been designed in VLSI Circuits and Systems Laboratory.     

Selecting measurements to test the functional behavior of analog circuits

This paper presents a method for functional testing of analog circuits, on the basis of circuit sensitivities. The approach selects the minimum number of measurements that allows a precise prediction of a circuit's functional behavior. A criterion is applied to this predicted behavior to determine if the circuit functions according to specifications. The presented method combines a matrix decomposition technique (the singular value decomposition) with an iterative algorithm to select measurements. The number of measurements is determined on the basis of the desired precision of the response prediction and the influence of random measurement errors. Examples demonstrate that the resulting method tests the functional circuit behavior with a high precision, even in the presence of large measurement errors.     

Testing of RF mixers with adaptive filters

This work describes a technique for testing RF mixers with digital adaptive filters. RF circuits are widely used on data transmission applications, such as wireless communication, radio and portable phone systems. However, traditional analog testing covers mainly linear circuits, being not suitable to non-linear pieces of hardware like analog mixers. Herein, an adaptive non-linear filter is trained so that it can mimic the behavior of a RF mixer. Then, a test stimulus is simultaneously applied to the filter and the mixer and the outputs of both circuits are compared to check whether the circuit under test is faulty or fault free. A prototype of a mixer was built in order to allow fault injection in the circuit under test. Thus, the detection capability of the proposed technique could be checked in a real life circuit. The preliminary results point to a very promising test technique. The test is very precise, low cost and allows a complete fault coverage with a very small testing time.     

Generation and Verification of Tests for Analog Circuits Subject to Process Parameter Deviations

The paper presents a test stimulus generation and fault simulation methodology for the detection of catastrophic faults in analog circuits. The test methodology chosen for evaluation is RMS AC supply current monitoring. Tests are generated and evaluated taking account of the potential fault masking effects of process spread on the faulty circuit responses. A new test effectiveness metric of probability of detection is defined and the application of the technique to an analog multiplier circuit is presented. The fault coverage figures are therefore more meaningful than those obtained with a fixed threshold.     

A Switched-Capacitor Adaptive Lattice Filter

Integration of an adaptive lattice filter in MOS-LSI technology is described. The architecture is designed to optimally exploit the advantages of analog and digital approaches. Switched-capacitor techniques are used for filtering and digital circuitry is used to perform the adaption. To test the concept, the analog circuitry was fabricated as an IC and operated with discrete digital circuitry. However, a complete monolithic implementation using this approach can be realized. The switched-capacitor metal-gate CMOS IC has die size of 18 500 mils/sup 2/ and power consumption of 108 mW.     

Scan power-aware deterministic test scheme using a low-transition linear decompressor

Growing test data volume and excessive testing power are both serious challenges in the testing of very large-scale integrated circuits. This article presents a scan power-aware deterministic test method based on a new linear decompressor which is composed of a traditional linear decompressor, k-input AND gates and T flip-flops. This decompression architecture can generate the low-transition deterministic test set for a circuit under test. When applying the test patterns generated by the linear decompressor, only a few transitions occur in the scan chains, and hence the switching activity during testing decreases significantly. Entire test flow compatible with the design is also presented. Experimental results on several large International Symposium on Circuits and Systems’89 and International Test Conference’99 benchmark circuits demonstrate that the proposed methodology can reduce test power significantly while providing a high compression ratio with limited hardware overhead.     

Functional Constraints vs. Test Compression in Scan-Based Delay Testing

We present an approach to prevent overtesting in scan-based delay test. The test data is transformed with respect to functional constraints while simultaneously keeping as many positions as possible unspecified in order to facilitate test compression. The method is independent of the employed delay fault model, ATPG algorithm and test compression technique, and it is easy to integrate into an existing flow. Experimental results emphasize the severity of overtesting in scan-based delay test. Influence of different functional constraints on the amount of the required test data and the compression efficiency is investigated. To the best of our knowledge, this is the first systematic study on the relationship between overtesting prevention and test compression.     

伪随机测试生成在混合电路参数测试中的应用

混合信号电路在通信、多媒体等领域获得越来越广泛的应用。然而,测试也变得更复杂。传统上对模拟电路的测试采用的是直接功能测试,即直接测量电路的性能参数Z。采用该测试方法,其缺点是测试时间长、测试设备昂贵、且精度差。本文针对这一问题进行研究,详细讨论了利用伪随机技术进行混合信号电路测试的方法。