Effect of processing conditions on inversion layer mobility and interface state density in 4H−SiC MOSFETs

N-channel, inversion mode MOSFETs have been fabricated on 4H−SiC using different oxidation procedures, source/drain implant species and implant activation temperature. The fixed oxide charge and the field-effect mobility in the inversion layer have been extracted, with best values of 1.8×10¹² cm⁻² and 14 cm²/V-s, respectively. The interface state density, D_it close to the conduction band of 4H−SiC has been extracted from the subthreshold drain characteristics of the MOSFETs. A comparison of interface state density, inversion layer mobility and fixed oxide charges between the different processes indicate that pull-out in wet ambient after reoxidation of gate oxide improves the 4H−SiC/SiO₂ interface quality.     

Extraction of SiO2/SiC interface trap profile in 4H- and 6H-SiC metal-oxide semiconductor field-effect transistors from subthreshold characteristics at 25°C and 150°C

The profile of trap density at the SiO₂/SiC interface in SiC metal-oxide semiconductor field-effect transistors (MOSFETs) is critical to study the channel electron mobility and evaluate device performance under various processing and annealing conditions. In this work, we report on our results in determining the interface trap density in 4H- and 6H-SiC MOSFETs annealed in dry O₂, NO, and CO₂, respectively, based on the device transfer and currentvoltage characteristics in the subthreshold region at 25°C and 150°C. We also studied electron field-effect mobility, fixed oxide charge, and gate leakage in those devices.     

Improved oxidation procedures for reduced SiO2/SiC defects

A significant reduction in the effective oxide charge and interface state densities in oxides grown on p-type 6H-SiC has been obtained by lowering the oxidation temperature of SiC to 1050°C. Further improvements are obtained by following the oxidation with an even lower temperature re-oxidation anneal. This anneal dramatically improves the electrical properties of the Si/SiC interface, and substantially lowers the interface state density. The net oxide charge density on p-type 6H-SiC is also lowered significantly, but remains quite high, at 1.0 × 10¹² cm^-2. The interface state densities of 1.0 × 10¹¹ cnr⁻²/eV are approaching acceptable MOS device levels. The breakdown fields of the oxides are also substantially improved by both the lower oxidation temperature and re-oxidation anneal. Using a low temperature oxidation followed by a re-oxidation anneal for MOSFETs results in a room temperature mobility of 72 cm²/V-s, the highest channel mobility reported for SiC MOSFETs to date.     

Behavior of hot carrier generation in power SOI LDNMOS with shallow trench isolation (STI)

In this work, we investigated the hot carrier (HC) generation of power silicon-on-insulator (SOI) lateral double-diffused N-type MOSFETs (LDNMOSFET) with shallow trench isolation (STI) structure under different biasing conditions. Experimental measurements of drain and substrate currents are done. Two-dimensional (2-D) device simulation is performed to provide a better insight on the electrical behaviors of the device by looking at the electric-field (EF), electron current density (J_E) and impact ionization generation rate (R_II) distributions in the devices. The high R_II site is found to be near the STI corner instead of near the channel or field oxide area close to the gate surface in standard small signal MOSFET.     

SiC-MOS界面优化的工艺验证及MOSFET电学特性仿真拟合

SiC因其优越的电学特性,已发展成为高压功率器件领域的翘楚。然而,SiC与SiO₂界面存在高密度界面态,使得SiC MOSFET沟道迁移率远低于SiC材料本身的体迁移率,大大约束了SiC材料本身电学性能的发挥。为改善反型层沟道迁移率,不同功率器件厂商采用了不同的栅极氧化工艺,所实现的栅极氧化层界面态密度各有不同,现有的功率器件仿真软件提供的多种界面态能级分布模型都需要芯片厂商实际的流片数据作为支撑,这对功率器件上游设计人员产生了阻碍。基于此,文章通过流片测试数据,结合TCAD仿真软件给出了一种用于SiC MOSFET器件仿真的界面态能级分布模型。利用给出的界面态能级分布模型,与实际产品对比,仿真得出的I-V曲线与测试曲线基本重合。     

Compound semiconductor MOSFETs

Enhancement mode, high electron mobility MOSFET devices have been fabricated using an oxide high-κ gate dielectric stack developed using molecular beam epitaxy. A template layer of Ga₂O₃, initially deposited on the surface of the III-V device unpins the GaAs Fermi level while a (Gd_xGa_1−x)₂O₃ bulk ternary layer forms the highly resistive layer to reduce leakage current through the dielectric stack. A midgap interface state density of ∼2 × 10¹¹ cm⁻² eV⁻¹ and a dielectric constant of 20 are determined using electrical measurements.. N-channel MOSFETs with a gate length of 1 μm and a source-drain spacing of 3 μm show a threshold voltage, saturation current and transconductance of 0.11 V, 380 mA/mm and 250 mS/mm, respectively.     

SiC JBS二极管和SiC MOSFET的空间辐照效应及机理

基于第六代650 V 碳化硅结型肖特基二极管(SiC JBS Diode)和第三代900 V 碳化硅场效应晶体管(SiC MOSFET),开展SiC功率器件的单粒子效应、总剂量效应和位移损伤效应研究。20~80 MeV质子单粒子效应实验中,SiC功率器件发生单粒子烧毁(SEB)时伴随着波浪形脉冲电流的产生,辐照后SEB器件的击穿特性完全丧失。SiC功率器件发生SEB时的累积质子注量随偏置电压的增大而减小。利用计算机辅助设计工具(TCAD)开展SiC MOSFET的单粒子效应仿真,结果表明,重离子从源极入射器件时,具有更短的SEB发生时间和更低的SEB阈值电压。栅-源拐角和衬底-外延层交界处为SiC MOSFET的SEB敏感区域,强电场强度和高电流密度的同时存在导致敏感区域产生过高的晶格温度。SiC MOSFET在栅压偏置(U_GS=3 V,U_DS=0 V)下开展钴源总剂量效应实验,相比于漏压偏置(U_GS=0 V,U_DS=300 V)和零压偏置(U_GS=U_DS=0 V),出现更严重的电学性能退化。利用中带电压法分析发现,栅极偏置下氧化层内的垂直电场提升了陷阱电荷的生成率,加剧了阈值电压的退化。中子位移损伤会导致SiC JBS二极管的正向电流和反向电流减小。在漏极偏置下进行中子位移损伤效应实验,SiC MOSFET的电学性能退化最严重。该研究为空间用SiC器件的辐射效应机理及抗辐射加固研究提供了一定的参考和支撑。     

Significantly improved performance of MOSFETs on silicon carbideusing the 15R-SiC polytype

Recent studies regarding MOSFETs on SiC reveal that 4H-SiC devices suffer from a low inversion layer mobility, while in 6H-SiC, despite a higher channel mobility the bulk mobility parallel to the c-axis is too low, making this polytype unattractive for power devices. This work presents experimental mobility data of MOSFETs fabricated on different polytypes as well as capacitance-voltage (C-V) measurements of corresponding n-type MOS structures which give evidence that the low inversion channel mobility in 4H-SiC is caused by a high density of SiC-SiO₂ interface states close to the conduction band. These defects are believed to be inherent to all SiC polytypes and energetically pinned at around 2.9 eV above the valence band edge. Thus, for polytypes with band gaps smaller than 4H-SiC like 6H-SiC and 15R-SiC, the majority of these states will become resonant with the conduction band at room temperature or above, thus remarkably suppressing their negative effect on the channel mobility. In order to realize high performance power MOSFETs the results reveal that 15R-SiC is the best candidate among all currently accessible SiC polytypes     

Active defects in MOS devices on 4H-SiC: A critical review

The state-of-the-art 4H-SiC MOSFETs still suffer from performance (low channel-carrier mobility and high threshold voltage) and reliability (threshold voltage instability) issues. These issues have been attributed to a large density of electrically active defects that exist in the SiO₂–SiC interfacial region. This paper reviews the earlier and the latest results about the responsible defects for the performance and reliability issues of SiC MOS devices, in the context of the evolution of physical understanding of these defects. The aim of this critical review is to clarify possible confusions due to inconsistencies between the earlier and the latest results. Specific clarifications relate to the physical position of the active defects (whether they are located at or near the SiO₂–SiC interface) and the energy position of their energy levels (above or below the bottom of conduction band).     

Comparison of 3C–SiC, 6H–SiC and 4H–SiC MESFETs performances

A comparative analysis of the main DC and microwave performances of MESFETs made of the commercially available silicon carbide polytypes 3C–SiC, 6H–SiC and 4H–SiC is presented. In this purpose, we have developed an analytical model that takes into account the basic material properties such as field dependent mobility, critical electric field, ionization grade of impurities, and saturation of the charge carrier velocity. For a better precision in appreciating device characteristics in the case of a short gate device, the influences of the gate length and parasitic elements of the structure, e.g. source and drain resistances, are considered too. Cut-off frequency f_T, the corresponding output power P_m and the thermal stability are also evaluated and compared with the available experimental data, revealing the specific electrical performances of MESFETs, when any of the three polytypes is used in device fabrication.     

Effect of underlap and gate length on device performance of an AlInN/GaN underlap MOSFET

We investigate the performance of an 18 nm gate length AlInN/GaN heterostructure underlap double gate MOSFET, using 2D Sentaurus TCAD simulation. The device uses lattice-matched wideband Al_0.83In_0.17N and narrowband GaN layers, along with high-k Al₂O₃ as the gate dielectric. The device has an ultrathin body and is designed according to the ITRS specifications. The simulation is done using the hydrodynamic model and interface traps are also considered. Due to the large two-dimensional electron gas (2DEG) density and high velocity, the maximal drain current density achieved is very high. Extensive device simulation of the major device performance metrics such as drain induced barrier lowering (DIBL), subthreshold slope (SS), delay, threshold voltage (V_t), I_on/I_off ratio and energy delay product have been done for a wide range of gate and underlap lengths. Encouraging results for delay, I_on, DIBL and energy delay product are obtained. The results indicate that there is a need to optimize the I_off and SS values for specific logic design. The proposed AlInN/GaN heterostructure underlap DG MOSFET shows excellent promise as one of the candidates to substitute currently used MOSFETs for future high speed applications.     

Low-field mobility and carrier transport mechanism transition in nanoscale MOSFETs

This paper extends the flux scattering method to study the carrier transport property in nanoscale MOSFETs with special emphasis on the low-field mobility and the transport mechanism transition. A unified analytical expression for the low-field mobility is proposed, which covers the entire regime from drift-diffusion transport to quasi-ballistic transport in 1-D, 2-D and 3-D MOSFETs. Two key parameters, namely the long-channel low-field mobility (μ0) and the low-field mean free path (λ0), are obtained from the experimental data, and the transport mechanism transition in MOSFETs is further discussed both experimentally and theoretically. Our work shows that λ0 is available to characterize the inherent transition of the carrier transport mechanism rather than the low-field mobility. The mobility reduces in the MOSFET with the shrinking of the channel length; however, λ0 is nearly a constant, and λ0 can be used as the "entry criterion" to determine whether the device begins to operate under quasi-ballistic transport to some extent.     

Performance analysis of long Ge channel double gate (DG) p MOSFETs with high-k gate dielectrics based on carrier concentration formulation

In this paper, electrical behavior of symmetric double gate Ge channel MOSFETs with high-k dielectrics is reported on the basis of carrier concentration formalism. The model relies on the solution of Poisson-Boltzmann equations subject to suitable boundary conditions taking into account the effect of interface trap charge density (D_it) and the Pao-Sah’s current formulation considering field dependent hole mobility. It is continuous as it holds good for sub-threshold, weak and strong inversion regions of device operation. The proposed model has been employed to calculate the drain current of DG MOSFETs for different values of gate voltage and drain voltage along with various important device parameters such as transconductance, output conductance, and transconductance per unit drain current for a wide range of interface trap charge density, equivalent oxide thickness (EOT) and bias conditions. Moreover, most of the important device parameters are compared with their corresponding Si counter parts. Accuracy of the model has been verified by comparing analytical results with the numerical simulation data. A notable improvement of the drive current and transconductance for Ge devices is observed with reference to Si devices, particularly when D_it is small.     

Some Critical Materials and Processing Issues in SiC Power Devices

There has been a rapid improvement in SiC materials and power devices during the last few years. However, the materials community has overlooked some critical issues, which may threaten the emergence of SiC power devices in the coming years. Some of these pressing materials and processing issues will be presented in this paper. The first issue deals with the possibility of process-induced bulk traps in SiC immediately under the SiC/SiO₂ interface, which may be involved in the reduction of effective inversion layer electron mobility in SiC metal–oxide–semiconductor field-effect transistor (MOSFETs). The second issue addresses the effect of recombination-induced stacking faults (SFs) in majority carrier devices such as MOSFETs, Schottky diodes, and junction field-effect transistors (JFETs). In the past it was assumed that the SFs only affect the bipolar devices such as PiN diodes and thyristors. However, most majority carrier devices have built-in p–n junction diodes, which can become forward biased during operation in a circuit. Thus, all high-voltage SiC devices are susceptible to this phenomenon.     

Phosphorous passivation of the SiO2/4H–SiC interface

We describe experimental and theoretical studies to determine the effects of phosphorous as a passivating agent for the SiO₂/4H–SiC interface. Annealing in a P₂O₅ ambient converts the SiO₂ layer to PSG (phosphosilicate glass) which is known to be a polar material. Higher mobility (approximately twice the value of 30–40 cm²/V s obtained using nitrogen introduced with an anneal in nitric oxide) and lower threshold voltage are compatible with a lower interface defect density. Trap density, current–voltage and bias-temperature stress (BTS) measurements for MOS capacitors are also discussed. The BTS measurements point to the possibility of an unstable MOSFET threshold voltage caused by PSG polarization charge at the O–S interface. Theoretical considerations suggest that threefold carbon atoms at the interface can be passivated by phosphorous which leads to a lower interface trap density and a higher effective mobility for electrons in the channel. The roles of phosphorous in the passivation of correlated carbon dangling bonds, for SiC counter-doping, for interface band-tail state suppression, for Na-like impurity band formation and for substrate trap passivation are also discussed briefly.     

Reliability and performance limitations in SiC power devices

Despite silicon carbide’s (SiC’s) high breakdown electric field, high thermal conductivity and wide bandgap, it faces certain reliability challenges when used to make conventional power device structures like power MOS-based devices, bipolar-mode diodes and thyristors, and Schottky contact-based devices operating at high temperatures. The performance and reliability issues unique to SiC discussed here include: (a) MOS channel conductance/gate dielectric reliability trade-off due to lower channel mobility as well as SiC–SiO₂ barrier lowering due to interface traps; (b) reduction in breakdown field and increased leakage current due to material defects; and (c) increased leakage current in SiC Schottky devices at high temperatures.Although a natural oxide is considered a significant advantage for realizing power MOSFETs and IGBTs in SiC, devices to date have suffered from poor inversion channel mobility. Furthermore, the high interface state density presently found in the SiC–SiO₂ system causes the barrier height between SiC and SiO₂ to be reduced, resulting in increased carrier injection in the oxide. A survey of alternative dielectrics shows that most suffer from an even smaller conduction band offset at the SiC–dielectric interface than the corresponding Silicon–dielectric interface and have a lower breakdown field strength than SiO₂. Thus, an attractive solution to reduce tunneling such as stacked dielectrics is required.In Schottky-based power devices, the reverse leakage currents are dominated by the Schottky barrier height, which is in the 0.7–1.2 eV range. Because the Schottky leakage current increases with temperature, the SiC Schottky devices have a reduction in performance at high temperature similar to that of Silcon PN junction-based devices, and they do not have the high temperature performance benefit associated with the wider bandgap of SiC.Defects in contemporary SiC wafers and epitaxial layers have also been shown to reduce critical breakdown electric field, result in higher leakage currents, and degrade the on-state performance of devices. These defects include micropipes, dislocations, grain boundaries and epitaxial defects. Optical observation of PN diodes undergoing on-state degradation shows a simultaneous formation of mobile and propagating crystal stacking faults. These faults nucleate at grain boundaries and permeate throughout the active area of the device, thus degrading device performance after extended operation.     

高压VDMOS器件的研制及其抗辐照特性研究

利用SILVACO工艺模拟软件和器件模拟软件以及L—Edit版图设计工具,我们对一款高压VDMOS功率器件进行了模拟仿真和优化设计。利用自主开发的VDMOS工艺流程完成了器件的实际流片。测试结果表明,器件的源漏击穿电压达到600V以上,导通电阻小于2．5Ω,跨导为4S,栅一源泄漏电流约为±100nA,零栅电压时的漏一源泄漏电流约为10υA,二极管正向压降约为1．2V。采用二维器件模拟仿真工具以及相关物理模型对所研制的高压VDMOS器件的SEB和SEGR效应进行了分析,并通过对所研制的器件样片采用钴-60y射线源进行辐照实验,研究了在一定剂量率、不同总剂量水平下辐照对所研制的高压VDMOS器件相关电学参数的影响。     

Analog and radio-frequency performance analysis of silicon-nanotube MOSFETs

This work presents a comparative study of the influence of various parameters on the analog and RF properties of silicon-nanotube MOSFETs and nanowire-based gate-all-around (GAA) MOSFETs. The important analog and RF performance parameters of SiNT FETs and GAA MOSFETs, namely drain current (I_d), transconductance to drain current ratio (g_m/I_d), I_on/I_off, the cut-off frequency (f_T) and the maximum frequency of oscillation (f_MAX) are evaluated with the help of Y- and H-parameters which are obtained from a 3-D device simulator, ATLAS^TM. It is found that the silicon-nanotube MOSFETs have far more superior analog and RF characteristics (g_m/I_d, f_T and f_MAX) compared to the nanowire-based gate-all-around GAA MOSFETs. The silicon-nanotube MOSFET shows an improvement of~2.5 and 3 times in the case of f_T and f_MAX values respectively compared with the nanowire-based gate-all-around (GAA) MOSFET.     

MOS Characteristics of C-Face 4H-SiC

Metal–oxide–semiconductor (MOS) capacitors and MOS field-effect transistors (MOSFETs) fabricated on the carbon face of 4H-SiC were characterized following different postoxidation annealing methods used to passivate the oxide–semiconductor (O–S) interface. Of the various processes studied, sequential postoxidation annealing in NO followed by atomic hydrogen gave the lowest interface trap density (D _it). Direct oxidation/passivation in NO yielded somewhat better I–V characteristics, though all passivation ambients produced approximately the same breakdown field strength. n-Channel MOSFETs showed high channel mobility at low field, which is likely caused by the presence of mobile ions at the O–S interface. Comparisons with the silicon face are presented for interface trap density, oxide breakdown field, and channel mobility. These comparisons suggest that the carbon face does not offer significant performance advantages.     

Self-aligned metal-SiO2-InP based MISFETS having modulation doped channels

A novel metal-SiO₂-InP MISFET (metal-insulator-semiconductor field effect transistor) structure is proposed. This device incorporates a modulation doped channel and the self-aligned gate feature of Si MOSFETs. The modulation doping provides very high electron mobility and the self-alignment of gate, source and drain provides high packing density. Analytical results on current-voltage and transconductance characteristics are presented. Significant enhancement in high frequency performance over conventional MISFETs, employing SiO₂ as an insulator, is reported.