InGaAs/GaAs 0.98- $mu{hbox {m}}$ Low-Divergence Central-Lobe Semiconductor Lasers With $delta$ -Doped Resonant Tunneling Quantum Wells

In this paper, we describe a new structure design for producing low-threshold, high-efficiency, and high-brightness 0.98-$mu{hbox {m}}$ lasers. In this structure, we incorporated a self-discriminating weak optical confinement asymmetrical waveguide coupled to passive waveguides, and an active region based on three InGaAs quantum wells (QWs) coupled to Te n-type $delta$-doping. Optimized coupling between the $delta$-doping and the three QWs, together with waveguide optimization and doping profile optimization, yields $J_{rm th}=98 {hbox {A/cm}}^{2}$ per QW, ${T}_{0}=80;^{circ}hbox{C}$, and a far-field central lobe angle of $sim 10^{circ}$.      

A 10-kV Monolithic Darlington Transistor With $beta_{ rm forced}$ of 336 in 4H-SiC

4H-SiC bipolar Darlington transistors with a record-high current gain have been demonstrated. The dc forced current gain was measured up to 336 at 200 $hbox{W/cm}^{2}$ ( $J_{C} = hbox{35} hbox{A/cm}^{2}$ at $V_{rm CE} = hbox{5.7} hbox{V}$) at room temperature. The current gain exhibits a negative temperature coefficient and remains as high as 135 at 200 $^{circ}hbox{C}$. The specific on-resistance is 140 $hbox{m}Omegacdothbox{cm}^{2}$ at room temperature and increases at elevated temperatures. An open-emitter breakdown voltage $(BV_{rm CBO})$ of 10 kV was achieved at a leakage current density of $≪hbox{1} hbox{mA/cm}^{2}$. The device exhibits an open-base breakdown voltage $(BV_{rm CEO})$ of 9.5 kV. The high current gain of SiC Darlington transistors can significantly reduce the gate-drive power consumption with the same forward-voltage drop as that of 10-kV SiC bipolar junction transistors, thus making the device attractive for high-power high-temperature applications.      

Performance Improvement of N-Type $hbox{TiO}_{x}$ Active-Channel TFTs Grown by Low-Temperature Plasma-Enhanced ALD

We report on performance improvement of $n$-type oxide–semiconductor thin-film transistors (TFTs) based on $hbox{TiO}_{x}$ active channels grown at 250 $^{circ}hbox{C}$ by plasma-enhanced atomic layer deposition. TFTs with as-grown $hbox{TiO}_{x}$ films exhibited the saturation mobility $(mu_{rm sat})$ as high as 3.2 $hbox{cm}^{2}/hbox{V}cdothbox{s}$ but suffered from the low on–off ratio $(I_{rm ON}/I_{rm OFF})$ of $hbox{2.0} times hbox{10}^{2}$. $hbox{N}_{2}hbox{O}$ plasma treatment was then attempted to improve $I_{rm ON}/I_{rm OFF}$. Upon treatment, the $hbox{TiO}_{x}$ TFTs exhibited $I_{rm ON}/I_{rm OFF}$ of $hbox{4.7} times hbox{10}^{5}$ and $mu_{rm sat}$ of 1.64 $hbox{cm}^{2}/hbox{V}cdothbox{s}$, showing a much improved performance balance and, thus, demonstrating their potentials for a wide variety of applications such as backplane technology in active-matrix displays and radio-frequency identification tags.      

1580-V–40-$hbox{m}Omegacdot hbox{cm}^{2}$ Double-RESURF MOSFETs on 4H-SiC $(hbox{000}bar{hbox{1}})$

Double-reduced-surface-field (RESURF) MOSFETs with $hbox{N}_{2}hbox{O}$ -grown oxides have been fabricated on the 4H-SiC $(hbox{000} bar{hbox{1}})$ face. The double-RESURF structure is effective in reducing the drift resistance, as well as in increasing the breakdown voltage. In addition, by utilizing the 4H-SiC $(hbox{000}bar{hbox{1}})$ face, the channel mobility can be increased to over 30 $hbox{cm}^{2}/hbox{V}cdothbox{s}$, and hence, the channel resistance is decreased. As a result, the fabricated MOSFETs on 4H-SiC $( hbox{000}bar{hbox{1}})$ have demonstrated a high breakdown voltage $(V_{B})$ of 1580 V and a low on-resistance $(R_{rm ON})$ of 40 $hbox{m}Omega cdothbox{cm}^{2}$. The figure-of-merit $(V_{B}^{2}/R_{rm ON})$ of the fabricated device has reached 62 $hbox{MW/cm}^{2}$, which is the highest value among any lateral MOSFETs and is more than ten times higher than the “Si limit.”      

High-Performance Metal/High-$k$ n- and p-MOSFETs With Top-Cut Dual Stress Liners Using Gate-Last Damascene Process on (100) Substrates

Newly proposed mobility-booster technologies are demonstrated for metal/high- $k$ gate-stack n- and pMOSFETs. The process combination of top-cut SiN dual stress liners and damascene gates remarkably enhances local channel stress particularly for shorter gate lengths in comparison with a conventional gate-first process. Dummy gate removal in the damascene gate process induces high channel stress, because of the elimination of reaction force from the dummy gate. PFETs with top-cut compressive stress liners and embedded SiGe source/drains are performed by using atomic layer deposition TiN/$ hbox{HfO}_{2}$ gate stacks with $T_{rm inv} = hbox{1.4} hbox{nm}$ on (100) substrates. On the other hand, nFETs with top-cut tensile stress liners are obtained by using $hbox{HfSi}_{x}/hbox{HfO}_{2}$ gate stacks with $T_{rm inv} = hbox{1.4} hbox{nm}$. High-performance n- and pFETs are achieved with $I_{rm on} = hbox{1300}$ and 1000 $muhbox{A}/muhbox{m} hbox{at} I_{rm off} = hbox{100} hbox{nA}/mu hbox{m}$, $V_{rm dd} = hbox{1.0} hbox{V}$, and a gate length of 40 nm, respectively.      

Impacts of $hbox{N}_{2}$ and $hbox{NH}_{3}$ Plasma Surface Treatments on High-Performance LTPS-TFT With High-$kappa$ Gate Dielectric

Low-temperature polycrystalline-silicon thin-film transistors (LTPS-TFTs) with high- $kappa$ gate dielectrics and plasma surface treatments are demonstrated for the first time. Significant field-effect mobility $mu_{rm FE}$ improvements of $sim$86.0% and 112.5% are observed for LTPS-TFTs with $hbox{HfO}_{2}$ gate dielectric after $hbox{N}_{2}$ and $ hbox{NH}_{3}$ plasma surface treatments, respectively. In addition, the $hbox{N}_{2}$ and $ hbox{NH}_{3}$ plasma surface treatments can also reduce surface roughness scattering to enhance the field-effect mobility $mu_{rm FE}$ at high gate bias voltage $V_{G}$, resulting in 217.0% and 219.6% improvements in driving current, respectively. As a result, high-performance LTPS-TFT with low threshold voltage $V_{rm TH} sim hbox{0.33} hbox{V}$, excellent subthreshold swing S.S. $sim$0.156 V/decade, and high field-effect mobility $mu_{rm FE} sim hbox{62.02} hbox{cm}^{2}/hbox{V} cdot hbox{s}$ would be suitable for the application of system-on-panel.      

3510-V 390-$hbox{m}Omegacdothbox{cm}^{2}$ 4H-SiC Lateral JFET on a Semi-Insulating Substrate

The performance of high-voltage 4H-SiC lateral JFETs on a semi-insulating substrate is reported in this letter. The design of the voltage-supporting layers is based on the charge compensation of p- and n-type epilayers. The best measured breakdown voltage is 3510 V, which, to the authors' knowledge, is the highest value ever reported for SiC lateral switching devices. The $R_{rm on}$ of this device is 390 $hbox{m}Omegacdot hbox{cm}^{2}$, in which 61% is due to the drift-region resistance. The $BV^{2}/R_{rm on}$ is 32 $hbox{MW}/hbox{cm}^{2}$, which is typical among other reported SiC lateral devices.      

$hbox{TiN/ZrO}_{2}$/Ti/Al Metal–Insulator–Metal Capacitors With Subnanometer CET Using ALD-Deposited $hbox{ZrO}_{2}$ for DRAM Applications

We provide the first report of the structural and electrical properties of $hbox{TiN/ZrO}_{2}$/Ti/Al metal–insulator–metal capacitor structures, where the $hbox{ZrO}_{2}$ thin film (7–8 nm) is deposited by ALD using the new zirconium precursor ZrD-04, also known as Bis(methylcyclopentadienyl) methoxymethyl. Measured capacitance–voltage ($C$– $V$) and current–voltage ( $I$–$V$) characteristics are reported for premetallization rapid thermal annealing (RTP) in $hbox{N}_{2}$ for 60 s at 400 $^{circ}hbox{C}$, 500 $^{circ}hbox{C}$, or 600 $^{ circ}hbox{C}$. For the RTP at 400 $^{circ}hbox{C}$ , we find very low leakage current densities on the order of nanoamperes per square centimeter at a gate voltage of 1 V and low capacitance equivalent thickness values of $sim$ 0.9 nm at a gate voltage of 0 V. The dielectric constant of $ hbox{ZrO}_{2}$ is 31 $pm$ 2 after RTP treatment at 400 $^{circ}hbox{C}$.      

2 MHz AO $Q$ -switched ${rm TEM}_{00}$ Grazing Incidence Laser With 3 at.% Neodymium Doped Nd:YVO$_{4}$

We present a detailed experimental and theoretical study of the ultrahigh repetition rate AO $Q$ -switched ${rm TEM}_{00}$ grazing incidence laser. Up to 2.1 MHz $Q$-switching with ${rm TEM}_{00}$ output of 8.6 W and 2.2 MHz $Q$ -switching with multimode output of 10 W were achieved by using an acousto-optics $Q$ -switched grazing-incidence laser with optimum grazing-incidence angle and cavity configuration. The crystal was 3 at.% neodymium doped Nd:YVO$_{4}$ slab. The pulse duration at 2 MHz repetition rate was about 31 ns. The instabilities of pulse energy at 2 MHz repetition rate were less than ${pm}6.7hbox{%}$ with ${rm TEM}_{00}$ operation and ${pm}3.3hbox{%}$ with multimode operation respectively. The modeling of high repetition rate $Q$-switched operation is presented based on the rate equation, and with the solution of the modeling, higher pump power, smaller section area of laser mode, and larger stimulated emission cross section of the gain medium are beneficial to the $Q$-switched operation with ultrahigh repetition rate, which is in consistent with the experimental results.      

Demonstration of Tunneling FETs Based on Highly Scalable Vertical Silicon Nanowires

This letter demonstrates a vertical silicon-nanowire (SiNW)-based tunneling field-effect transistor (TFET) using CMOS-compatible technology. With a $hbox{Si} hbox{p}^{+}{-}hbox{i}{-} hbox{n}^{+}$ tunneling junction, the TFET with a gate length of $sim$200 nm exhibits good subthreshold swing of $sim$ 70 mV/dec, superior drain-induced-barrier-lowering of $sim$ 17 mV/V, and excellent $I_{rm on} {-} I_{rm off}$ ratio of $sim!!hbox{10}^{7}$ with a low $I_{rm off} (sim!!hbox{7} hbox{pA}/muhbox{m})$. The obtained 53 $muhbox{A}/muhbox{m} I_{rm on}$ can be further enhanced with heterostructures at the tunneling interface. The vertical SiNW-based TFET is proposed to be an excellent candidate for ultralow power and high-density applications.      

Integrated Hydrogen-Sensing Amplifier With GaAs Schottky-Type Diode and InGaP–GaAs Heterojunction Bipolar Transistor

New hydrogen-sensing amplifiers are fabricated by integrating a GaAs Schottky-type hydrogen sensor and an InGaP–GaAs heterojunction bipolar transistor. Sensing collector currents ( $I_{rm CN}$ and $I_{rm CH}$) reflecting to $hbox{N}_{2}$ and hydrogen-containing gases are employed as output signals in common-emitter characteristics. Gummel-plot sensing characteristics with testing gases as inputs show a high sensing-collector-current gain $(I_{rm CH}/I_{rm CN})$ of $≫hbox{3000}$. When operating in standby mode for in situ long-term detection, power consumption is smaller than 0.4 $muhbox{W}$. Furthermore, the room-temperature response time is 85 s for the integrated hydrogen-sensing amplifier fabricated with a bipolar-type structure.      

Comparative Study of the Low-Frequency-Noise Behaviors in a-IGZO Thin-Film Transistors With $hbox{Al}_{2}hbox{O}_{3}$ and $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ Gate Dielectrics

A comparative study is made of the low-frequency noise (LFN) in amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) with $hbox{Al}_{2}hbox{O}_{3}$ and $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ gate dielectrics. The LFN is proportional to $hbox{1}/f^{gamma}$, with $gamma sim hbox{1}$ for both devices, but the normalized noise for the $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ device is two to three orders of magnitude lower than that for the $hbox{Al}_{2} hbox{O}_{3}$ device. The mobility fluctuation is the dominant LFN mechanism in both devices, but the noise from the source/drain contacts becomes comparable to the intrinsic channel noise as the gate overdrive voltage increases in $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ devices. The $hbox{SiN}_{x}$ interfacial layer is considered to be very effective in reducing LFN by suppressing the remote phonon scattering from the $hbox{Al}_{2}hbox{O}_{3}$ dielectric. Hooge's parameter is extracted to $sim !!hbox{6.0} times hbox{10}^{-3}$ in $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ devices.      

Extraction of the Effective Mobility of $ hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ MOSFETs

The extraction of the effective mobility on $hbox{In}_{0.53} hbox{Ga}_{0.47}hbox{As}$ metal–oxide–semiconductor field-effect transistors (MOSFETs) is studied and shown to be greater than 3600 $hbox{cm}^{2}/hbox{V} cdot hbox{s}$. The removal of $C_{rm it}$ response in the split $C$–$V$ measurement of these devices is crucial to the accurate analysis of these devices. Low-temperature split $C$–$V$ can be used to freeze out the $D_{rm it}$ response to the ac signal but maintain its effect on the free carrier density through the substrate potential. Simulations that match this low-temperature data can then be “warmed up” to room temperature and an accurate measure of $Q_{rm inv}$ is achieved. These results confirm the fundamental performance advantages of $hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ MOSFETs.      

A Center-Offset Polycrystalline-Silicon Thin-Film Transistor With ${rm n}^{+}$ Amorphous-Silicon Contacts

We have studied a bottom-gate polycrystalline-silicon thin-film transistor (poly-Si TFT) with amorphous-silicon (a-Si) ${rm n}^{+}$ contacts and center-offset gated structure, where intrinsic poly-Si is used in the center-offset region. The fabrication process is compatible with the conventional a-Si TFT with addition of thermal annealing for crystallization of a-Si. The bottom-gate poly-Si TFT with a 5-$muhbox{m}$ offset length exhibited a field-effect mobility of 18.3 $hbox{cm}^{2}/hbox{V} cdot hbox{s}$ and minimum OFF-state current of $hbox{2.79} times hbox{10}^{-12} hbox{A}/muhbox{m}$ at $V_{rm ds} = hbox{5} hbox{V}$. The leakage currents are two orders of magnitude lower than those of a nonoffset TFT with mobility drop from 23.8 to 18.3 $hbox{cm}^{2}/ hbox{V} cdot hbox{s}$.      

High-Density and Low-Leakage-Current MIM Capacitor Using Stacked $hbox{TiO}_{2}/hbox{ZrO}_{2}$ Insulators

We have fabricated high-$kappa hbox{Ni}/hbox{TiO}_{2}/hbox{ZrO}_{2}/ hbox{TiN}$ metal–insulator–metal (MIM) capacitors. A low leakage current of $hbox{8} times hbox{10}^{-8} hbox{A/cm}^{2}$ at 125 $^{circ}hbox{C}$ was obtained with a high 38- $hbox{fF}/muhbox{m}^{2}$ capacitance density and better than the $hbox{ZrO}_{2}$ MIM capacitors. The excellent device performance is due to the lower electric field in 9.5-nm-thick $hbox{TiO}_{2}/ hbox{ZrO}_{2}$ devices to decrease the leakage current and to a higher $kappa$ value of 58 for $ hbox{TiO}_{2}$ as compared with that of $hbox{ZrO}_{2}$ to preserve the high capacitance density.      

Electrical Properties of $hbox{Ga}_{2}hbox{O}_{3}/ hbox{GaAs}$ Interfaces and GdGaO Dielectrics in GaAs-Based MOSFETs

Electrical properties of $hbox{Ga}_{2}hbox{O}_{3}/hbox{GaAs}$ interfaces with GdGaO cap dielectrics used in recent enhancement-mode GaAs-based NMOSFETs which perform in line with theoretical model predictions are presented. Capacitors with GdGaO thickness ranging from 3.0 to 18 nm ($hbox{0.9} leq hbox{EOT} leq hbox{3.9} hbox{nm}$) have been characterized by capacitance–voltage measurements. Midgap interface state density $D_{rm it}$, effective workfunction $phi_{m}$, fixed charge $Q_{f}$, dielectric constant $kappa$, and low field leakage current density are $hbox{2} times hbox{10}^{11} hbox{cm}^{-2} cdot hbox{eV}^{-1}$, 4.93 eV, $-hbox{8.9} times hbox{10}^{11} hbox{cm}^{-2}$, 19.5, and $hbox{10}^{-9}{-} hbox{10}^{-8} hbox{A/cm}^{2}$, respectively. The presence of interfacial Gd was confirmed to dramatically degrade electrical interface properties. The data illuminate the intimate interplay between heterostructure and interface engineering to achieve optimum MOSFET operation.      

A Comparative NBTI Study of $hbox{HfO}_{2}$, $hbox{HfSiO}_{x}$, and SiON p-MOSFETs Using UF-OTF $I_{rm DLIN}$ Technique

The time, temperature, and oxide-field dependence of negative-bias temperature instability is studied in $hbox{HfO}_{2}/hbox{TiN}$, $ hbox{HfSiO}_{x}/hbox{TiN}$, and SiON/poly-Si p-MOSFETs using ultrafast on-the-fly $I_{rm DLIN}$ technique capable of providing measured degradation from very short (approximately microseconds) to long stress time. Similar to rapid thermal nitrided oxide (RTNO) SiON, $hbox{HfO}_{2}$ devices show very high temperature-independent degradation at short (submilliseconds) stress time, not observed for plasma nitrided oxide (PNO) SiON and $hbox{HfSiO}_{x}$ devices. $hbox{HfSiO}_{x}$ shows lower overall degradation, higher long-time power-law exponent, field acceleration, and temperature activation as compared to $hbox{HfO}_{2}$, which are similar to the differences between PNO and RTNO SiON devices, respectively. The difference between $ hbox{HfSiO}_{x}$ and $hbox{HfO}_{2}$ can be attributed to differences in N density in the $hbox{SiO}_{2}$ IL of these devices.      

High-Performance $hbox{In}_{0.7}hbox{Ga}_{0.3}hbox{As}$ -Channel MOSFETs With High-$kappa$ Gate Dielectrics and $alpha$-Si Passivation

Long and short buried-channel $hbox{In}_{0.7}hbox{Ga}_{0.3}hbox{As}$ MOSFETs with and without $alpha$-Si passivation are demonstrated. Devices with $alpha$-Si passivation show much higher transconductance and an effective peak mobility of 3810 $hbox{cm}^{2}/ hbox{V} cdot hbox{s}$. Short-channel MOSFETs with a gate length of 160 nm display a current of 825 $muhbox{A}/muhbox{m}$ at $V_{g} - V_{t} = hbox{1.6} hbox{V}$ and peak transconductance of 715 $muhbox{S}/muhbox{m}$. In addition, the virtual source velocity extracted from the short-channel devices is 1.4–1.7 times higher than that of Si MOSFETs. These results indicate that the high-performance $hbox{In}_{0.7}hbox{Ga}_{0.3} hbox{As}$-channel MOSFETs passivated by an $alpha$ -Si layer are promising candidates for advanced post-Si CMOS applications.      

Experimental Demonstration of Deeply-Etched SiO$_{2}$ Ridge Optical Waveguides and Devices

Deeply-etched ${hbox{SiO}}_{2}$ optical ridge waveguides are fabricated and characterized. A detailed discussion of the fabrication process (especially for the deep etching process) is presented. The measured propagation losses for the fabricated waveguides with different core widths range from $0.33sim {hbox {0.81}}~{hbox {dB}}/{hbox {mm}}$. The loss is mainly caused by the scattering due to the sidewall roughness. The losses in bending sections are also characterized, which show the possibility of realizing a small bending radius (several tens of microns). 1 $,times {rm N}$ ( ${rm N}=2$, 4, 8) multimode interference couplers based on the deeply-etched ${hbox{SiO}}_{2}$ ridge waveguide are also fabricated and show fairly good performances.      

GaAs MESFET With a High-Mobility Self-Assembled Planar Nanowire Channel

We demonstrate the first metal–semiconductor field-effect transistor with a self-assembled planar $langlehbox{110}rangle$ GaAs nanowire channel. Well-defined dc output and transfer characteristics have been observed with a subthreshold slope of $sim$150 mV/dec, maximum $g_{m}$ of 23 mS/mm, and excellent on-current saturation. Bulklike mobility of $sim! hbox{4100} hbox{cm}^{2}/hbox{V}cdot hbox{s}$ with corresponding electron concentration of $hbox{2.3} cdot hbox{10}^{17} hbox{cm}^{-3}$ is derived by fitting the experimental data using a self-consistent long channel field effect device model.