清管器中的信号发射装置电路设计

为了监测清管器在管线内卡堵位置,在清管器上加装电子信号发射装置,向外界发出电磁脉冲信号。为了克服所发出的信号频率不稳定、节拍通断时间分散性大等缺陷,对发射装置结构、发射装置内部电路、程序等都有严格特殊要求。经过深入的理论研究和测试,制造出了试验样机,该样机圆满的通过了多种环境下的试验并取得了良好的效果。     

清管器(Pig)清洗技术

文章对清管器的结构。性能、应用特点进行了全面分析,并对它在输水管、输油管及工业管线清洗中的应用情况做了具体介绍     

管道清管器电磁跟踪定位系统接收机的设计与实现

介绍了清管器电磁跟踪定位的基本原理。提出了清管器电磁跟踪定位系统接收机的总体方案。研制了低噪声、窄通频带、高精度数据采集电路,实现了微弱磁信号的准确检测。实测表明,所设计的清管器电磁跟踪定位系统接收机,有效跟踪范围可达10米,可以满足油气管道工程实际需求。     

原油管道清洗工程中清洗技术的综合运用

本文通过一个典型工程的施工,分别介绍了管道清洗技术中的清管器技术、高压水射流技术及其各自的主要特点.这些技术的综合运用保证了工程的按期按质完成,以及良好的施工效果.     

电子清管器发射机系统的改进设计

现有的以555芯片产生间断超低频（23Hz左右）电磁脉冲的电子清管器发射机系统会带来频率漂移、各组振荡问的相位关系随机不恒定及静态功耗偏大的问题。为此利用89c2051编程产生间断的超低频脉冲信号,解决了频率漂移及振荡间的相位关系随机的问题。通过采取配置合适的晶振和电源电压措施,并在软件设计部分充分利用单片机休眠模式的低功耗特性,解决了功耗问题。经测试频率稳定在（233-0．01）Hz,振荡间的相位关系恒定。有效工作时间由60h提高至100h。     

恒流源在输油管线冰堵位置测定的应用

北方冬季气温一般在—15℃~—30℃左右,在冰冻期内,脱水不完全或者蜡质过高的油气在输送过程中,部分水或蜡质会在油气管线或气管线内壁凝聚,造成管内介质流动孔径变小,严重时会造成管道局部冰堵,从而导致全线停输,若不能及时处理将会造成巨大的经济损失。以应变片的应力应变特性利用电桥的加减特性,通过检测变送电路在管线加压过程中冰堵位置前后管内介质压力不同,致使冰堵点前后管道变形程度也不同,通过传感器来捕捉冰堵前后管道的变形程度,从而判断冰堵点的位置,是一种相比传统检测方法(如钻孔法、敲击法、理论数值分析法、超声波法等)较为高效的测量方法。     

螺旋弹簧钢丝刷式清管器

介绍了一种螺旋弹簧钢丝刷式清管器专利技术,其设计巧妙,结构简单,清管作业时,清管器在管道内螺旋旋转式推进,其优点有:对管壁上的污垢清理效果好、对皮碗的磨损小且均匀、易于通过弯头处。     

中国电信重庆公司资源管理工作创佳绩

1月16日，中国电信集团公司公布了“2007年网络类固定资产卡实管理数据考核”结果，中国电信重庆公司成为唯一在传输、交换、数据专业固定资产卡实管理数据基本项和动力、管线加分项取得两个满分的省级公司，并获得全集团第一的可喜成绩。     

钴-60后装机放射源驱动电机卡堵检测装置设计

介绍了利用通用的光电装置实现对钴-60后装机放射源卡堵进行检测，使控制系统能够迅速准确地掌握电机状态，做出相关保护处理。硬件电路由光电检测和脉冲检测电路组成，该检测装置结构简单、安全可靠、通用性强，可以推广应用到其他医疗器械的检测当中。     

为什么香港远不如北京堵车严重

现在,在中国大陆的各大城市,堵车基本成了普遍现象。我们的网友还对每个城市的堵车现象做了个总结,简直太形象了!他们把首都叫"首堵",上海是"一上路就堵",广州是"广泛地堵",深圳是"深度地堵",成都是"成天堵",重庆是"重复地堵"……为了治堵,北京出台了摇号购车政策。     

清管器清洗技术--管道工业的重要保障

前言 　　继陆运、水运、空运成为当今社会的三大动脉以后,迅速发展的地下管道运输线,已成为当今社会的第四大动脉.目前.全世界的新建管线正以每年几十万公里的速度发展,人们几乎把钢铁总产量的十分之一用来建造地下管线.……     

Pipeline Reconfigurable FPGAs

While reconfigurable computing promises to deliver incomparable performance, it is still a marginal technology due to the high cost of developing and upgrading applications. Hardware virtualization can be used to significantly reduce both these costs. In this paper we describe the benefits of hardware virtualization, and show how it can be achieved using the technique of pipeline reconfiguration. The result is PipeRench, an architecture that supports robust compilation and provides forward compatibility. Our preliminary performance analysis on PipeRench predicts that it will outperform commercial FPGAs and DSPs in both overall performance and in performance normalized for silicon area over a broad range of problem sizes.     

Pipeline Reconfigurable FPGAs

While reconfigurable computing promises to deliver incomparable performance, it is still a marginal technology due to the high cost of developing and upgrading applications. Hardware virtualization can be used to significantly reduce both these costs. In this paper we describe the benefits of hardware virtualization, and show how it can be achieved using the technique of pipeline reconfiguration. The result is PipeRench, an architecture that supports robust compilation and provides forward compatibility. Our preliminary performance analysis on PipeRench predicts that it will outperform commercial FPGAs and DSPs in both overall performance and in performance normalized for silicon area over a broad range of problem sizes.     

有线电视管道施工与其他管线位置交叉冲突的处理方法

结合工程实践,针对有线电视管道施工中经常碰到的与其他各类管线相互交叉的问题,分析市政管道施工中管道交叉冲突发生的原因,介绍几种处理市政公用管道交叉冲突的工程措施。     

一种支持无符号数的流水线乘法器

文章介绍了一种32×32位的乘法器设计方案。该乘法器采用了改进的Booth算法,增加对无符号数乘法的支持,简化了部分积的符号扩展,使电路结构简洁清晰;使用(4,2)计数器实现Wallace树提高了部分积的归约性能;应用了流水线技术并且具有完整的控制接口。该设计综合考虑了一个高性能通用CPU对定点乘法的要求,作为某CPU定点部件的一部分,在FPGA和ASIC上得到验证。     

Two's Complement Pipeline Multipliers

Digital filters and signal processors when realized in hardware often use serial transfer of data. Multipliers which are capable of accepting variable coefficients and data in sign and magnitude notation and producing serial products of the same length as the input data word have been known for some time. This concise paper addresses the design of multipliers capable of accepting data in 2's complement notation, or both data and coefficients in 2's complement notation. It also considers multiplier recoding techniques, such as the Booth algorithm. Specialized (fixed coefficient) multiplier designs are considered briefly. Finally, multiplier rounding and overflow characteristics are discussed, and a rough comparison is made between the complexity of the various designs.     

Digit-Serial Pipeline Sorter Architecture

This paper presents the VLSI architecture design of pipeline sorter which is suitable for the fast sorting of the continuous serial input data stream. By decomposing the Batcher’s merge-sort process into a network of compare-and-swap (C&S) operations, two different styles of pipeline architectures based on the feedback and feed-forward data shuffling modules can be first achieved. However, both architectures suffer the low hardware utilization due to the discrepancy of input sample rate and internal processing rate. Therefore, this paper further proposes a novel digit-serial pipeline sorter architecture by dividing the data into two sub-words. In addition, the most-significant half-word data are processed first in order to reduce the internal register overhead incurred in the C&S unit. Our experimental results show that about 50% saving of gate counts can be achieved by the digit-serial approach.     

复杂指令集流水线系统设计

摒弃传统流水线设计必须先将复杂指令集指令转化为精简指令集指令,然后再按照精简指令集实现流水线的方法.采用拓展的哈佛结构,设计新型指令流水线前端多指令缓冲和双指令指针,以及流水线中、后端双总线寄存器组和多端口数据存储器,优化指令流水线结构,实现高效率的复杂指令集指令流水线系统.设计从理论上解决了复杂指令集流水线实现的两个难点:寄存器和存储器读写冲突问题,以及流水线各阶段功能和任务划分.VHDL语言建模,用ModelSim和Xilinx仿真、测试,证明复杂指令集流水线系统设计可行.     

Constant Number Serial Pipeline Multipliers

The pipeline form of the serial/parallel multiplier for constant numbers, which operates without insertion of zero words between successive data, is presented. The constant number is in Canonical Signed Digit (CSD) form and the other factor in two's complement form. The CSD form was chosen because it yields significant hardware reduction. Also, for the above data forms the Lyon's serial pipeline multiplier is examined. For these designs, a special algorithm for the multiplication of two's complement numbers with constant numbers in CSD representation was developed. The proposed serial pipeline multipliers are compared with the existing schemes from the point of hardware complexity.     

Pipeline array for square-root extraction

Pipelining an arithmetic process is a well known technique for improving the computation speed of the arithmetic algorithm. In the letter is proposed a pipeline version of the array for the extraction of square roots of binary numbers. It is shown that a significant speed improvement (on a throughout basis) can result by this modification of the conventional logic arrays.