60 GHz monolithic GaAs front-end circuit for receiver applications

A millimetre-wave planar mixer diode compatible with GaAs MESFET based integrated circuit fabrication has been developed. Selective ion implantation was used to optimise the diode and FET doping profiles. A novel feature reported here is the use of a deep implanted buried n+ layer to minimise diode series resistance, yielding diode cutoff frequencies in excess of 500 GHz. Monolithic balanced mixer diodes integrated with an MESFET IF amplifier fabricated by this technique have given 5dB conversion loss at 60 GHz.     

A 31-GHz monolithic GaAs mixer/preamplifier circuit for receiver applications

The portion of a monolithic receiver containing integrated Schottky mixer diodes and MESFET'S with microstrip circuitry has been developed and tested at 31 GHz. This work is part of a program to establish the feasibility of monolithic receivers and transmitters at microwave and millimeter-wave frequencies. Receiver designs using high-cutoff frequency diodes in a mixer configuration followed by a MESFET amplifier are capable of operating from microwave through millimeter-wave frequencies. However, the fabrication of monolithic receiver designs requires the integration on the same wafer of devices with different material requirements. We have developed a compatible integration scheme which is fundamental to the fabrication of monolithic receivers at millimeter-wave frequencies. Fabrication and design considerations for the 31-GHz balanced mixer and IF preamplifier are described. Completed monolithic units typically exhibit a conversion gain of 4 dB from the signal frequency of 31 GHz to the IF frequency of 2 GHz. The associated noise figure is typically 11.5 dB.     

A Ku-band integrated receiver front end

A Ku-band integrated receiver front end has been fabricated on 20-mil aluminum oxide substrates. The receiver consists of a balanced mixer and a Gunn oscillator within an area of 0.300/spl times/0.325 inch. The performance of both packaged and unpackaged microstripline receivers is described. Using external RF tuning, a noise figure of 9 dB at 18 GHz was obtained. A higher Q Gunn oscillator design is needed for more reliable single-frequency operation.     

用于DVB-S信道芯片设计的符号检测

介绍了用于DVB-S信道接收芯片设计的符号检测系统,阐述了数据源的结构,数据同步、码流的实时分析、检测的过程和检测的方法.     

A 30-GHz monolithic receiver

Several monolithic integrated circuits have been developed to make a 30-GHz receiver. The receiver components include a low-noise amplifier, an IF amplifier, a mixer, and a phase shifter. The LNA has a 7-dB noise figure with over 17 dB of associated gain. The IF amplifier has a 13-dB gain with a 30-dB control range. The mixer has a conversion loss of 10.5 dB. The phase shifter has a 180° phase shift control and a minimum insertion loss of 1.6 dB.     

A monolithic micropower command receiver

The use of battery-operated chronically implanted telemetry systems in biomedical instrumentation is growing rapidly. In many cases the flexibility and operating lifetime of these systems is severely limited by the capacity of the power source. Describes the theory of operation, design, fabrication, technology and performance of a micropower command receiver that can extend the operating lifetime of an implanted telemetry system to the shelf life of its battery by disconnecting the power source when the system is not in use. The command receiver consists of an RF amplifier, and AM detector, and an audio amplifier. It has a sensitivity of better than 100 /spl mu/V and a total power dissipation of less than 15 /spl mu/W. It operates from a single 1.35-V mercury cell and is fabricated entirely on a single silicon chip. The only necessary off-the-chip components are the antenna and the battery.     

A monolithic GaAs receiver for optical interconnect systems

A monolithic GaAs optical receiver which includes a photodetector and preamplifier was designed and fabricated using a common 1.0-μm GaAs MESFET technology. The optical receiver operates at the data rate of 1 Gb/s. The transimpedance value can be continuously tuned from 1 to 10 kΩ. The metal-semiconductor-metal photodiode shows a 35% efficiency. Several design factors are considered to achieve high-bandwidth and low-noise operation. An array of the integrated receivers can be compactly implemented in a single chip for high-speed interconnection networks and photonic signal processing     

A monolithic dual tone multifrequency receiver

A fully integrated DTMF receiver has been fabricated on a single CMOS chip requiring only three external passive components. The circuit combines precision filters, zero crossing detectors and amplitude detectors with digital logic. Switched capacitor techniques are used to implement high-pass, bandpass, and bandstop filters. The receiver architecture and circuit implementation are described.     

A monolithic GaAs-on-Si receiver front end for optical interconnectsystems

The authors describe a monolithic technology for integrating GaAs with Si bipolar devices and demonstrate that such integration can provide improved system performance without degrading individual devices. The technology has been used to implement a 1-GHz GaAs/Si optical receiver with an equivalent input noise current density of less than 3 pA/√Hz for midband operation, and less than 4.5 pA/√Hz at 1 GHz. In this receiver an interdigitated GaAs metal-semiconductor-metal (MSM) photodetector is combined with a transimpedance preamplifier fabricated in silicon bipolar technology. The measured dark current of the GaAs/Si photodetector is 7 nA. The measured pulse response of an experimental integrated receiver is less than 550 ps FWHM. The integrated front end provides a wideband, low-noise optical receiver for use in local optical interconnections and demonstrates the successful application of integrated GaAs-on-Si technology to optoelectronics     

A Ku-band high power density AlGaN/GaN HEMT monolithic power amplifier

A high power density monolithic power amplifier operated at Ku band is presented utilizing a 0.3μm AlGaN/GaN HEMT production process on a 2-inch diameter semi-insulating（SI） 4H-SiC substrate by MOCVD. Over the 12-14 GHz frequency range,the single chip amplifier demonstrates a maximum power of 38 dBm（6.3 W）, a peak power added efficiency（PAE） of 24.2%and linear gain of 6.4 to 7.5 dB under a 10%duty pulse condition when operated at V_ds = 25 V and V_gs = -4 V.At these power levels,the amplifier exhibits a power density in excess of 5 W/mm.     

一个Ku波段高功率密度AlGaN/GaN HEMTs单片集成功率放大器

本文报道了一款工作于Ku波段的高功率密度单片集成功率放大器。该放大器采用金属有机化学气相淀积技术在2英寸半绝缘 4H-SiC衬底上生长0.2um AlGaN/GaN HEMTs工艺制作而成。在10%占空比的脉冲偏置Vds=25V,Vgs=-4V条件下,该单片放大器在12-14GHz频率范围内得到最大输出功率38dBm(6.3W),最高PAE 24.2%和线性增益6.4到7.5dB。以这种功率水平而论,该放大器的功率密度超过5W/mm。     

Eight-channel p-i-n/HBT monolithic receiver array at 2.5 Gb/s perchannel for WDM applications

We report a monolithic chip incorporating an eight channel p-i-n/HBT photoreceiver array designed for multichannel WDM applications. The p-i-n photodetectors are edge illuminated and centered at a 250 μm pitch for mating with either ribbon fiber connectors or waveguide demultiplexers. Each channel operates at 2.5 Gb/s with an electrical crosstalk of -20 dB between adjacent channels. The average sensitivity of each receiver in the array was measured to be (-20±1) dBm for a bit error rate of 10^-9 at a wavelength of 1.5 μm     

A monolithic quad line driver for industrial applications

The device described in this paper is a new quad line driver to be used in the hostile and noisy industrial environment and developed in mixed technology (BCD: Bipolar, CMOS, DMOS). It consists of four independent line drivers, each of which has a rail-to-rail push-pull output stage realized with power DMOS transistors connected in half bridge configuration. Even though the device is designed to be used primarily in the output cards of programmable controllers, it is a general purpose device, since it can drive any kind of load (resistive, capacitive, or inductive) with an output current of 100 mA. The novel structure of the top driver allows full protection of the output stage against any kind of short circuits and/or overloads, providing a linear current limitation. Furthermore, when a channel is tristated, for every applied voltage ranging from ground to the supply voltage, virtually zero current is absorbed from the output. An innovative high efficiency central charge pump circuit has also been designed and implemented, making both a very wide supply voltage operation (6-50 V) and high switching frequency (up to 500 KHz) possible, The device can also be used as a receiver since the input voltage can swing from -10-50 V     

A CMOS monolithic amplifier for cardiac EIT applications

Analog Integrated Circuits and Signal Processing - This paper presents a low-noise amplifier (LNA) with superior linearity for ultra-wideband (UWB) purposes. Linearity is a significant parameter...     

A versatile monolithic IC building-block for light-sensing applications

An all-bipolar building-block consisting of a linear light-to-current converter, a voltage comparator, and a voltage reference has been developed. This new general purpose IC combines the advantages of silicon photodiode light sensors with the linear signal processing capability of bipolar integrated transistors. In achieving this marriage, new circuit techniques were developed in order to operate at the very low current levels (<1 nA) and over the wide dynamic range of the light input. Besides their normal sensory function, photodiodes were made to serve as active elements in the circuit, taking part in biasing and acting as active loads in circuits that operate entirely on photocurrents. Use of these techniques boosted overall performance and eliminated the need for a light shield over the active-device portion of the die.     

A 50-Mbit/s CMOS monolithic optical receiver

A general-purpose CMOS optical receiver that operates at data rates from 1 to 50 Mb/s has been fabricated in a 1.75-μm CMOS process. The technology choice resulted in a high level of integration compared with similar bipolar technology receivers. The measured minimum signal current for a 10^-9 bit error rate at 50 Mb/s is 48-nA r.m.s. Automatic gain control gives the receiver an electrical input dynamic range of greater than 60 dB. The outputs are TTL (transistor-transistor logic)-compatible and the chip dissipates less than 500 mW when switching at maximum speed. The die area is 16 mm² . A comprehensive noise analysis of the receiver front end provides insight into the design tradeoffs of optical receiver preamplifiers. A wideband precision amplifier used in the linear channel is discussed in detail. A simple method for recovering low-frequency signal information lost in AC coupling is described     

A 1.9-GHz silicon receiver with monolithic image filtering

A 1.9-GHz fully monolithic silicon superheterodyne receiver front-end is presented; it consists of a low noise amplifier (LNA), a tunable image reject filter, and a Gilbert cell mixer integrated in one die. The receiver was designed to operate with a 1.9-GHz RF and a 2.2-GHz local oscillator (LO) for a 300-MHz IF. Two chip versions were fabricated on two different fabrication runs using a 0.5-μm bipolar technology with 25 GHz transit frequency (f_T). Measured performance for the receiver front-end version 1, packaged and without input matching, was: conversion gain 33.5 dB, noise figure 4.9 dB, input IP3 -28 dBm, image rejection 53 dB (tuned to reject a 2.5-GHz image frequency), and 15.9 mA current consumption at +3 V. The image rejection was tunable from 2.4-2.63 GHz by means of an on-chip varactor. Version 2 had increased mixer degeneration for improved linearity. Its measured performance for the packaged receiver with its input matched to 50 Ω was: conversion gain 24 dB, noise figure 4.8 dB, input IP3 -19 dBm, and 65 dB image rejection for a 2.5-GHz image with an image tuning range from 2.34-2.55 GHz     

A low-power all-digital FSK receiver for space applications

A frequency-shift keying (FSK) receiver has been designed for deep space applications which exhibits potential for ultra low power performance. The receiver is based on a novel, almost all-digital architecture. It supports a wide range of data rates and is very robust against large and fast frequency offsets due to Doppler. The architecture utilizes subsampling and 1-bit data processing together with a discrete Fourier transform-based detection scheme to enable power consumption dramatically lower than implementations reported in the literature. Novel and power-efficient algorithms are derived for frequency and timing tracking. Most of the power saving techniques are applicable to a variety of applications, but some are achieved by taking advantage of the asymmetric power constraints for the receiver and the transmitter as well as the absence of adjacent channel interferers. The worst-case bit-error rate (BER) performance of the receiver is just 2.5 dB below that of the optimal uncoded noncoherent FSK receiver at a BER of 10^-6 and better for lower BERs     

A 1.2 mW RDS receiver for portable applications

A 0.9 V 1.2 mA fully integrated radio data system (RDS) receiver for the 88-108 MHz FM broadcasting band is presented. Requiring only a few external components (matching network, VCO inductors, loop filter components), the receiver, which has been integrated in a standard digital 0.18 /spl mu/m CMOS technology, achieves a noise figure of 5 dB and a sensitivity of -86dBm. The circuit can be configured and the RDS data retrieved via an I/sup 2/C interface so that it can very simply be used as a peripheral in any portable application. A 250 kHz low-IF architecture has been devised to minimize the power dissipation of the baseband filters and FM demodulator. The frequency synthesizer consumes 250 /spl mu/A, the RF front-end 450 /spl mu/A while providing 40 dB of gain, the baseband filter and limiters 100 /spl mu/A, and the FM and BPSK analog demodulators 300 /spl mu/A. The chip area is 3.6 mm/sup 2/.     

基于ST5105的数字卫星接收机的设计与实现

结合数字卫星广播电视系统的基本原理和发送端信号处理的基本过程,阐述了数字卫星接收机的工作原理,介绍了MPEG-2解码芯片ST5105的功能和结构特点,并给出了基于该芯片的数字卫星接收机的总体设计与实现。