3D封装及其最新研究进展

介绍了3D封装的主要形式和分类。将实现3D互连的方法分为引线键合、倒装芯片、硅通孔、薄膜导线等,并对它们的优缺点进行了分析。围绕凸点技术、金属化、芯片减薄及清洁、散热及电路性能、嵌入式工艺、低温互连工艺等,重点阐述了3D互连工艺的最新研究成果。结合行业背景和国内外专家学者的研究,指出3D封装主要面临的是散热和工艺兼容性等问题,提出应尽快形成统一的行业标准和系统的评价检测体系,同时指出对穿透硅通孔(TSV)互连工艺的研究是未来研究工作的重点和热点。     

3D封装的发展动态与前景

3D封装是手机等便携式电子产品小型化和多功能化的必然产物。3D封装有两种形式,芯片堆叠和封装堆叠。文章介绍了芯片堆叠和封装堆叠的优缺点、关键技术、最新动态和发展前景。     

3D封装与硅通孔(TSV)工艺技术

在IC制造技术受到物理极限挑战的今天,3D封装技术越来越成为了微电子行业关注的热点。对3D封装技术结构特点、主流多层基板技术分类及其常见键合技术的发展作了论述,对过去几年国际上硅通孔（TSV）技术发展动态给与了重点的关注。尤其就硅通孔关键工艺技术如硅片减薄技术、通孔制造技术和键合技术等做了较详细介绍。同时展望了在强大需求牵引下2015年前后国际硅通孔技术进步的蓝图。     

堆叠封装技术进展

目前电子产品正朝着高集成化、多功能及微型化方向不断发展。堆叠封装(PoP)作为一种新型3D封装技术,在兼容现有的标准表面贴装技术(SMT)的基础上能够实现不同集成电路在垂直方向上堆叠,从而能够提升封装密度,节省PCB板组装空间,缩短互连线路长度。该技术已从初期的低密度双层堆叠发展至当前的高密度多层堆叠,并在互连方式与塑封形式等封装结构及工艺上不断改进,以适应高性能电子产品的发展需求。通过对PoP上层与下层封装体结构及其封装工艺的近期研究成果进行综述,对比分析它们的各自特点与优势,并展望PoP未来发展趋势。     

3D堆叠技术及TSV技术

介绍了3D堆叠技术及其发展现状,探讨了W2W(Wafer to wafer)及D2W(Die to wafer)等3D堆叠方案的优缺点,并重点讨论了垂直互连的穿透硅通孔TSV(Through silicon via)互连工艺的关键技术,探讨了先通孔、中通孔及后通孔的工艺流程及特点,介绍了TSV的市场前景和发展路线图。3D堆叠技术及TSV技术已经成为微电子领域研究的热点,是微电子技术及MEMS技术未来发展的必然趋势,也是实现混合集成微系统的关键技术之一。     

含TSV结构的3D封装多层堆叠Cu/Sn键合技术

研究了利用Cu/Sn对含硅通孔(TSV)结构的多层芯片堆叠键合技术。采用刻蚀和电镀等工艺,制备出含TSV结构的待键合芯片,采用扫描电子显微镜(SEM)对TSV形貌和填充效果进行了分析。研究了Cu/Sn低温键合机理,对其工艺进行了优化,得到键合温度280℃、键合时间30 s、退火温度260℃和退火时间10 min的最佳工艺条件。最后重点分析了多层堆叠Cu/Sn键合技术,采用能谱仪(EDS)分析确定键合层中Cu和Sn的原子数比例。研究了Cu层和Sn层厚度对堆叠键合过程的影响,获得了10层芯片堆叠键合样品。采用拉力测试仪和四探针法分别测试了键合样品的力学和电学性能,同时进行了高温测试和高温高湿测试,结果表明键合质量满足含TSV结构的三维封装要求。     

堆叠硅片互联FPGA突破摩尔定律

赛灵思日前正式在全球发布其堆叠硅片互联技术,旨在超越摩尔定律的束缚。在赛灵思启动目标设计平台战略时,他们提到要进行统一架构的产品路线。而该公司不久前推出的7系列FPGA     

一种3D堆叠集成电路中间绑定测试时间优化方案

中间绑定测试能够更早地检测出3D堆叠集成电路绑定过程引入的缺陷,但导致测试时间和测试功耗剧增.考虑测试TSV、测试管脚和测试功耗等约束条件,采用整数线性规划方法在不同的堆叠布局下优化中间绑定测试时间.与仅考虑绑定后测试不同,考虑中间绑定测试时,菱形结构和倒金字塔结构比金字塔结构测试时间分别减少4.39%和40.72%,测试TSV增加11.84%和52.24%,测试管脚减少10.87%和7.25%.在测试功耗约束下,金字塔结构的测试时间增加10.07%,而菱形结构和倒金字塔结构测试时间只增加4.34%和2.65%.实验结果表明,菱形结构和倒金字塔结构比金字塔结构更具优势.     

先进的叠层式3D封装技术及其应用前景

采用叠层3D封装技术将使芯片所包含晶体管数目成倍的增加,它不但具有体积小、性能高、功耗低等优点,而且拥有无可比拟的封装效率.对其叠层3D封装的发展趋势、技术特点、技术优势、散热问题以及应用前景等几个方面进行了探讨.     

射频系统2.5D/3D封装结构的研究进展

射频系统封装已经成为无线通信系统重要的集成技术,对于不断向高速率、小型化、多功能方向发展的无线通信系统,先进射频系统封装结构为其提供了坚实的基础.介绍了2.5D/3D射频系统封装结构的研究进程,重点分析了中介层结构、埋入结构、堆叠结构中的关键工艺,并从信号传输、电磁干扰、结构集成度等多角度出发,对不同封装结构做了深入剖...     

三维集成封装中的TSV互连工艺研究进展

为顺应摩尔定律的增长趋势,芯片技术已来到超越"摩尔定律"的三维集成时代。电子系统进一步小型化和性能提高,越来越需要使用三维集成方案,在此需求推动下,穿透硅通孔(TSV)互连技术应运而生,成为三维集成和晶圆级封装的关键技术之一。TSV集成与传统组装方式相比较,具有独特的优势,如减少互连长度、提高电性能并为异质集成提供了更宽的选择范围。三维集成技术可使诸如RF器件、存储器、逻辑器件和MEMS等难以兼容的多个系列元器件集成到一个系统里面。文章结合近两年的国外文献,总结了用于三维集成封装的TSV的互连技术和工艺,探讨了其未来发展方向。     

叠层式片状电感器的设计

采用铁氧体材料和多层厚膜印刷技术，把铁氧体膜片和导电浆料相间印刷、叠合起来，经过热压、切割，烧制成一体化的闭磁路螺旋管状磁芯线圈，具有矩形微型、封闭磁路、独石结构的特点。     

应用于三维封装中的硅通孔技术

随着集成电路日新月异的发展,当半导体器件工艺进展到纳米级别后,传统的二维领域封装已渐渐不能满足电路高性能、低功耗与高可靠性的要求。为解决这一问题,三维封装成为了未来封装发展的主流。文章简要介绍了三维封装的工艺流程,并重点介绍了硅通孔技术的现阶段在CSP领域的应用,以及其未来的发展方向。     

Copper plating for 3D interconnects

In this paper we report on Cu plating of through-silicon-vias (TSV-s) using in-house made acidic Cu bath with model additives (SPS, PEG, and JGB). Although the model additives might not be as potent as commercial additives, they have been studied in detail, and their role in Cu plating has been described extensively in scientific literature. This in turn allows deeper insight into how changes in bath composition affect the plating mechanism and Cu via-fill.     

用于3D封装的带TSV的超薄芯片新型制作方法

提出了一种应用于3D封装的带有硅通孔(TSV)的超薄芯片的制作方法。具体方法为通过刻蚀对硅晶圆打孔和局部减薄,然后进行表面微加工,最后从硅晶圆上分离出超薄芯片。利用两种不同的工艺实现了TSV的制作和硅晶圆局部减薄,一种是利用深反应离子刻蚀(DRIE)依次打孔和背面减薄,另一种是先利用KOH溶液湿法腐蚀局部减薄,再利用DRIE刻蚀打孔。通过实验优化了KOH和异丙醇(IPA)的质量分数分别为40%和10%。这种方法的优点在于制作出的超薄芯片翘曲度相较于CMP减薄的小,而且两个表面都可以进行表面微加工,使集成度提高。利用这种方法已经在实验室制作出了厚50μm的带TSV的超薄芯片,表面粗糙度达到0.02μm,并无孔洞地电镀填满TSV,然后在两面都制作了凸点,在表面进行了光刻、溅射和剥离等表面微加工工艺。实验结果证实了该方法的可行性。     

RF characterization and modelling of high density Through Silicon Vias for 3D chip stacking

3D integration including Through Silicon Vias is more and more considered as the solution to overcome conventional 2D IC issues. In this way, TSV analytical equivalent models are hardly required to achieve 3D products and to make design recommendations. In this paper, a 3D process flow is detailed and used to integrate specific RF structures including copper-filled TSVs with 3 μm wide and 15 μm deep dimensions. Both measurements and simulations of these structures lead to the extraction of frequency-dependent parameters and the building of a SPICE compatible π-shaped analytical parametrical model of the TSV.     

Fast thermal analysis for fixed-outline 3D floorplanning

Three dimensional integrated circuits (3D ICs) can alleviate the problem of interconnection, a critical problem in the nanoscale era, and are also promising for heterogeneous integration. However, the thermal challenge in industry is one of key obstacles to adopt the 3D ICs technology. Various thermal analysis models for 3D IC have been proposed in literature. However, the long simulation cycle makes runtime of thermal management inefficient during floorplanning phase. In this paper, we propose a fast thermal analysis method for fixed-outline 3D floorplanning. Before floorplanning, we simulate the thermal distribution of each block placed on different positions. Based on the simulated thermal profiles, bilinear interpolation is adopted to quickly estimate temperature during floorplanning. After the block planning, a heuristic method, which combines the shortest path and min-cost-max-flow, is presented for TSV allocation with minimization of chip temperature and wirelength. Compared with the superposition of thermal profiles method, the proposed thermal analysis method can reduce the peak temperature by 6.7% on average with short runtime for 3D fixed-outline floorplanning, which demonstrates the efficiency and effectiveness of the proposed thermal analysis method.     

Compact model to efficiently characterize TSV-to-transistor noise coupling in 3D ICs

A methodology is proposed to characterize through silicon via (TSV) induced noise coupling in three-dimensional (3D) integrated circuits. Different substrate biasing schemes (such as a single substrate contact versus regularly placed substrate contacts) and TSV fabrication methods (such as via-first and via-last) are considered. A compact π model is proposed to efficiently estimate the coupling noise at a victim transistor. Each admittance within the compact model is approximated with a closed-form expression consisting of logarithmic functions. The methodology is validated using the 3D transmission line matrix (TLM) method, demonstrating, on average, 4.8% error. The compact model and the closed-form expressions are utilized to better understand TSV induced noise as a function of multiple parameters such as TSV type, placement of substrate contacts, signal slew rate and voltage swing. The effect of differential TSV signaling is also investigated. Design guidelines are developed based on these results.     

Clock Mesh Network Design with Through‐Silicon Vias in 3D Integrated Circuits

Many methodologies for clock mesh networks have been introduced for two‐dimensional integrated circuit clock distribution networks, such as methods to reduce the total wirelength for power consumption and to reduce the clock skew variation through consideration of buffer placement and sizing. In this paper, we present a methodology for clock mesh to reduce both the clock skew and the total wirelength in three‐dimensional integrated circuits. To reduce the total wirelength, we construct a smaller mesh size on a die where the clock source is not directly connected. We also insert through‐silicon vias (TSVs) to distribute the clock signal using an effective clock TSV insertion algorithm, which can reduce the total wirelength on each die. The results of our proposed methods show that the total wirelength was reduced by 12.2%, the clock skew by 16.11%, and the clock skew variation by 11.74%, on average. These advantages are possible through increasing the buffer area by 2.49% on the benchmark circuits.