Mismatch shaping for a current-mode multibit delta-sigma DAC

Mismatch shaping allows the use of multibit quantization in delta-sigma analog-to-digital converters and digital-to-analog converters (DAC's) since it noise-shapes the error caused by static element mismatch in a multibit DAC. In this paper, mismatch-shaping techniques for low-pass delta-sigma (ΔΣ) modulators are reviewed, and a mismatch-shaping technique for bandpass ΔΣ modulators is described. The dynamic error caused by frequent element switching is identified as a major source of error in a current-mode DAC with a continuous-time output. Modifying the mismatch-shaping algorithm to account for this effect yields a continuous-time ΔΣ DAC that is insensitive to both element mismatch and element switching dynamics. Experimental results confirm the effectiveness of the proposed techniques     

Architecture, design, and test of continuous-time tunableintermediate-frequency bandpass delta-sigma modulators

This paper examines the architecture, design, and test of continuous-time tunable intermediate-frequency (IF) fourth-order bandpass delta-sigma (BP ΔΣ) modulators. Bandpass modulators sampling at high IFs (~100 MHz) allow direct sampling of the RF signal-reducing analog hardware and make it easier to realize completely software programmable receivers. This paper presents circuit design of and test results from continuous-time fourth-order BP ΔΣ modulators fabricated in AlInAs/GaInAs heterojunction bipolar technology with a peak unity current gain cutoff frequency (f_T) of 80 GHz and a maximum frequency of oscillation (f_MAX) of about 130 GHz. Operating from ±5-V power supplies, a fabricated 180-MHz IF fourth-order ΔΣ modulator sampling at 4 GS/s demonstrates stable behavior and achieves 75.8 dB of signal-to-(noise+distortion)-ratio (SNDR) over a 1-MHz bandwidth. Narrowband performance (~1 MHz) performance of these modulators is limited by thermal/device noise while broadband performance (~60 MHz), is limited by quantization noise. The high sampling frequency (4 GS/s) in this converter is dictated by broadband (60 MHz) performance requirements     

Granular quantization noise in the first-order delta-sigmamodulator

A unified approach to analyzing the granular quantization error of the first-order ΔΣ modulator is presented. The approach handles many of the previously analyzed input sequences in addition to a large class of new input sequences. By averaging over the arbitrarily small amount of circuit noise assumed to be present at the analog input to the ΔΣ modulator, a simple expression for the autocorrelation of the quantization error is derived. Each term in the expression is formally equal to the quantization error of a nonoverloaded uniform quantizer operating upon a finite partial sum of consecutive input sequence samples. Hence, existing results concerning uniform quantizers are directly applicable in evaluating the autocorrelation expression for specific input sequences. The theory is also applicable to deterministic input sequences, and has been applied to obtain a new closed-form result for sinusoidal input sequences. Ergodic results which assert that, under mild conditions, the autocorrelation equals the time-average autocorrelation in probability are presented     

A 10.7-MHz IF-to-baseband ΣΔ A/D conversion system forAM/FM radio receivers

ΣΔ modulation with integrated quadrature mixing is used for analog-to-digital (A/D) conversion-of a 10.7-MHz IF input signal in an AM/FM radio receiver. After near-zero IF mixing to a 165 kHz offset frequency, the I and Q signals are digitized by two fifth-order, 32 times oversampling continuous-time ΣΔ modulators. A prototype IC includes digital filters for decimation and the shift of the near-zero-IF to dc. The baseband output signal has maximum carrier-to-noise ratios of 94 dB in 9 kHz (AM) and 79 dB in 200 kHz (FM), with 97 and 82 dB dynamic range, respectively. The IM3 distance is 84 dB at full-scale A/D converter input signal. Including downconversion and decimation filtering, the IF A/D conversion system occupies 1.3 mm² in 0.25-μm standard digital CMOS. The ΣΔ modulators consume 8 mW from a 2.5-V supply voltage, and the digital filters consume 11 mW     

Design and realization of a digital ΔΣ modulator forfractional-n frequency synthesis

The basic operation of a fractional-n frequency synthesizer has been published, but to date little has been presented on the digital ΔΣ modulators which are required to drive such synthesizers. This paper provides a tutorial overview, which relates digital ΔΣ modulation to other applications of ΔΣ modulation where the literature is more complete. The paper then presents a digital ΔΣ modulator architecture which is economical and efficient and which is practical to realize with commercially available components in comparison with other possible implementations which require extensive custom very large-scale integration (VLSI). A demonstration is made of a 28-b modulator using the architecture presented, which provides a 25-MHz tuning bandwidth and <1-Hz frequency resolution. The modulator is demonstrated in an 800-MHz frequency synthesizer having phase noise of -90 dBC/Hz at a 30-kHz offset     

Quadrature bandpass ΔΣ modulation for digital radio

A quadrature bandpass ΔΣ modulator IC facilitates monolithic digital-radio-receiver design by allowing straightforward “complex A/D conversion” of an image reject mixer's I and Q, outputs. Quadrature bandpass ΔΣ modulators provide superior performance over pairs of real bandpass ΔΣ modulators in the conversion of complex input signals, using complex filtering embedded in ΔΣ loops to efficiently realize asymmetric noise-shaped spectra. The fourth-order prototype IC, clocked at 10 MHz, converts narrowband 3.75-MHz I and Q inputs and attains a dynamic range of 67 dB in 200-kHz (GSM) bandwidth, increasing to 71 and 77 dB in 100- and 30-kHz bandwidths, respectively. Maximum signal-to-noise plus distortion ratio (SNDR) in 200-kHz bandwidth is 62 dB. Power consumption is 130 mW at 5 V. Die size in a 0.8-μm CMOS process is 2.4×1.8 mm²      

A GMSK modulator using a ΔΣ frequencydiscriminator-based synthesizer

This paper describes a new transmitter architecture suitable for wideband GMSK modulation. The technique uses direct modulation of ΔΣ frequency discriminator (ΔΣFD)-based synthesizer to produce the modulated RF signal without any up-conversion. Digital equalization is used to extend the modulation data rate far beyond the synthesizer closed-loop BW. A prototype 1.9-GHz GSM transmitter was constructed consisting of a ΔΣFD-based synthesizer and a digital transmit filter. The synthesizer consists of an 0.8-μm BiCMOS ΔΣFD chip, a digital signal processor FPGA, and an off-chip D/A converter, filter, and VCO. Measured results, using 271-kbit/s GSM modulation, demonstrate data rates well in excess of the 30-kHz synthesizer closed-loop BW are possible with digital equalization. Without modulation, the synthesizer exhibits a -76-dBc spurious noise level and a close-in phase noise of -74 dBc/Hz     

Multibit oversampled ΣΔ A/D converters as front end forCD players

A technique is presented for deriving all of the different control signals needed for focusing and radial tracking in a digital servosystem for compact disc (CD) players, as well as the full band data from the disc. Because of the different natures of all those signals, different bandwidth and dynamic range, complex analog anti-aliasing circuits, and several types of A/D (analog-to-digital) converters would normally be required to convert the signals from the analog to digital domain. With the proposed technique it is possible to carry out the conversion of the high-frequency data as well as the low-frequency control signals with only a single type of multibit sigma-delta (ΣΔ) A/D converter in combination with digital signal processing. The use of ΣΔ type A/D conversion also has other advantages such as its suitability for integration in a CMOS VLSI process and the fact that the requirements for the anti-aliasing filters in front of the converters are relaxed due to the oversampling technique     

A low oversampling ratio 14-b 500-kHz ΔΣ ADC with aself-calibrated multibit DAC

Delta-sigma (ΔΣ) analog-to-digital converters (ADC's) rely on oversampling to achieve high-resolution. By applying multibit quantization to overcome stability limitations, a circuit topology with greatly reduced oversampling requirements is developed. A 14-bit 500-kHz ΔΣ ADC is described that uses an oversampling ratio of only 16. A fourth-order embedded modulator, four-bit quantizer, and self-calibrated digital-to-analog converter (DAC) are used to achieve this performance. Although the high-order embedded architecture was previously thought to be unstable, it is shown that with proper design, a robust system can be obtained. Circuit design and implementation in a 1.2-μm CMOS process are presented. Experimental results give a dynamic range of 84 dB with a sampling rate of 8 MHz and oversampling ratio of 16. This is the lowest oversampling ratio for this resolution and bandwidth achieved to date     

A 2.5-V sigma-delta modulator for broadband communicationsapplications

Oversampled sigma-delta (EA) modulators offer numerous advantages for the realization of high-resolution analog-to-digital (A/D) converters. This paper explores how oversampling and feedback can be employed in high-resolution ΣΔ modulators to extend the signal bandwidth into the range of several megahertz when the oversampling ratio is constrained by technology limitations. A 2-2-1 cascaded multibit architecture suitable for operation from a 2.5-V power supply is presented, and a linearization technique referred to as partitioned data weighted averaging is introduced to suppress in-band digital-to-analog converter (DAC) errors. An experimental prototype based on the proposed topology has been integrated in a 0.5-μm double-poly triple-metal CMOS technology. Fully differential double-sampled switched-capacitor integrators enable the modulator to achieve 95-dB dynamic range at a 4-Msample/s Nyquist conversion rate with an oversampling ratio of 16. The experimental modulator dissipates 150 mW from a 2.5-V supply     

A delta-sigma PLL for 14-b, 50 kSample/s frequency-to-digitalconversion of a 10 MHz FM signal

In many wireless applications, it is necessary to demodulate and digitize frequency or phase modulated signals. Most commonly, this is done using separate frequency discrimination and analog-to-digital (A/D) conversion. In low-cost IC technologies, such as CMOS, precise analog frequented discrimination is not practical, so the A/D conversion is usually performed in quadrature or at a nonzero intermediate frequency (IF) with digital frequency discrimination. While practical, the approach tends to require complicated A/D converters, and accuracy is usually limited by the duality of the A/D conversion. This paper presents an alternative structure, referred to as a delta-sigma frequency-to-digital converter (ΔΣFDC), that simultaneously performs frequency demodulation and digitization. The ΔΣFDC is shown to offer high-precision performance with very low analog complexity. A prototype of the key component of the ΔΣFDC has been fabricated in a 0.6 μm, single-poly, CMOS process. The prototype achieved 50 kSample/s frequency-to-digital conversion of a 10 MHz frequency-modulated signal with a worst case signal-to-noise-and-distortion ratio of 85 dB and a worst case spurious-free dynamic range of 88 dH     

A CMOS analog front-end circuit for an FDM-based ADSL system

A CMOS analog front-end circuit for an FDM-based ADSL system is presented. The circuit contains all analog functions including AGC amplifiers, continuous-time band pass filters, ΣΔ AD/DA converters, and digital decimation and interpolation filters. On-chip automatic tuning of the bandpass filters provides more than 300% center frequency range with 1% frequency accuracy. The higher-order ΣΔ AD/DA converters achieve 12-b data conversion at 1.54 Msamples/s with an oversampling ratio of only 32. The 0.7 μm CMOS circuit measures 65 mm² and consumes 1.9 W from a single 5 V power supply     

Triangularly weighted zero-crossing detector providingΣΔ frequency-to-digital conversion

It is shown that for delta-sigma (ΣΔ) frequency-to-digital conversion (FDC) there is no need for a ΣΔ modulator, since a limited FM signal itself may be considered as an asynchronous ΣΔ bit-stream. By feeding the limited FM signal directly to a sinc² ΣΔ decimator, a triangularly weighted zero-crossing counter FDC is introduced, providing ΣΔ noise shaping. The results measured confirm the theory     

Use of sigma-delta modulation to control EMI from switch-mode powersupplies

Conducted electromagnetic interference (EMI) is a major cause of concern in switch-mode power supplies (SMPSs) which commonly use standard pulsewidth modulation (PWM). In this paper, sigma-delta (ΣΔ) modulation is proposed as an alternative switching technique to reduce conducted EMI from an SMPS. The result of using ΣΔ modulation is a spread in the spectrum of the conducted emissions so that large concentrations of power at discrete frequencies are avoided. Experimental time-domain waveforms and spectra of the switching function of first-order and second-order ΣΔ modulators are presented to prove the viability of the scheme for EMI mitigation. These modulators are then applied to a DC-DC converter in an off-the-shelf computer power supply and experimental results show a reduction of roughly 5-10 dB·μV in EMI emissions over standard PWM modulators     

Digital detection of instability of higher order bandpasssigma-delta converters

A digital method of stabilising higher order sigma-delta converters is presented. Results are given for a third order bandpass ΣΔ converter with three continuous time LC filters tuned to 1/4 of clock frequency f_c     

Optimal decoding for data acquisition applications of sigma deltamodulators

A class of optimal nonlinear decoding algorithms is proposed for data acquisition applications of sigma-delta (ΣΔ) modulators. The technique is applicable to all current ΣΔ structures, including single and double-loop, cascade, and interpolative modulators. While the performance of the technique is identical to that of other optimal nonlinear decoding schemes such as table lookup, it is considerably simpler to implement. Numerical results are presented to compare its performance to that of linear decoders. Effects of circuit imperfections on performance are examined     

An 18-mW 2.5-GHz/900-MHz BiCMOS dual frequency synthesizer with<10-Hz RF carrier resolution

A 2.5-GHz/900-MHz dual fractional-N/integer-N frequency synthesizer is implemented in 0.35-μm 25-GHz BiCMOS. A ΔΣ fractional-N synthesizer is employed for RF channels to have agile switching, low in-band noise, and fine frequency resolution. Implementing two synthesizers with an on-chip ΔΣ modulator in a small package is challenging since the modulator induces substantial digital noise. In this work, several design aspects regarding noise coupling are considered. The fractional-N synthesizer offers less than 10-Hz frequency resolution having the in-band noise contribution of -88 dBc/Hz for 2.47-GHz output frequency and -98 dBc/Hz for 1.15-GHz output frequency, both measured at 20-kHz offset frequency. The prototype dual synthesizer consumes 18 mW with 2.6-V supply     

标准数字工艺下16位精度低压低功耗ΣΔ模数调制器设计

针对输入信号频率在20 Hz～24 kHz范围的音频应用,该文采用标准数字工艺设计了一个1.2 V电源电压16位精度的低压低功耗ΣΔ模数调制器。在6 MHz采样频率下,该调制器信噪比为102.2 dB,整个电路功耗为2.46 mW。该调制器采用一种伪两级交互控制的双输入运算放大器构成各级积分器,在低电源电压情况下实现高摆率高增益要求的同时不会产生更多功耗。另外,采用高线性度、全互补MOS耗尽电容作为采样、积分电容使得整个电路可以采用标准数字工艺实现,从而提高电路的工艺兼容性、降低电路成本。与近期报道的低压低功耗ΣΔ模数调制器相比,该设计具有更高的品质因子FOM。     

CMOS oversampling ΔΣ magnetic-to-digital converters

In this paper, two CMOS oversampling delta-sigma (ΔΣ) magnetic-to-digital converters (MDCs) are proposed. The first MDC consists of the magnetic operational amplifier (MOP) and a first-order switched-capacitor (SC) ΔΣ modulator. The second one directly uses the MOP to realize a first-order SC ΔΣ modulator. They can convert the external magnetic field into digital form. Both circuits were fabricated in a 0.5-μm CMOS double-poly double-metal (DPDM) process and operated at a 5-V supply voltage and the nominal sampling rate of 2.5 MHz. The dynamic ranges of these converters are at least ±100 mT. The gain errors within ±100 mT are less than 3% and the minimum detectable magnetic field can reach as small as 1 mT. The resolutions are 100 μT for both of the two MDCs. The measured sensitivities are 1.327 mv/mT and 0.45 mv/mT for the first and the second MDC, respectively