NASA ground terminal communication equipment: Automated fault isolation expert systems

This paper describes the prototype expert systems that diagnose the Distribution and Switching System I and II (DSS1 and DSS2), Statistical Multiplexers (SM), and Multiplexer and Demultiplexer systems (MDM) at the NASA Ground Terminal (NGT) located at White Sands, New Mexico. A system-level fault isolation expert system monitors the activities of a selected data stream, verifies that the fault exists in the NGT and identifies the faulty equipment. Equipment-level fault isolation expert systems will be invoked to isolate the fault to a Line Replaceable Unit (LRU) level. Input and sometimes output data stream activities for the equipment are available. The system-level fault isolation expert system will compare the equipment input and output status for a data stream and perform loopback tests (if necessary) to isolate the faulty equipment. The equipment-level fault isolation system utilizes the process of elimination and/or the maintenance personnel's fault isolation experience stored in its knowledge base. The DSS1, DSS2, and SM fault isolation systems, using the knowledge of the current equipment configuration and the equipment circuitry, will issue a set of test connections according to the predefined rules. The faulty component or board can be identified by the expert system by analyzing the test results. The MDM fault isolation system correlates the failure symptoms with the faulty component based on maintenance personnel experience. The faulty component can be determined by knowing the failure symptoms.

The NGT fault isolation prototype is implemented in Prolog, C, and VP-Expert, on an IBM AT compatible workstation. The DSS1, DSS2, SM, and MDM equipment simulators are implemented in PASCAL. The equipment simulator receives connection commands and responds with status for the expert system according to the assigned faulty component in the equipment. The DSS1 fault isolation expert system was converted to C language from VP-Expert and integrated into the NGT automation software for offline switch diagnoses.

Potentially, the NGT fault isolation algorithms can be used for the DSS1, SM, and MDM located at Goddard Space Flight Center (GSFC). The prototype could be a training tool for the NGT and NASA Communications (Nascom) Network maintenance personnel.     

Fault dictionary based switched current circuit fault diagnosis using entropy as a preprocessor

A novel method based on a fault dictionary that uses entropy as a preprocessor to diagnose faulty behavior in switched current (SI) circuit is presented in the paper. The proposed method uses a data acquisition board to extract the original signal form the output terminals of the circuit-under-tests. These original data are fed to the preprocessors for feature extraction and finds out the entropies of the signals which are a quantitative measure of the information contained in the signals. The proposed method has the capability to detect and identify faulty transistors in SI circuit by analyzing its output signals with high accuracy. Using entropy of signals to preprocess the circuit response drastically reduces the size of fault dictionary, minimizing fault detect time and simplifying fault dictionary architecture. The result from our examples showed that entropies of the signals fall on different range when the faulty transistors^` Transconductance G_m value varying within their tolerances of 5 or 10%, thus we can identify the faulty transistors correctly when the response do not overlap. The average accuracy of fault recognition achieved is more than 95% although there are some overlapping data when tolerance is considered. The method can classify not only parametric faults but also catastrophic faults. It is applicable to analog circuits as well as SI ones. A low-pass and a band-pass SI filter and a Clock feedthrough cancellation circuit have been used as test beached to verify the effectiveness of the proposed method. A comparison of our work with Yuan et al. (IEEE Trans Instrum Meas 59(3):586–595, 2010), which used entropy and kurtosis as preprocessors, reveals that our method requiring one feature parameter reduces the computation and fault diagnosis time.     

基于多系统数据接口的整合技术研究与实现

针对"一站妥"工作中存在工作周期长、无法提前进行故障定位和分析等问题,东莞供电局设计了一种工作效率高、快速定位故障的城市用户故障排查专家系统。文章提出了一种基于SOA的Web Service技术,该技术实现了多系统数据接口整合,让城市用户故障排查专家系统可以访问外部系统。专家系统的实现,解决了"一站妥"工作中存在的问题,提高工作效率和客户满意度,更节省更环保。     

基于混合推理模式的电路故障诊断系统

针对电路单元的自动测试问题,采用二叉树来表示经验知识中电路测试点的因果关系,并采用人机交互的方式将功能知识和专家经验知识输入到知识库中。提出了一种利用混合推理机模式进行故障诊断的专家系统,采用故障字典与产生式规则相结合的知识库表示方式,解决了专家系统知识库开发与故障诊断速度之间的矛盾。实践表明,该专家系统简便易用、开发速度快,具有较高的使用价值。     

电子电路故障检测技术应用分析

电子电路在电子产品中有着重要作用,但电子电路会受到诸多因素的影响,可能会出现一些故障,文中结合工作中的实际情况探讨了电子电路故障检测技术的应用,以期增强电子产品的稳定性和可靠性。探究结果表明,电子电路在运行过程中可能会出现设计故障、内部故障等,这些故障是由设计不合理、人为操作不当等造成的。因此,应做好故障检测工作,通过观察法、电压测量法、电流测量法等先进的检测技术明确电子电路的故障类型与位置,为故障检修提供支持。     

A Semiautomatic Approach to Deriving Turbine Generator Diagnostic Knowledge

Condition monitoring of turbine generators, housed at British Energy nuclear power stations throughout the U.K., is implemented to diagnose incipient faults at an early stage, so corrective action can be taken to avoid the associated high costs of an unplanned shutdown. A prototype expert system has been developed that provides decision support to condition monitoring experts who monitor British Energy turbine generators. The expert system automatically interprets data from strategically positioned sensors and transducers on the turbine generator by applying expert knowledge in the form of heuristic rules. This paper reviews the application domain and describes the work undertaken in developing the prototype expert system. The paper also outlines a learning module design that uses an approach based on an analytical symbolic machine learning technique, explanation-based generalization, to semiautomatically derive heuristic rules for turbine generator fault diagnosis. The approach adopted by the learning module is explained in detail and a worked example demonstrates how the learning module can derive a fault heuristic from a single training example. The modular approach to capturing the causal fault and behavioral models is described, and the method in which the module will be integrated with the existing expert system has been outlined. A preliminary evaluation of the learning module design is discussed.     

Structural Fault Modeling and Fault Detection Through Neyman–Pearson Decision Criteria for Analog Integrated Circuits

A new approach for analog fault modeling and simulation is presented. The proposed approach utilizes the sensitivity of the circuit’s DC node voltages to the process variations and consequently the current deviance so as to differentiate the faulty behavior. A systematic method is proposed for the fault discrimination to minimize the probability that the circuit is accepted as a fault-free when it is faulty. Tests are generated and evaluated taking into account the potential fault masking effects of process spread on the faulty circuit responses. The introduced fault model is validated on a time-interleaved sample-and-hold circuit. Simulation results demonstrate the effectiveness of the model.     

Transition Path Delay Faults: A New Path Delay Fault Model for Small and Large Delay Defects

We propose a new path delay fault model called the transition path delay fault model. This model addresses the following issue. The path delay fault model captures small extra delays, such that each one by itself will not cause the circuit to fail, but their cumulative effect along a path from inputs to outputs can result in faulty behavior. However, non-robust tests for path delay faults may not detect situations where the cumulative effect of small extra delays is sufficient to cause faulty behavior after any number of extra delays are accumulated along a subpath. Under the new path delay fault model, a path delay fault is detected when all the single transition faults along the path are detected by the same test. This ensures that if the accumulation of small extra delays along a subpath is sufficient to cause faulty behavior, the faulty behavior will be detected due to the detection of a transition fault at the end of the subpath. We discuss the new model and present experimental results to demonstrate its viability as an alternative to the standard path delay fault model. We describe an efficient fault simulation procedure for this model. We also describe test generation procedures. An efficient test generation procedure we discuss combines tests for transition faults along the target paths in order to obtain tests that satisfy the requirements of the new model.     

Distributed diagnosis for homogeneous systems

This article presents a distributed fault-diagnosis algorithm for identifying faulty and fault-free units (processors, PEs, cells) in homogeneous systems. It is based on local comparison among units in a system and dissemination of the test results. Each unit performs comparison with its neighbors by using its own comparator. Unlike other approaches, the algorithm does not assume that diagnostic circuits are fault free. The algorithm is simple enough to be realized with small circuit overhead. The results are especially useful in locating faulty units in processor arrays implemented on a single chip or wafer. Computer simulation has shown that even for low unit yields, extremely high performance (fault coverage) can be obtained by adjusting algorithm parameters.     

Analog circuit diagnosis based on the nullor concept and multiport description of the circuit

The subject of this paper is the fault diagnosis of analog circuits based on the use of nullor concept. The fault location technique presented in the paper can be implemented in the general-purpose analysis program which provides many advantages, of which the most important is the automation of the diagnosis process. A simulation based diagnosis model can be obtained by introducing the norators across the potentially faulty elements and the fixators at the accessible nodes. A practical problem that arises when using this nullor diagnosis model is a lack of an efficient procedure for localization of multiple faults. In the proposed diagnosis technique, the online computational requirements are reduced by introducing a diagnosis model that contains accessible nodes only. The diagnosis model is obtained from the original circuit using relationships among the measured voltages and compensated currents of the faulty elements. The proposed faulty location technique is validated on a benchmark example.     

A new swarm-SVM-based fault diagnosis approach for switched current circuit by using kurtosis and entropy as a preprocessor

This paper presents a new fault diagnosis method for switched current (SI) circuits. The kurtoses and entropies of the signals are calculated by extracting the original signals from the output terminals of the circuit. Support vector machine (SVM) is introduced for fault diagnosis using the entropies and kurtoses as inputs. In this technique, a particle swarm optimization is proposed to optimize the SVM to diagnose switched current circuits. The proposed method can identify faulty components in switched current circuit. A low-pass SI filter circuit has been used as test beached to verify the effectiveness of the proposed method. The accuracy of fault recognition achieved is about 97 % although there are some overlapping data when tolerance is considered. A comparison of our work with Long et al. (Analog Integr Circuit Signal Process 66:93–102, 2011), which only used entropy as a preprocessor, reveals that our method performs well in the part of fault diagnostic accuracy.     

Routability estimation of FPGA-based fault injection

In past years various approaches to hardware-based fault injection using FPGA-based systems have been presented. Owing to the generation of additional faulty functions the mapping and a routable placement of the circuit into the FPGA are difficult to achieve. A technique is presented for estimating the routability, which guarantees the routability of the faulty circuit in the FPGA.     

Behavioral Fault Modeling and Simulation Using VHDL-AMS to Speed-Up Analog Fault Simulation

One of the main requirements for generating test patterns for analog and mixed-signal circuits is fast fault simulation. Analog fault simulation is much slower than the digital equivalent. This is due to the fact that digital circuit simulators use less complex algorithms compared with transistor-level simulators. Two of the techniques to speed up analog fault simulation are: fault dropping/collapsing, in which faults that have similar circuit responses compared with the fault-free circuit response and/or with another faulty circuit response are considered equivalent; and behavioral/macro modeling, whereby parts of the circuit are modeled at a more abstract level, therefore reducing the complexity and the simulation time. This paper discusses behavioral fault modeling to speed-up fault simulation for analog circuits.     

Enhanced FPGA reliability through efficient run-time faultreconfiguration

The expanded use of field programmable gate arrays (FPGA) in remote, long life, and system-critical applications requires the development and implementation of effective, efficient FPGA fault-tolerance techniques. FPGA have inherent redundancy and in-the-field reconfiguration capabilities, thus providing alternatives to standard integrated circuit redundancy-based fault-recovery techniques. Runtime reliability can be enhanced by using such unique features. Recovery from permanent logic and interconnect faults without runtime computer-aided design (CAD) support can be efficiently performed with the use of fine-grained and physical design partitioning. Faults are localized to small partitioned blocks that have fixed interfaces to the surrounding portions of the design, and the affected blocks are reconfigured with previously generated, functionally equivalent block instances that do not use the faulty resources. This technique minimizes the post-fault-detection system downtime, while requiring little area overhead. Only the finely located faulty portions of the FPGA are removed from use. In addition, the end user need not have access to CAD tools, making the algorithm completely transparent to system users. This approach has been efficiently implemented on a diverse set of FPGA architectures. The algorithm's flexibility is also apparent from the variable emphases that can be placed on system reliability, area overhead, timing overhead, design effort, and system memory. Given user-defined emphases, the algorithm can be modified to specific application requirements. Experiments using random s-independent and s-correlated fault models reveal that the approach enhances system reliability, while minimizing area and timing overhead     

Fault isolation for nonisolated blocks

We consider circuits represented as interconnections of logic blocks. In such circuits, the goal of fault isolation is to identify which one of the blocks is faulty based on a faulty output response produced by the circuit. We study this issue and demonstrate that perfect or close-to-perfect fault isolation is possible with tests that propagate fault effects through pairs of blocks. We relate this phenomenon to the numbers of fault effects observed on the circuit outputs for faults in different blocks. For cases where fault isolation is not perfect, we insert observation points to ensure perfect fault isolation. We also study the number of tests required to achieve perfect fault isolation. The study is performed for single stuck-at faults in combinational (or full scan) blocks.     

Fault detection in analog and mixed-signal circuits by using Hilbert–Huang transform and coherence analysis

Using Hilbert–Huang transform (HHT) and coherence analysis, a signature extraction method for testing analog and mixed-signal circuits is proposed in this paper. The instantaneous time–frequency signatures extracted with HHT technique from the measured signal of circuits under test (CUT) are used for faults detection that is implemented through comparing the signatures of faulty circuits with that of the fault-free circuit. The coherence functions of the instantaneous time–frequency signatures and its integral help to test faults in the faulty dictionary according to the minimum distance criterion. The superior capability of HHT-based technique, compared to traditional linear techniques such as the wavelet transform and the fast Fourier transform, is to obtain the subtle time-varying signatures, i.e., the instantaneous time–frequency signatures, and is demonstrated by applying to Leapfrog filter, a benchmark circuit for analog and mixed-signal testing, with 100% of F.D.R (fault detection rate) in the best cases and with the least 24.2% of F.L.R. (fault localization rate) with one signature.     

Fault Diagnosis of Analog Circuits Using Systematic Tests Based on Data Fusion

An analog fault diagnosis approach using a systematic step-by-step test is proposed for fault detection and location in analog circuits with component tolerance and limited accessible nodes. First, by considering soft faults and component tolerance, statistics-based fault detection criteria are established to determine whether a circuit is faulty by measuring accessible node voltages. For a faulty circuit, fuzzy fault verification is performed using the accessible node voltages. Furthermore, using an approximation technique, the most likely faulty elements are identified with a limited number of circuit gain measurements at selected frequencies. Finally, employing the D-S evidence theory, synthetic decision is made to locate faults according to the results of fault verification and estimation. Unlike other methods which use a single diagnosis method or a particular type of measurement information, the proposed approach makes use of the redundancy of different types of measurement information and the combined use of different diagnosis methods so as to improve diagnosis accuracy.     

Fault Diagnosis of Analog Circuits Using Bayesian Neural Networks with Wavelet Transform as Preprocessor

We have developed an analog circuit fault diagnostic system based on Bayesian neural networks using wavelet transform, normalization and principal component analysis as preprocessors. Our proposed system uses these preprocessing techniques to extract optimal features from the output(s) of an analog circuit. These features are then used to train and test a neural network to identify faulty components using Bayesian learning of network weights. For sample circuits simulated using SPICE, our neural network can correctly classify faulty components with 96% accuracy.     

Complex decision diagrams

Complex decision diagrams to represent integer-valued functions in the form of complex Hadamard transforms and spectra are introduced. With the distinctive and unique properties of the transform, the novel complex decision diagrams could be further simplified by reduction rules and a half-spectra theorem that will lead to a more compact representation