Experimental results and modeling techniques for substrate noise inmixed-signal integrated circuits

An experimental technique is described for observing the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate. Various approaches to reducing substrate crosstalk (the use of physical separation of analog and digital circuits, guard rings, and a low-inductance substrate bias) are evaluated experimentally for a CMOS technology with a substrate comprising an epitaxial layer grown on a heavily doped bulk wafer. Observations indicate that reducing the inductance in the substrate bias is the most effective. Device simulations are used to show how crosstalk propagates via the heavily doped bulk and to predict the nature of substrate crosstalk in CMOS technologies integrated in uniform, lightly doped bulk substrates, showing that in such cases the substrate noise is highly dependent on layout geometry. A method of including substrate effects in SPICE simulations for circuits fabricated on epitaxial, heavily doped substrates is developed     

The twin-transistor noise-tolerant dynamic circuit technique

This paper describes a new circuit technique for designing noise-tolerant dynamic logic. It is shown that voltage scaling aggravates the crosstalk noise problem and reduces circuit noise immunity, motivating the need for noise-tolerant circuit design. In a 0.35-μm CMOS technology and at a given supply voltage, the proposed technique provides an improvement in noise immunity of 1.8×(for an AND gate) and 2.5×(for an adder carry chain) over domino at the same speed. A multiply-accumulate circuit has been designed and fabricated using a 0.35-μm process to verify this technique. Experimental results indicate that the proposed technique provides a significant improvement in the noise immunity of dynamic circuits (>2.4x) with only a modest increase in power dissipation (15%) and no loss in throughput     

A 0.65-ns, 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM

An ultrahigh-speed 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM with 0.65-ns address-access time, 0.80-ns write-pulse width, and 30.24-μm ² memory cells has been developed using 0.3-μm BiCMOS technology. Two key techniques for achieving ultrahigh speed are an ECL decoder/driver circuit with a BiCMOS inverter and a write-pulse generator with a replica memory cell. These circuit techniques can reduce access time and write-pulse width of the 72-kb RAM macro to 71% and 58% of those of RAM macros with conventional circuits. In order to reduce crosstalk noise for CMOS memory-cell arrays driven at extremely high speeds, a twisted bit-line structure with a normally on MOS equalizer is proposed. These techniques are especially useful for realizing ultrahigh-speed, high-density SRAM's, which have been used as cache and control storages in mainframe computers     

CMOS gigabit-per-second switching

An analysis and experimental results for a 600-Mb/s 1.2-μm CMOS space switch chip are provided. The high bit rate is achieved with a tree architecture, which is relatively insensitive to on-chip stray capacitance. Computer simulations indicate that bit rates in excess of 1 Gb/s are achievable with 1-μm CMOS and circuit/layout optimization. An obstacle to achieving high bit rate is crosstalk, which is primarily caused by chip packaging and not by the chip itself. Even the best discrete packaging technologies result in excessive crosstalk when 32 outputs switch simultaneously at 600 Mb/s. Tolerable crosstalk was achieved by limiting outputs to two per power supply pin. A major increase in bit rate can be obtained by switching bytes (8 b parallel) of information. This requires on-chip information storage and reclocking to maintain synchronization between the eight parallel bits. Experiments with a second-generation synchronous switch chip have demonstrated switching at 311 MB/s, which corresponds to an STS-48 rate of 2.488 Gb/s     

Low-noise current optoelectronic integrated receiver with internalequalizer for gigabit-per-second long-wavelength optical communications

An equalizer, which is essential in order to improve the sensitivity of receiver optoelectronic integrated circuits (OEICs) at a gigabit-per-second data rate, has been monolithically integrated on an InP substrate with a p-i-n photodiode and a high-impedance high-electron-mobility-transistor (HEMT) amplifier. The receiver operated up to 1.6 Gb/s and showed low noise current characteristics. The minimum noise current is less than 4 pA/√Hz. The sensitivity calculated from the noise current characteristics is -28.4 dBm for 1.6-Gb/s signals. The receiver chip, which was assembled on a ceramic mount, exhibited a sensitivity of -30.4 dBm at 1.2 Gb/s and 1.3-μm wavelength. The performance is as good as those of receiver OEICs with an external equalizer and sufficient for practical use in gigabit-per-second optical communication system     

60-GHz pseudomorphic-MODFET low-noise MMIC amplifiers

The development of V-band low-noise monolithic microwave integrated circuits (MMICs) based on pseudomorphic modulation-doped FETs (P-MODFETs) is presented. These dual-stage MMICs incorporate P-MODFETs, with 0.35-μm×60-μm gates, as the active elements, electron-beam-written tuning elements, and DC-blocking and bias networks. The dual-stage chips exhibited a maximum gain of 10.2 dB at 59.5 GHz and a minimum noise figure of 5.3 dB, with an associated gain of 8.2 dB at 58.2 GHz. A cascaded four-stage amplifier using two MMIC modules exhibited 5.8-dB minimum noise figure with an associated gain of 18.3 dB at 58 GHz and up to 21.1 dB of maximum gain     

A 150-MHz graphics rendering processor with 256-Mb embedded DRAM

A 150-MHz graphics rendering processor with an integrated 256-Mb embedded DRAM, delivering a rendering rate of 75 M polygons/s, is presented, 287.5 M transistors are integrated on a 21.3×21.7 mm ² die in a 0.18-μm embedded DRAM CMOS process with six layers of metal. Design methodologies for hierarchical electrical and physical design of this very large-scale IC, including power distribution, fully hierarchical timing design, and verification utilizing a newly developed nonlinear model, clock design, propagation delay, and crosstalk noise management in multi-millimeter RC transmission lines, are presented     

A 900-MHz dual-conversion low-IF GSM receiver in 0.35-μm CMOS

A low-power fully integrated GSM receiver is developed in 0.35-μm CMOS. This receiver uses dual conversion with a low IF of 140 kHz. This arrangement lessens the impact of the flicker noise. The first IF of 190 MHz best tolerates blocking signals. The receiver includes all of the circuits for analog channel selection, image rejection, and more than 100-dB controllable gain. The receiver alone consumes 22 mA from a 2.5-V supply, to give a noise figure of 5 dB, and input IP3 of -16 dBm. A single frequency synthesizer generates both LO frequencies. The integrated VCO with on-chip resonator and buffers consume another 8 mA, and meets GSM phase-noise specifications     

A 23.8-GHz SOI CMOS tuned amplifier

A 23.8-GHz tuned amplifier is demonstrated in a partially scaled 0.1-μm silicon-on-insulator CMOS technology. The fully integrated three-stage amplifier employs a common-gate, source-follower, and cascode with on-chip spiral inductors and MOS capacitors. The gain is 7.3 dB, while input and output reflection coefficients are -45 and -9.4 dB, respectively. Positive gain is exhibited beyond 26 GHz. The amplifier draws 53 mA from a 1.5-V supply. The measured on-wafer noise figure is 10 dB, while the input-referred third-order intercept point is -7.8 dBm. The results demonstrate that 0.1-μm CMOS technology may be used for 20-GHz RF applications and suggest even higher operating frequencies and better performance for further scaled technologies     

Highly uniform operation of high-performance 1.3-μm AlGaInAs-InPmonolithic laser arrays

We describe the fabrication of monolithically integrated 1×12 arrays of 1.3-μm strain-compensated multiquantum-well AlGaInAs-InP ridge lasers. The laser array shows highly uniform characteristics in threshold current, slope efficiency, and lasing wavelength with a standard deviation of 0.08 and 0.27 mA, 0.012 and 0.007 W/A, and 0.59 and 0.57 nm, respectively, at 20°C and 100°C. Besides, each laser on the array exhibits a low threshold current of 8 mA at 20°C and 21 mA at 100°C, a characteristic temperature of 92 K, and a slope efficiency drop of 0.7 db between 20°C and 80°C. A low thermal crosstalk of less than -4 dB can be obtained from one diode as the injected current of other elements is increased to 70 mA. Also, each laser on the array has a negligible degradation after a 24-hr burn-in test at 80 mA and 100°C. An expected lifetime of more than 20 years is estimated for the lasers when operating at 10 mW and 85°C. The lasers have a small-signal modulation bandwidth of about 9 GHz at 25°C and a low relative intensity noise of -155 dB/Hz without an isolator at 2.5 GHz. It can transmit a 2.5-GHz signal to 50 km through standard single-mode fiber and to 308 m through multimode fiber, with a clear eye opening in OC-48 data-rate tests     

The investigation of key technologies for sub-0.1-μm CMOS devicefabrication

The fabrication of sub-0.1-μm CMOS devices and ring oscillator circuits has been successfully explored. The key technologies include: lateral local super-steep-retrograde (SSR) channel doping with heavy ion implantation, 40-nm ultrashallow source/drain (S/D) extension, 3-nm nitrided gate oxide, dual p⁺/n⁺ poly-Si gate electrode, double sidewall scheme, e-beam lithography and RIE etching for sub-0.1-μm poly-Si gate pattern, thin and low sheet resistance SALICIDE process, etc. By these innovations in the technologies, high-performance sub-0.1-μm CMOS devices with excellent short-channel effects (SCEs) and good driving ability have been fabricated successfully; the shortest channel length is 70 nm. 57 stage unloaded 0.1-μm CMOS ring oscillator circuits exhibiting delay 23.8 ps/stage at 1.5 V, and 17.5 ps/stage and 12.5 ps/stage at 2 V and 3 V, respectively, are achieved     

Advanced thin-film silicon-on-sapphire technology: microwavecircuit applications

This paper reviews the prospects of thin-film silicon-on-sapphire (TFSOS) CMOS technology in microwave applications in the 1-5 GHz regime and beyond and presents the first demonstration of microwave integrated circuits based on this technology, MOSFET's optimized for microwave use, with 0.5-μm optically defined gate lengths and a T-gate structure, have f_t values of 25 GHz (14 GHz) and f_max values of 66 GHz (41 GHz) for n-channel (p-channel) devices and have noise figure values below 1 db at 2 GHz, some of the best reported performance characteristics of any silicon-based MOSFET's to date. On-chip spiral inductors exhibit quality factors above ten. Circuit performance compares favorably with that of other CMOS-based technologies and approach performance levels similar to those obtained by silicon bipolar technologies. The results demonstrate the significant potential of this technology for microwave applications     

On-chip sampling in CMOS integrated circuits

This paper presents a technique for precise crosstalk delay measurement based on on-chip sampling. Results obtained on a test chip fabricated in 0.7-μm CMOS technology exhibit a 100% delay increase in a long coupled line configuration     

Coupling induced soft error mechanisms in nanoscale CMOS technologies

Due to scaling induced effects, CMOS circuits become increasingly more sensitive to transient pulses caused by single event (SE) particles. Researchers mostly considered SE transients as the main cause for combinational logic (CL) related radiation-induced soft errors. However, for high-reliability applications such as avionics, military and medical applications, additional sources such as SE induced soft delays, clock jitters, false clock pulses and crosstalk effects need to be included in soft-error reliability analysis. As technologies advance, coupling effects among interconnects increasingly cause SE transients to contaminate electronically unrelated circuit paths, which can in turn increase the “SE susceptibility” of CMOS circuits. This work focuses on such coupling induced soft error mechanisms in CL, namely the SE crosstalk noise and delay effects. An attempt has been made to compare SE crosstalk noise and SE transient effects, and crosstalk contribution to soft error rate has been examined. In addition, the SE induced coupling delay effect has been studied and compared to radiation induced soft delay effect for various technologies. Results show that, in newer technologies, the SE coupling delay becomes quite comparable to soft delay effect, although caused indirectly by cross-coupling effects. In comparisons, the distributed nature of interconnects has been taken into account and results are demonstrated using HSPICE simulations with interconnect and device parameters derived in 130, 90 and 65 nm technologies.     

Accurate in situ measurement of peak noise and delay change inducedby interconnect coupling

An accurate in situ noise and delay measurement technique that considers interconnect coupling effects is presented. This paper improves upon previous work by proposing (1) a novel accurate peak detector to measure on-chip crosstalk noise, and (2) in situ measurement structure to characterize the dynamic delay effect. A test chip was fabricated using 0.35-μm process and measured results demonstrate the effectiveness of the proposed technique. Noise peak measurements show 40-60 mV (1.8% average) accuracy to simulation results and dynamic delay change curve match well with SPICE. The proposed measurement technique can be used for interconnect model verification and calibration, and has applications to various design automation tools such as noise-aware static timing analysis     

A CMOS readout amplifier for instrumentation applications

An integrated readout amplifier for instrumentation applications in smart sensor systems is presented. A fully integrated CMOS version of such an amplifier has been developed using switched-capacitor techniques. The amplifier system provides differential input capability, programmable amplification, clock generation, and low-pass filtering on the chip. The output signal is continuous in time and the system can be used without any of the special precautions necessary for sampled-data circuits. Emphasis was put on high PSRR (-63 dB at DC), low noise (10-μV_rms input equivalent wideband noise) and offset, low harmonic distortion, and small amplification error (<0.06% at 4 V_pp). To cover a large field of applications, only slightly different realizations can be used for capacitive sensors as well as for resistive sensor bridges     

A 0.5-μm-gate GaAs/AlGaAs inverted HEMT IC-multiplier and D/Aconverter

A gate recess process for a 0.5-μm I-HEMT (inverted high electron mobility transistor) has been developed. A drain conductance for the 0.5-μm I-HEMT as small as 2 mS/mm was achieved, indicating a small short-channel effect. The threshold voltage uniformities were studied in microscopic and macroscopic areas in a 2-in wafer. The uniformities are very high, i.e. the standard deviations of microscopic and macroscopic areas are 10 and 30 mV, respectively, at a threshold voltage of 0.1 V. An 8×4 parallel multiplier was fabricated, and a multiplication time of 1.67 ns was obtained at room temperature. An 8-b digital/analog converter (DAC) was fabricated and operated at a clock rate of 1.2 GHz. The DC linearity of the DAC is better than 0.18 LSB. These results confirm that an I-HEMT is very well suited for high-speed integrated circuits     

Crosstalk characteristics of a 1.3-μm/1.5-μm wavelengthdemultiplexing photodetector using laser-assisted MOMBE growth

This paper demonstrates a monolithic 1.3-μm/1.5-μm wavelength demultiplexing photodetector fabricated using Ar ion laser-assisted metal organic molecular beam epitaxy (MOMBE) growth. Reduction of crosstalk to -24 dB is accomplished in both 1.3-μm and 1.5-μm wavelength regions. The dependence of the crosstalk on the coupling efficiency between the fiber and device and the polarization dependence of the responsivity is also discussed     

A CMOS multichannel IC for pulse timing measurements with 1-mVsensitivity

A multichannel data acquisition circuit that measures the occurrence times of input pulses relative to a 62.5-MHz clock has been integrated in a 1.2-μm CMOS technology. The pulse timing measurement channels are sensitive to input pulses with peak amplitudes as small as 1 mV. Each channel consists of a wideband preamplifier, a tail-cancellation filter, a timing discriminator with time-walk compensation, and a time digitizer. A phase-locked loop (PLL) reference for the time digitizer is included in the circuit. An overall channel timing error of 0.46 ns RMS has been achieved, with negligible channel-to-channel crosstalk, at a power dissipation of 50 mW/channel     

A comprehensive submicrometer MOST delay model and its applicationto CMOS buffers

In this paper, an accurate delay model for MOS transistors in submicrometer CMOS digital circuits is presented. It takes into account a ramp shape input voltage and a feedforward capacitive coupling between gate and drain nodes, along with the main second-order effects present in short-channel MOS transistors. The proposed model shows an average agreement with SPICE simulations of 3% in the calculation of the propagation time, tested on a minimum inverter with a 0.7-μm CMOS reference technology for a wide range of input voltage slopes. An example of application in optimization algorithms regarding CMOS tapered buffers is also reported. A maximum error ranging from 3-6% with respect to SPICE has been found for the optimized circuits