Simulation of interconnect inductive impact in the presence of process variations in 90 nm and beyond

The on-chip inductive impact on signal integrity has been a problem for designs in deep-submicrometer technologies. The inductive impact increases the clock skew, max timing, and noise of bus signals. In this letter, circuit simulations using silicon-validated macromodels show that there is a significant inductive impact on the signal max timing (/spl sim/ 10% pushout versus RC delay) and noise (/spl sim/2/spl times/RC noise). In nanometer technologies, process variations have become a concern. Results show that device and interconnect process variations add /spl sim/ 3% to the RLC max-timing impact. However, their impact on the RLC signal noise is not appreciable. Finally, inductive impact in 65- and 45-nm technologies is investigated, which indicates that the inductance impact will not diminish as technology scales.     

Power-Supply and Substrate-Noise-Induced Timing Jitter in Nonoverlapping Clock Generation Circuits

This paper describes a study of power-supply noise and substrate noise impact on the timing properties of two nonoverlapping clock generation circuits that are typically used in sigma-delta modulators. The constituent logic blocks of the clock generation circuits are also individually characterized where special attention has been put on the inverter whose behavior is fully described in mathematical terms. The analytical model is verified with SPICE using 0.35-mum CMOS process parameters, and a reference simulation in 0.18 mum is also presented showing the trend of technology downscaling. Furthermore, the nonoverlapping clock generation circuits are characterized in the 0.18-mum process and the phenomenon of jitter peaking is described. Finally, all variations of connection configurations in the clock generation circuits are explored to reveal possible optimal configurations.     

一种新的SC—FDE系统粗定时同步算法

定时同步是单载波频域均衡(SC-FDE)系统的一项关键技术,其中的粗定时同步算法决定着同步收敛速度,由Schmidl和Cox提出的传统算法中出现的测度峰值平台影响着粗同步的精度与速度。通过训练符号格式的重新设计,利用其中4个相同部分良好的相关特性,提出了一种基于特殊训练符号的粗同步算法。仿真结果表明,在高斯白噪声信道和多径衰落信道条件下,新算法定时偏差估计的方差和均值接近于理论值,粗定时同步能够精确地完成,较好解决了测度峰值平台问题。     

An efficient merging scheme for prescribed skew clock routing

In ultra-deep submicron very large-scale integration (VLSI) designs, clock network layout plays an increasingly important role on determining circuit quality indicated by timing, power consumption, cost, power-supply noise, and tolerance to process variations. In this brief, a new merging scheme is proposed for prescribed nonzero skew routings which are useful in reducing clock cycle time, suppressing power-supply noise, and improving tolerance to process variations. This technique is simple and easy to implement for practical applications. Experimental results on benchmark circuits with both buffered and unbuffered routings exhibit large improvement on wirelength and buffer cost compared with other existing works.     

Modeling and Technique to Improve PSRR and PS-IMD in Analog PWM Class-D Amplifiers

Although power-supply noise, qualified by power- supply rejection ratio (PSRR), has been recognized as a potential drawback of Class-D amplifiers (CDAs) compared to linear amplifiers, the mechanisms of PSRR for CDAs are not well established. It is also not well recognized that the power-supply noise can intermodulate with the input signal, manifesting into power-supply induced intermodulation distortion (PS-IMD), and that the PS-IMD can be significantly larger than the output distortion component at supply noise frequency. Furthermore, techniques to improve PSRR and PS-IMD are largely unreported in literature. In this brief, by means of a linear model, the PSRR and PS-IMD of single-feedback and double-feedback CDAs are analyzed and analytical expressions derived. A simple method is proposed to improve PSRR and PS-IMD with very low hardware overheads, and the improvement is ~ 26 dB. Analytical expressions for PSRR and PS-IMD of the improved design are derived and the pertinent parameters thereof are investigated. The model and analyses provide practical insight to the mechanisms of PSRR and PS-IMD, and how various parameters may be varied to meet a given specification.     

Supply-voltage optimization for below-70-nm technology-node MOSFETs

A tradeoff between the performance and power consumption is discussed for below-70-nm technology-node MOSFETs, as a function of power-supply voltage. In order to optimize the supply voltage, gate-delay (CV/I) and energy-delay product (C²V³/I) trends are evaluated using the characteristics of down to 24-nm physical-gate-length nMOSFETs. The gate-delay dependence on the supply voltage down to 0.9 V is almost constant at the same OFF current of 100 nA/μm. On the other hand, an optimum supply voltage for the energy-delay product significantly depends, on the short-channel characteristics, and is interpreted with analytic expressions. Therefore, for the below-70-nm technology node at sub-1.0 V, it is important to design the power-supply voltage taking into consideration of a short-channel effect (SCE)     

Spatial characterization of process variations via MOS transistortime constants in VLSI and WSI

This paper is the first large-scale experimental characterization of spatial process variations for a parameter that is directly involved in timing issues: the MOS transistor time constant. This is achieved by measuring the oscillation period of highspeed (500 MHz) CMOS ring oscillators that are implemented at different locations on individual dies and over wafers. Novel phenomena are observed, improving our understanding of how process variations affect the performance of synchronous systems, particularly in clock distribution networks. We observed four components contributing to period variations: an environment-dependent component, a process-dependent component of lower spatial frequency, a random component analogous to white noise, and a component depending on the geometry of the power-supply distribution network     

锁相环电源噪声激起的抖动灵敏度研究

锁相环作为噪声敏感器件,最大干扰源来自电源噪声。为实现系统的高性能,盲目降噪是很多工程师唯一手段。文中指出,不同频点电源噪声对PLL造成的抖动不同,而单纯降噪可能导致过度设计且不能达到目的。文中通过搭建锁相环Spice模型,开发的一款软件作为论证工具来阐述抖动灵敏度概念。     

A variable-frequency parallel I/O interface with adaptivepower-supply regulation

This paper presents a low-power high-speed CMOS signaling interface that operates off of an adaptively regulated supply. A feedback loop adjusts the supply voltage on a chain of inverters until the delay through the chain is equal to half of the input period. This voltage is then distributed to the I/O subsystem through an efficient switching power-supply regulator. Dynamically scaling the supply with respect to frequency leads to a simple and robust design consisting mostly of digital CMOS gates, while enabling maximum energy efficiency. The interface utilizes high-impedance drivers for operation across a wide range of voltages and frequencies, a dual-loop delay-locked loop for accurate timing recovery, and an input receiver whose bandwidth tracks with the I/O frequency to filter out high-frequency noise. Test chips fabricated in a 0.35-μm CMOS technology achieve transfer rates of 0.2-1.0 Gb/s/pin with a regulated supply ranging from 1.3-3.2 V     

Impact of die-to-die and within-die parameter fluctuations on themaximum clock frequency distribution for gigascale integration

A model describing the maximum clock frequency (FMAX) distribution of a microprocessor is derived and compared with wafer sort data for a recent 0.25-μm microprocessor. The model agrees closely with measured data in mean, variance, and shape. Results demonstrate that within-die fluctuations primarily impact the FMAX mean and die-to-die fluctuations determine the majority of the FMAX variance. Employing rigorously derived device and circuit models, the impact of die-to-die and within-die parameter fluctuations on future FMAX distributions is forecast for the 180, 130, 100, 70, and 50-nm technology generations. Model predictions reveal that systematic within-die fluctuations impose the largest performance degradation resulting from parameter fluctuations. Assuming a 3σ channel length deviation of 20%, projections for the 50-nm technology generation indicate that essentially a generation of performance gain can be lost due to systematic within-die fluctuations. Key insights from this work elucidate the recommendations that manufacturing process controls be targeted specifically toward sources of systematic within-die fluctuations, and the development of new circuit design methodologies be aimed at suppressing the effect of within-die parameter fluctuations     

Theoretical analysis of timing jitter in monolithic multisectionmode-locked DBR laser diodes

We present a theoretical analysis of the timing jitter in monolithic multisection mode-locked DBR lasers which is shown to agree well with experimental measurements. The analysis uses a traveling-wave equation model with Langevin spontaneous emission noise and includes the important physical effects of gain nonlinearities, self-phase modulation, and the presence of DBR filtering. It is found that spontaneous noise limits low-jitter operation. The impact of frequency detuning on the timing jitter is studied and the effects of laser parameters, such as linewidth enhancement factor and gain section length, are discussed for achieving low-jitter pulses     

A sub-130-nm conditional keeper technique

Increasing leakage currents combined with reduced noise margins significantly degrade the robustness of wide dynamic circuits. In this paper, we describe two conditional keeper topologies for improving the robustness of sub-130-nm wide dynamic circuits. They are applicable in normal mode of operation as well as during burn-in test. A large fraction of the keepers is activated conditionally, allowing the use of strong keepers with leaky precharged circuits without significant impact on performance of the circuits. Compared to conventional techniques, up to 28% higher performance has been observed for wide dynamic gates in a 130-nm technology. In addition, the proposed burn-in keeper results in 64% active area reduction     

A New Lossy Substrate Model for Accurate RF CMOS Noise Extraction and Simulation With Frequency and Bias Dependence

A lossy substrate model is developed to accurately simulate the measured RF noise of 80-nm super-100-GHz f_T n-MOSFETs. A substrate RLC network built in the model plays a key role responsible for the nonlinear frequency response of noise in 1-18-GHz regime, which did not follow the typical thermal noise theory. Good match with the measured S-parameters, Y-parameters, and noise parameters before deembedding proves the lossy substrate model. The intrinsic RF noise can be extracted easily and precisely by the lossy substrate deembedding using circuit simulation. The accuracy has been justified by good agreement in terms of I_d,g_m, Y-parameters, and f _T under a wide range of bias conditions and operating frequencies. Both channel thermal noise and resistance induced excess noises have been implemented in simulation. A white noise gamma factor extracted to be higher than 2/3 accounts for the velocity saturation and channel length modulation effects. The extracted intrinsic NF_min as low as 0.6-0.7 dB at 10 GHz indicates the advantages of super-100 GHz f_T offered by the sub-100-nm multifinger n-MOSFETs. The frequency dependence of noise resistance R_n suggests the bulk RC coupling induced excess channel thermal noise apparent in 1-10-GHz regime. The study provides useful guideline for low noise and low power design by using sub-100-nm RF CMOS technology     

Sleep Transistor Sizing and Adaptive Control for Supply Noise Minimization Considering Resonance

The conventional sleep transistor sizing schemes do not consider the resonant supply noise which represents the worst-case supply disturbance. This paper investigates the impact of sleep transistor sizing on different on-chip noise components and shows that, contrary to the conventional wisdom, a larger sleep transistor is not always favored in term of performance when the resonant supply noise is taken into account. To minimize the worst-case supply noise, an optimal sizing scheme using an explicit noise and impedance model is developed and verified by benchmark circuits. Employing the proposed technique results in a reduction of the worst-case noise by 19%, as well as a saving of standby leakage and area overhead by 60% in comparison with conventional sizing scheme. In order to deal with the sporadic nature of the resonant, we propose an adaptive sleep transistor circuit which adjusts the size of sleep transistor on the fly to remove the DC noise penalty of the fixed sizing scheme. Simulation results on 32-nm CMOS technology are used to demonstrate the functionality and effectiveness of the proposed adaptive sizing circuits.      

一种高电源抑制能力低噪声的低压差调节器电路

提出了一种高电源抑制能力(PSR)、低噪声的低压差调节器结构。利用电流镜和压控电流源技术,消除一个低频极点,提高LDO系统稳定性。1 kHz时PSR可达到100 dB以上,1 MHz时PSR高于40 dB,最大电流输出能力为150 mA。另外,电路中具有启动电路和限流电路,可以有效地保证电路正常工作。基于TSMC 130 nm低功耗工艺流片,流片结果表明,芯片噪声特性良好。稳定性较高,并具有很高的电源抑制能力,有效地保证了系统指标。     

An autonomous SRAM with on-chip sensors in an 80-nm double stacked cell technology

An active solution is proposed to overcome the uncertainty and fluctuation of the device parameters in nanotechnology SRAM. The proposed scheme is composed of sensing blocks, analysis blocks and control blocks. An on-chip timer, temperature sensor, substrate noise detector, and leakage current monitor are used to monitor internal status of chip during operation. From the sensed data, internal supply voltage, internal timing margin from decoding to sensing time, substrate noise from digital area, and low voltage level of wordline are controlled. A 512-kb test SRAM chip, fabricated with an 80-nm double stacked cell technology, shows that average power consumption is reduced by 9% and the standard deviation decreases by 58%.     

Temperature-adaptive voltage tuning for enhanced energy efficiency in ultra-low-voltage circuits

Circuits optimized for minimum energy consumption operate typically in the subthreshold regime with ultra-low power-supply voltages. Speed of a subthreshold logic circuit is enhanced with an increase in the die temperature. The excessive timing slack observed in the clock period of subthreshold logic circuits at elevated temperatures provides opportunities to lower the active-mode energy consumption. A temperature-adaptive dynamic-supply voltage-tuning technique is proposed in this paper to reduce the high-temperature energy consumption without degrading the clock frequency in ultra-low-voltage subthreshold logic circuits. Results indicate that the energy consumption can be lowered by up to 40% by dynamically scaling the supply voltage at elevated temperatures. An alternative technique based on temperature-adaptive reverse body bias to exponentially reduce the subthreshold leakage currents at elevated temperatures is also investigated. The active-mode energy consumption with two temperature-adaptive voltage-tuning techniques is compared. The impact of the process parameter and supply voltage variations on the proposed temperature-adaptive voltage scaling techniques is evaluated.     

Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design

On-chip global interconnect exhibits clear frequency dependence in both resistance (R) and inductance ( L). In this paper, its impact on modern digital and radio frequency (RF) circuit design is examined. First, a physical and compact ladder circuit model is developed to capture this behavior, which only employs frequency independent R and L elements, and thus, supports transient analysis. Using this new model we demonstrate that the use of dc values for R and L is sufficient for timing analysis (i.e., 50% delay and slew rate) in digital designs. However, RL frequency dependence is critical for the analysis of signal integrity, shield line insertion, power supply stability, and RF inductor performance.     

An 8-GHz to 10-GHz Distributed DLL for Multiphase Clock Generation

A distributed DLL (DDLL) with low jitter and high phase accuracy is proposed for the multiphase clock generator. The high-speed multiphase clock generator produces a five-phase clock at a frequency range of 8 to 10 GHz. Additionally, the discrete-time model for the distributed DLL and the analysis about stability and noise are proposed in this work. The measured rms jitter is 293.3 fs and the maximum phase mismatch is 1.4 ps. The proposed architecture can suppress the jitter by 58%. The distributed DLL occupies 0.03 ${hbox{mm}}^{2}$ active area in a 90-nm CMOS technology and consumes 15 mA from a 1.0-V supply.      

Nanometer Device Scaling in Subthreshold Logic and SRAM

Subthreshold circuit design is promising for future ultralow-energy sensor applications as well as highly parallel high-performance processing. Device scaling has the potential to increase speed in addition to decreasing both energy and cost in subthreshold circuits. However, no study has yet considered whether device scaling to 45 nm and beyond will be beneficial for subthreshold logic. We investigate the implications of device scaling on subthreshold logic and SRAM and And that the slow scaling of gate-oxide thickness leads to a 60% reduction in I_on/I_off between the 90- and 32-nm device generations. We highlight the effects of this device degradation on noise margins, delay, and energy. We subsequently propose an alternative scaling strategy and demonstrate significant improvements in noise margins, delay, and energy in sub-V_th circuits. Using both optimized and unoptimized subthreshold device models, we explore the robustness of scaled subthreshold SRAM. We use a simple variability model and find that even small memories become unstable at advanced technology nodes. However, the simple device optimizations suggested in this paper can be used to improve nominal read noise margins by 64% at the 32-nm node.