The dependence of stress induced voiding on line width studied by conventional and high resolution resistance measurements

The degradation due to stress induced voiding of nitride passivated Al-1 wt.% Si and Ti/TN/ Al-1wt.% Si-0.5 wt. % Cu/Ti/TN interconnects with widths ranging between 0.4 and 1.2 μm was studied by in-situ conventional high resolution resistance measurements (HRRM) during storage at temperatures between 168 and 240°C. The conventional measurements on Al-Si lines, which lasted more than one year, clearly showed that the interconnect lifetime decreases with decreasing line width. With HRRM the degradation due to stress induced voiding can be detected much sooner and with much more detail. From the HRRM it is clear that the resistance changes during storage often happen in jumps and that the degradation has a rather complex alloy, line width and temperature dependence. Both for 0.4 and 0.6 μm wide Al---Si lines more degradation occurred for storage at 175 °C compared to storage at 200 °C. For the Al---Si---Cu stacks the degradation of 0.4 μm wide lines was worse for storage at 240°C compared to storage at 200 °C, but the opposite was true for the 0.6 μm wide lines.     

Drawbacks to using NIST electromigration test-structures to testbamboo metal lines

In this work the applicability of NIST electromigration test patterns when used to test “bamboo” metal lines is discussed. Wafer level tests on passivated and nonpassivated samples employing the Al-1%Si/TiN/Ti metallization scheme were performed. Straight metal lines 1000 μm long and 0.9 μm or 1.4 μm wide were tested at two different current densities, j=3 MA/cm² and J=4.5 MA/cm², keeping the stress temperature at T=230°C. The failures occurred mainly in the end segment areas and hindered the evaluation of the electromigration resistance of the test lines. In order to avoid this problem, completely different test patterns containing a number of geometrical variations should be defined     

A study of the thermal behavior of different test patterns used in differential high resolution electromigration measurements

The differential high-resolution electromigration (EM) measurement technique requires special test patterns since for the implementation of this technique the presence of two metal lines is necessary, one metal line to be stressed with a high current density (‘test’ or ‘stressed’ resistor) and a second line (‘monitor’ or ‘reference’ resistor) to compensate for the thermal instabilities of the stressed one. It is accepted that due to Joule heating the stressed line always acquires higher temperature than the reference line and, therefore, additional resistance changes due to thermally induced phenomena, like precipitation of additional elements, will affect the measurement. In order to minimize these unwanted effects, an optimal high-resolution EM test structure should show a minimum temperature difference between the stressed and the reference lines. Based on this requirement, in this work we simulated three different test structures being used by various research groups for high-resolution measurements and subsequently compared these test structures on account of their thermal behavior. Each test structure was examined for the case of two different widths of metal lines, 4 and 0.5 μm. The results obtained from the simulation of these test patterns demonstrated that the test pattern comprised of two parallel stress and reference lines shows better thermal behavior than the ‘lined-up’ (continuous) metal lines where the stress and reference lines are actually part of the same line. In particular, the test pattern comprised of two parallel straight lines has slightly better behavior than the one with meandered lines in terms of minimization of the temperature difference between the stressed and the reference resistors. The difference between the thermal behavior of the two structures though is very small. For that reason, the parallel lines should be preferred from the meandered ones only if layout restrictions do not require the choice of a more compact (i.e., meandered) solution. Both test structures have shown a better thermal behavior than the ‘lined-up’ metal lines.     

高跨导AlGaN/GaN HFET器件研究

报道了蓝宝石衬底上AlGaN/GaNHFET的制备以及室温下器件的性能。器件栅长为0.8μm,源漏间距为3μm,得到器件的最大漏电流密度为0.7A/mm,最大跨导为242.4mS/mm,截止频率(fT)和最高振荡频率(fmax)分别为45GHz和100GHz。同时器件的脉冲测试结果显示,SiN钝化对大栅宽器件的电流崩塌效应不能彻底消除。     

Design of a new test structure for the study of electromigration with early resistance change measurements

A new test structure has been designed in order to perform accurate early resistance change measurements in metal lines submitted to high current stress. This test structure integrates both advantages of the so-called “absolute” and “bridge” techniques, resulting in accurate resistance measurements with a high resolution for both the current-stressed and reference strip. Due to the improved measurement configuration, the aging kinetics of a metal line under current stress can be studied in more detail.     

Residual stress estimation in damascene copper interconnects using embedded sensors

Mechanical stress in damascene copper/low-k interconnects has been studied by means of micro-rotating sensors embedded in chips and directly integrated in CMOS process flow. A new hinge sensor design has been elaborated and a new analytical model of the mechanical equilibrium of sensors is validated. These sensors allow the study of the average residual stress as a function of the line width in a range from few hundred nanometers to several microns. It was found that the residual stress increases from 290 to 850 MPa in, respectively, 2 and 0.25 μm wide lines. This trend shows a yield stress increase with the line width reduction. Copper grains microstructure change between large and narrow lines is probably one of the reasons for yield stress and so residual stress increase. This microstructure change has been observed by means of Transmission Electron Microscopy (TEM) observations.     

Texture and strain in narrow copper damascene interconnect lines: An X-ray diffraction analysis

The behaviour of submicron damascene copper lines raises a number of fundamental issues such as grain growth in narrow trenches, thermomechanical properties of copper in these confined geometries, etc. This experimental study is aimed at evaluating the influence of annealing, polishing and line width on the room temperature strain and texture of narrow copper damascene lines. X-ray diffraction has been performed on arrays of lines with widths ranging between 3 μm and 0.09 μm. Two annealing conditions (150 °C and 400 °C) have been used either prior or after Chemical Mechanical Polishing (CMP). A clear influence of the Cu overburden on the in-line microstructure is evidenced. X-ray diffraction analysis shows that strains in line longitudinal direction are higher in those annealed at 400 °C and decrease with the width of the lines.Effect of CMP on structure and relationship between both texture and strain and temperature of thermal treatments is discussed in light of these observations.     

Texture investigation of copper interconnects with a different line width

To understand the effect of line width on textural and microstructural evolution of Cu damascene interconnect, three Cu interconnects samples with different line widths are investigated. According to x-ray diffraction (XRD) results, the (111) texture is developed in all investigated lines. Scattered {111}〈112〉 and {111}〈110〉 texture components are present in 0.18-μm-width interconnect lines, and the {111}〈110〉 texture was developed in 2-μm-width interconnect lines. The directional changes of the (111) plane orientation with increased line width were investigated by XRD. In addition, microstructure and grain-boundary character distribution (GBCD) of Cu interconnect were measured using electron backscattered diffraction (EBSD) techniques. This measurement demonstrated that a bamboo-like microstructure is developed in the narrow line, and a polygranular structure is developed in the wider line. The fraction of ∑3 boundaries is increased as the line width increases but is decreased in the blanket film. A new interpretation of textural evolution in damascene interconnect lines after annealing is suggested, based on the state of stress and growth mechanisms of Cu deposits.     

Electromigration and integration aspects for the copper-SiLK system

In this study, the thermal characteristics and electromigration (EM) resistance of two dielectrics, SiLK™ and SiO₂, are investigated to evaluate the feasibility of low dielectric-constant SiLK for intermetal dielectric applications. Liftoff patterning was employed to fabricate the Cu interconnect for the EM test, and the Taguchi method was used in the experimental design to identify the key parameters for a successful liftoff. It was shown that the thermal impedance of the metal lines passivated with SiLK is 14% higher than that of metal lines passivated with SiO₂. On the basis of the thermal impedance and temperature rise of the interconnect, it was concluded that the major heat transfer path is via the underlayer dielectric to the Si substrate. The activation energy of EM for Cu passivated with SiLK is smaller, and the EM lifetime is shorter than that of Cu passivated with SiO₂. Possible mechanisms are discussed.     

The evolution of the resistance of aluminum interconnects during electromigration

Resistance monitoring is a traditional method to investigate electromigration failure. It is important to understand how much information can be extracted from the data generated by these experiments. To this end, precision resistance measurements were included as part of accelerated electromigration tests performed inside of a high voltage scanning electron microscope (HVSEM). Twenty-two passivated Al interconnects were tested at 30 mA/μm² and at two temperatures, half at 212°C and half at 269°C. During every test, our automated apparatus stored images of each 300 μm long structure several times per hour. The resistance of each line was also precisely measured and recorded. Changing the temperature affected only the time scale of the resistance evolution. There were resistance changes before voids formed that were neither due to temperature fluctuations nor solute effects. In most cases, the nucleation of the first void to form in a line was signaled by an increase in the time derivative of the resistance. Due to the strong effect of void shape, the void volume could not be determined by the magnitude of the resistance change. The width of a void (transverse to the line) rather than the volume largely determined the resistance change.     

RF measurements to pinpoint defects in inkjet-printed,thermally and mechanically stressed coplanar waveguides

In this work 10-GHz-band RF measurement and microscopy characterizations were performed on thermally and mechanically long-term-stressed coplanar waveguides (CPW) to observe electrical and mechanical degradation in 1-mm-thick PPO/PPE polymer substrates with inkjet-printed Ag conductors. The structure contained two different CPW geometries in a total of 18 samples with 250/270 μm line widths/gaps and 670/180 μm line widths/gaps. A reliability test was carried out with three sets. In set #1 three 250 μm and three 670 μm lines were stored in room temperature conditions and used as a reference. In set #2 six samples were thermally cycled (TC) for 10,000 cycles, and in set #3 six samples were thermally cycled and bent with 6 mm and 8 mm bending diameters.Thermal stressing was done by cycling the samples in a thermal cycling test chamber operating at 0/100 °C with 15-minutes rise, fall, and dwell times, resulting in a one-hour cycle. The samples were analyzed during cycling breaks using a vector network analyzer (VNA). In addition to optical microscopy, field emission scanning electron microscopy (FESEM) and atomic force microscopy (AFM) imaging were used to mechanically characterize the structures.The results showed that the line width of 670 μm had better signal performance and better long-term reliability than the line width of 250 μm. In this study, the average limit for proper RF operation was 2500 thermal cycles with both line geometries. The wide CPW lines provided more stable characteristics than the narrow CPW lines for the whole 10,000-cycle duration of the test, combined with repeated bending with a maximum bending radius of 6 mm. A phenomenon of nanoparticle silver protruding from cracks in the print of the bent samples was observed, as well as fracturing of the silver print in the CPW lines.     

Tunable dual-wavelength fiber laser

A narrow-linewidth, tunable, dual-wavelength fiber laser operating at room temperature with each lasing wavelength in single-longitudinal-mode operation is demonstrated. A commercially available tunable fiber Bragg grating was used to tune one of the lasing lines. An unpumped elliptical-core erbium-doped fiber was used as a saturable absorber to suppress mode hopping. Wavelength switching was achieved using a polarization controller. The linewidth (FWHM, full width at half maximum) of the laser line was 6.7 MHz and the OSNR (optical signal to noise ratio) was more than 40 dB.     

Effect of DC Current on the Creep Deformation of Tin

Impression creep testing of tin was performed in the temperature range of 343 K to 398 K and under a punching stress of 12 MPa to 55 MPa. During the impression test at constant load, a direct electric current in the range of 0 A to 6 A flowed through the punch into the sample, introducing an electromechanical interaction. Steady-state creep was observed under the simultaneous action of the electric current and mechanical stress. The steady-state impression velocity increased with increasing temperature, punching stress, and electric current. A hyperbolic sine relation was used to describe the stress dependence of the steady-state impression velocity for impression creep of tin. The apparent activation energy decreased with increasing electric current.     

Interconnect reliability - A study of the effect of dimensional and porosity scaling

A number of challenges linked to the reliability characterization of downscaled back-end-of-line copper/low-k interconnects are covered. Concerning copper reliability, it is shown using early data on 30 nm ½pitch that advanced barrier/seed/plating options can counteract models that predict decreased electromigration performance in smaller dimensions. Regarding stress-induced voiding, it is discussed that porosity scaling negatively influences metal degradation due to increased stress gradients. Also, since copper degradation during high temperature storage tests is driven by different failure mechanisms, it is argued that tests at a wide range of temperatures are needed to characterize stress-induced voiding in copper/low-k systems at normal operating conditions. In addition, it is suggested that the current knowledge on the dependence of interconnect pitches and dielectric porosity on stress in copper lines needs to be taken into account when building finite element models of copper/low-k stacks. This is motivated by highlighting results of our recent study where the copper strain is varied for different copper dimensions and pattern densities. Finally, because the reliability margin of time dependent dielectric breakdown of scaled intermetal dielectrics becomes smaller, it is put forward that understanding the low voltage behaviour of time dependent dielectric breakdown becomes indispensable. A case study using fully passivated MOS capacitors without metallic barrier between the copper and the dielectric is detailed out and differences in current versus time behaviour and distributional shapes between low and high fields are highlighted.     

Influence of water absorption by silicate glass on the strains in passivated Al conductor lines

X-ray diffraction strain measurements and elastic recoil detection analysis of aluminum conductor lines, passivated with silicon oxide, showed that the absorption of water molecules in the passivation layer directly influences the strain state in the lines. Volume changes of the passivation due to water absorption lead to unusual strain states, where the line is strained in compression in the width direction and in tension in the height and length direction, with the largest component in the height direction. The process of water absorption, as well as the rearrangement of the strain components in the lines, was found to be reversible.     

用于干涉测量的光栅外腔半导体激光器

研制了用于光干涉测量的单稳频、窄线宽光栅外腔半导体激光器(LD)。它由出光面镀有增透膜的单管半导体激光器、光束校正准直系统、闪耀光栅、注入电流驱动系统及温度控制系统组成。闪耀光栅作为外腔光反馈元件对单管半导体激光器输出的纵模进行选择，使之工作在单纵模状态。外腔的引入还使输出光的谱线宽度得以大大压窄。注入电流驱动系统为半导体激光器提供工作电流。温度控制系统由双层温控组成。第一层用于控制单管半导体激光器管芯温度；另一层用于及时带走第一层温控产生的热量，并消除环境温度影响，使外腔温度稳定。该温控系统可使所构成激光器的温度稳定在1‰℃量级。对研制的外腔半导体激光器的特性进行测试，其输出功率恒定、模式单一稳定、谱线宽度优于1．4MHz。     

Electromigration behavior of dual-damascene Cu interconnects––Structure, width, and length dependences

Experiments were performed to study the effect of line width and length, and the results revealed interesting differences in electromigration behavior of via-fed upper and lower layer dual-damascene test structures. The observed location of electromigration induced void in upper and lower layer test structures cannot be completely explained by the theory of current gradient induced vacancy diffusion. The electromigration median time to failure (MTF) were found to be dependent upon the line width for the lower layer test structures while it remained unaffected in the case of upper layer test structure. Cu/dielectric cap interface acting as the dominant electromigration path and the current crowding location being near the Cu/dielectric cap interface for lower layer structures due to structural differences, explain this behavior. Similarly, short length upper and lower layer test structures exhibited completely different characteristics. The back stress effect on short lines was evident on both upper and lower layer structures, however, only the upper layer showed two distinct via and line failure mechanisms. These observed effects are specific to Cu dual-damascene structures and can have major technological implications for electromigration reliability assessment.     

Localized monitoring of electromigration with early resistance change measurements

A new approach is presented in order to study the local effects of electromigration in metallisations. So-called localized electrical resistance measurements allow us to detect and localize the formation of individual voids and hillocks in metallisation lines submitted to current and temperature stress. Localized electrical resistance measurements are performed by adding a number of voltage terminals at equal distances on the test structure and by measuring the resistance drift of each line segment. Through the use of such a multi-voltage probe (MVP) test structure, the sensitivity of the electrical resistance to the presence of defects is strongly increased. By comparing the observed electrical resistance drift results with the corresponding SEM micrographs, important conclusions can be drawn concerning the nature of the resistance changes. With finite element calculations a quantitative interpretation is obtained of the observed local resistance changes. An additional feature of localized electrical resistance measurements is the possibility to determine the actual temperature profile present in a test strip at the beginning of a current stress experiment, i.e. prior to failure formation.     

Study of reverse dark current in 4H-SiC avalanche photodiodes

Temperature-dependent current-voltage (I-V) measurements have been used to determine the reverse dark current mechanisms in 4H-SiC avalanche photodiodes (APDs). A pn junction vertical mesa structure, passivated with SiO/sub 2/ grown by plasma enhanced chemical vapor deposition, exhibits predominate leakage current along the mesa sidewall. Similar APDs, passivated by thermal oxide, exhibit lower dark current before breakdown; however, when the temperature is higher than 146/spl deg/C, an anomalous dark current, which increases rapidly with temperature, is observed. This current component appears to be eliminated by the removal of the thermal oxide. Near breakdown, tunneling is the dominant dark current mechanism for these pn devices. APDs fabricated from a pp/sup -/n structure show reduced tunneling current. At room temperature, the dark current at 95% of breakdown voltage is 140 fA (1.8 nA/cm/sup 2/) for a 100-/spl mu/m diameter APD. At a gain of 1000, the dark current is 35 pA (0.44 /spl mu/A/cm/sup 2/).     

Optimization of large-area OLED current distribution grids with self-aligned passivation

The luminance homogeneity of large-area organic light emitting diodes (OLEDs) is limited by the sheet resistance of the transparent electrode. A large lateral voltage drop inside the electrode and thus brightness inhomogeneity result from the high sheet resistance of transparent conductors. To improve sheet resistance, a low-resistance metal grid is often included. To prevent shorting, the grid needs to be passivated. However, since passivation further decreases the device active area, accurate alignment of the passivation layer is crucial. We report simulations of a Joule-heating-based self-alignment method for the passivation layer. The Joule heating model was divided into two sub-models: a current model to study current distribution on grid scale during Joule heating, and thermoelectric model to study heat transfer in the system. Grid design rules – minimum line pitch and the geometry of the grid – necessary for a successful Joule heating process were studied. The line group design was found to be the best option for a current distribution grid. The minimum line pitch limited by heat transfer was 0.8 mm on an indium tin oxide (ITO) coated polyethylene terephthalate (PET) substrate. With the line group design, maximum luminance output was achieved with a pitch of 4 mm, when the sheet resistance of the metal lines was 0.01 Ω/□$\mathrm{\Omega }/\square$. This fulfils the demands placed by the Joule heating process.