Characterization of hafnium oxide grown on silicon by atomic layer deposition: Interface structure

Ultra-thin films of hafnium oxide deposited on Si(1 0 0) substrates by means of atomic layer deposition using tetrakis(diethylamino)hafnium as the hafnium precursor are characterized. These films and interface structures are probed using Fourier transform infrared spectroscopy along with Z-contrast imaging and electron energy loss spectroscopy (EELS) of a scanning transmission electron microscope. The interface structure of HfO₂/Si(1 0 0) is further investigated using angle resolved X-ray photoelectron spectroscopy to probe the core level orbitals (Hf 4f, Si 2p, O 1s) at high resolution. The interfacial differences are also examined by probing the Hf 4f bonding with normal incidence XPS in thin and thick films. The XPS studies show that the binding energies remain unchanged with film depth and that there is no apparent signature of silicate structure in the as-deposited films. EELS spectra taken at the interface and XPS measurements suggest the interface is mainly silicon oxide. Two different cleaning methods used show difference only in the thickness of the silicon oxide interlayer.     

Structural characterization of ultra-thin (0 0 1) silicon films bonded onto (0 0 1) silicon wafers:: a transmission electron microscopy study

Ultra-thin (0 0 1) silicon films (thickness less than 25 nm) directly bonded onto (0 0 1) silicon wafers have been investigated by transmission electron microscopy. Twist interfacial dislocations accommodate the twist between the two crystals, whereas tilt interfacial dislocations accommodate the tilt resulting from the residual vicinality of the initial surfaces. In low-twist angle grain boundaries, twist interfacial dislocations are dissociated and no precipitates are detected. In high-twist angle grain boundaries, there is no dissociation and a high density of silicon oxide precipitates is observed at the interface. Tilt interfacial dislocations are pinned by these precipitates, they are more mobile than precipitates. Without precipitates, their lines are straighter than those with precipitates, and this is especially when the bonded wafers are annealed at a high temperature. When no precipitates are present, tilt interfacial dislocations are associated by pairs, and we demonstrate that each tilt interfacial dislocations introduce a diatomic interfacial step at the interface.     

The origination and optimization of Si/SiO/sub 2/ interface roughness and its effect on CMOS performance

As CMOS device dimensions scale down to 100 nm and beyond, the interface roughness between Si and SiO/sub 2/ has become critical to device performance and reliability. Si/SiO/sub 2/ interface roughness degrades channel mobility decreasing drive currents. The authors have used atomic force microscopy to study surface roughness in the processing of 0.16 /spl mu/m CMOS integrated circuits. All of the process steps that could potentially affect the interface roughness have been studied. The results show that oxidation is the major contributor to the interface roughness. The rms roughness is found to be linearly dependent on oxide thickness. Transistors with Si/SiO/sub 2/ interface rms roughness that has been reduced from 1.6 to 1.1 /spl Aring/ by reducing oxide thicknesses show improved device drive currents. This technique for interfacial smoothing and device performance improvement has the advantage of being easily implemented in today's technology.     

超晶格插入层对Si基上GaN薄膜位错密度的影响

为了降低MOCVD外延生长Si基GaN的缺陷密度,尝试引入超品格插入层.界面突变的超晶格插入层能有效地阻挡由缓冲层延伸出来的位错.即使超晶格本身也产生位错,但位错的产生率比阻挡率低,所以超晶格总体起阻挡作用,可以减少后续生长的 HT-GaN(高温氮化镓)的位错密度.研究了超晶格厚度对 HT-GaN 的位错密度的影响.比较了超晶格厚度不同的3个样品,并采用高分辨双晶X射线衍射(DCXRD)对CaN进行结晶质量的分析,分别用 H3PO4 H2SO4 混合溶液和熔融 KOH 对样品进行腐蚀并用扫描电子显微镜(SEM)对腐蚀的样品进行观察.用 H3PO4 H2SO4 腐蚀过的样品比用KOH 腐蚀过的样品的位错密度大,进一步验证了之前有报道过的 H3PO4 H2SO4 溶液同时腐蚀螺位错和混合位错而 KOH只腐蚀螺位错.分析结果表明.引入适当厚度的超晶格插入层,可以有效地降低后续生长的 GaN 的位错密度.     

Si/Si键合结构的电学性质测量及模拟

研究Si／Si键合的电学性质对于界面研究和微电子器件的制备有着重要意义。分析了亲水处理方法键合的不同Si／Si键合结构的I—V特性，然后用SOS模型对n—Si／n—Si的C—V特性做了计算机辅助模拟，并和实际C—V曲线比较得出了平带电压VFB和界面态密度Din，这些结果对于键合的界面性质的了解和研究都是有意义的。     

Fabrication and mobility characteristics of SiGe surface channel pMOSFETs with a HfO/sub 2//TiN gate stack

This paper describes an extensive experimental study of TiN/HfO/sub 2//SiGe and TiN/HfO/sub 2//Si cap/SiGe gate stacked-transistors. Through a careful analysis of the interface quality (interface states and roughness), we demonstrate that an ultrathin silicon cap is mandatory to obtain high hole mobility enhancement. Based on quantum mechanical simulations and capacitance-voltage characterization, we show that this silicon cap is not contributing any silicon parasitic channel conduction and degrades by only 1 /spl Aring/ the electrical oxide thickness in inversion. Due to this interface optimization, Si/sub 0.72/Ge/sub 0.28/ pMOSFETs exhibit a 58% higher mobility at high effective field (1 MV/cm) than the universal SiO/sub 2//Si reference and a 90% higher mobility than the HfO/sub 2//Si reference. This represents one of the best hole mobility results at 1 MV/cm ever reported with a high-/spl kappa//metal gate stack. We thus validate a possible solution to drastically improve the hole mobility in Si MOSFETs with high-/spl kappa/ gate dielectrics.     

Growth and electrical properties of the (Si/Ge)-on-insulator structures formed by ion implantation and subsequent hydrogen-assisted transfer

Systematic features of endotaxial growth of intermediate germanium layers at the bonding interface in the silicon-on-insulator structure consisting of buried SiO₂ layer implanted with Ge⁺ ions are studied in relation to the annealing temperature. On the basis of the results for high-resolution electron microscopy and thermodynamic analysis of the Si/Ge/SiO₂ system it is assumed that the endotaxial growth of the Ge layer occurs via formation of a melt due to enhanced segregation and accumulation of Ge at the Si/SiO₂ interface. Effect of germanium at the bonding interface on the Hall mobility of holes in silicon layers with nanometer-scale thickness is studied. It is found that the structures including the top silicon layer with the thickness 3–20 nm and incorporating germanium feature the hole mobility that exceeds by a factor of 2–3 the hole mobility in corresponding Ge-free silicon-on-insulator structures.     

Growth of SiGe Films by Cold-wall UHV/CVD Using GeH4 and Si2H6

An ultrahigh vacuum chemical vapor deposition (UHV/CVD) system is introduced.SiGe alloys and SiGe/Si multiple quantum wells (MQWs) have been grown by cold-wall UHV/CVD using disilane(Si2H6) and germane (GeH4) as the reactant gases on Si(100) substrates.The growth rate and Ge contents in SiGe alloys are studied at different temperature and different gas flow.The growth rate of SiGe alloy is decreased with the increase of GeH4 flow at high temperature.X-ray diffraction measurement shows that SiGe/Si MQWs have good crystallinity,sharp interface and uniformity.No dislocation is found in the observation of transmission electron microscopy(TEM) of SiGe/Si MQWs.The average deviation of the thickness and the fraction of Ge in single SiGe alloy sample are 3.31% and 2.01%, respectively.     

Scanning tunneling microscopy investigation of the microtopography of SiO2 and Si surfaces at the Si/SiO2 interface in SIMOX structures

The microtopography of silicon and silicon oxide surfaces in SIMOX structures is investigated by scanning tunneling microscopy. A method of using scanning tunneling microscopy to study Si/SiO₂ interfacial roughness is developed for this purpose. It is shown that the relief of the silicon surface in SIMOX structures is smoother than that of the oxide surface. The observed Si/SiO₂ interfacial roughness is due to oxygen ion implantation in the silicon single crystal. The roughness of the SiO₂ and Si surfaces at the Si/SiO₂ interface is compared for the standard and high-temperature oxidation of the silicon single crystal. Fiz. Tekh. Poluprovodn. 33, 708–711 (June 1999)     

Sealed-Interface Local Oxidation Technology

A new regime of local oxidation, dubbed SILO for Sealed-Interface Local Oxidation, is explored. In SILO processing, a film of silicon nitride is in intimate contact with the silicon surface. The ubiquitous native oxide is effectively eliminated by using nitrogen ion implantation into silicon or plasma-enhanced nitridation to form a "sealing film" of approximately 100-/spl Aring/ in thickness. The oxidation rate of both types of films is characterized and found to be nearly equivalent. A 100-/spl Aring/ film can mask the growth of 7000 /spl Aring/of oxide in wet oxygen at 950/spl deg/C. With a sealed interface it is found that the usual "bird's beak" formation is completely suppressed in local oxidation. An approximate theoretical analysis shows that even a very thin interfacial oxide, acting as a lateral diffusion path for the oxidant species, can lead to a significant bird's beak. With a sealed interface using a 90-/spl Aring/ film, the thick-oxide to bare-silicon transition region is chisel shaped, with approximately 45/spl deg/ slopes. The transition region is even more abrupt if a conventional LPCVD nitride film is deposited on the sealing film before patterning. However, for total nitride thicknesses greater than about 300 /spl Aring/, defects are generated along the pattern edges aligned in [110] directions. Crystal damage generated during oxidation is found to be due to the intrinsic stress in the LPCVD nitride film. Argon-ion implantation into LPCVD nitride is found to be effective in reducing the defect density. A defect-free abrupt profile is produced by combining SILO with a nitride-oxide sandwich.     

Atomic configuration and charge state of hydrogen at dislocations in silicon

The effect of the introduction of hydrogen upon the vibration spectra and electrical characteristics of samples with dislocation networks at the interface of bonded silicon wafers was studied. In order to improve the sensitivity of measurements and to distinguish the signal from dislocation networks in Raman spectra, thin foils conventionally prepared for transmission electron microscopy were used as the sample under investigation. In the samples with dislocation networks, a Raman peak at 2000 cm^–1 was observed. This peak survived after annealing at a temperature of T = 500°C and was not observed in reference samples. Comparison of the experimental data with currently available theoretical calculations allowed one to attribute the observed peak to neutral hydrogen atoms H⁰ at the center of Si–Si bonds. The peak is metastable in the ideal lattice, but becomes stable in the vicinity of dislocations.     

Suppression of high-resistance phases of Ni silicide by Se passivation of Si(100)

High-resistance phases of Ni-rich Ni silicide are formed on Si(100) below 400/spl deg/C, while high-resistance phases of Si-rich Ni silicide are formed above 600/spl deg/C. The desired low-resistance NiSi is formed between 400/spl deg/C and 600/spl deg/C. In this paper, the authors report the suppression of high-resistance phases of Ni silicide by passivating the Si(100) surface with a monolayer of Se. A 500-/spl Aring/ Ni on n-type low 10/sup 15/ cm/sup -3/ doped Si(100) wafers, passivated with Se, shows a sheet resistance of /spl sim/2.55 /spl Omega//square upon annealing between 200/spl deg/C and 500/spl deg/C, while the sheet resistance of the 500-/spl Aring/ Ni on identical wafers without Se-passivation jumps to /spl sim/7.92 /spl Omega//square between 300/spl deg/C and 350/spl deg/C. Between 600/spl deg/C and 700/spl deg/C, the sheet resistance of the Se-passivated samples is /spl sim/ 10% lower than that of the control samples. Transmission electron microscopy, X-ray diffraction, and X-ray photoelectron spectroscopy all confirm that the suppression of high-resistance Ni silicides below 500/spl deg/C is attributed to the suppression of silicidation and above 600/spl deg/C to the delay in Si-rich Ni silicide formation at the Ni/Se-passivated Si(100) interface.     

(001)Si衬底上La0.9Sr0.1MnO3/SrTiO3外延生长薄膜的界面电子显微学研究

本文利用高分辨电子显微术、电子能量损失谱和电子全息技术对Si基体上生长的SrTiO3（STO）和La0.9Sr0.1MnO3（LSMO）薄膜及其STO层和Si基体之间的界面结构进行了深入研究,结果表明在Si和STO层之间由于氧扩散会形成一层过渡的SiOx无序层,且随沉积条件不同界面原子无序层厚度稍有不同;选区电子衍射结果表明薄膜和基体之间的外延生长关系为[001]LSMO//[^-110]Si,[110]LSMO//[001]Si[001]STO,//[001]Si,[010]STO//[110]Si;电子能量损失谱分析表明界面无序层中Si离子的氧化态处于Si^2＋和Si^0之间;电子全息结果清晰地显示了基体与薄膜之间存在明显的相位和势垒变化,负电荷聚集在界面SiOx的无序层中。     

Structure of [110] tilt grain boundaries in zirconia bicrystals

Cubic stabilized zirconia bicrystals with [110] symmetric tilt grain boundaries were fabricated by diffusion bonding of two single crystals with the composition of ZrO2-9.6mol%Y2O3. The structures of symmetric tilt small angle grain boundary and two types of symmetric tilt sigma3 grain boundaries with different grain boundary planes were observed by transmission electron microscopy (TEM). High-resolution transmission electron microscopy (HREM) observations clarified that the [110] small angle tilt grain boundary consists of periodic array of b = a/2[110] type edge dislocations. This result is consistent with Frank's dislocation model for small angle grain boundary. HREM observation also revealed that the 70.5 degrees sigma3 grain boundary shows atomically coherent grain boundary structure with the boundary plane of [111], while the 109.5 degrees sigma3 grain boundary accompanies grain boundary facets taking [111]/[115] asymmetric grain boundary plane. Because of the very low surface energy of [111] plane and/or high lattice matching of [111] and [115] type planes, the grain boundary faceting may be preferred in spite of increasing grain boundary area to about 6%. TEM-energy-dispersive X-ray spectroscopy (EDS) analyses were performed on both sigma3 grain boundaries, and the segregation of yttrium ions to the boundaries was detected in both cases. The amount of segregation is about the same in both sigma3 boundaries. It can be concluded that the segregation of yttrium ions to sigma3 grain boundary exists in cubic zirconia.     

200-mm wafer-scale transfer of 0.18-/spl mu/m dual-damascene Cu/SiO/sub 2/ interconnection system to plastic substrates

We report a low-temperature (<200/spl deg/C) 200-mm wafer-scale transfer of a 0.18-/spl mu/m dual-damascene Cu/SiO/sub 2/ interconnection system to FR-4 plastic substrates using adhesive bonding. We demonstrate removal of the silicon bulk layer to leave behind a flexible 3-/spl mu/m-thick Si back-end-of-line (BEOL) circuit on a 0.1-mm-thick FR-4 wafer. The mechanical and electrical integrity of the thin Si BEOL circuit on FR-4 are confirmed by focused ion beam scanning electron microscope microscopy and current-voltage characterization on a variety of test structures, which include serpentine, via chain and Kelvin test structures on different locations on the wafer. This process will pave the path to allow integration of high-performance submicrometer Si electronics on plastic substrates.     

硅衬底GaN基LED外延生长的研究

采用在AlN缓冲层后原位沉积SiN掩膜层,然后横向外延生长GaN薄膜.通过该法在硅衬底上获得了1.7 μm无裂纹的GaN薄膜,并在此基础上外延生长出了GaN基发光二极管(LED)外延片,其外延片的总厚度约为1.9 μm.采用高分辨率双晶X-射线衍射(DCXRD)、原子力显微镜(AFM)测试分析.结果表明,GaN薄膜(0002)面的半峰全宽(FWHM)降低到403 arcsec,其表面平整度得到了很大的改善;InGaN/GaN多量子阱的界面较平整,结晶质量良好.光致发光谱表明,GaN基LED峰值波长为469.2 nm.     

Atomic scale effects of zirconium and hafnium incorporation at amodel silicon/silicate interface by first principles calculations

First principles calculations aimed at quantifying the effects of zirconium and hafnium incorporation at a model silicon/silicate interface have been performed. The tetrahedral bonding character of silicates allows useful comparisons as well as important new distinctions to be drawn with the familiar Si/SiO₂ system. The calculated energy cost of forming (Zr,Hf)-Si bonds suggests that SiO ₂-like bonding is energetically favored over silicide-like bonding at the Si interface. The calculations also suggest that the volume strain associated with Zr or Hf incorporation may lead to increased stress, both in the bulk oxide and in the interfacial transition region     

Nitrogen bonding configurations near the oxynitride/silicon interface after oxynitridation in N2O ambient of a thin SiO2 gate

The identification of the bonding environments and their progressive modifications upon reaching the oxynitride/silicon interface, in a SiO₂/SiO_xN_y/Si structure, have been investigated by means of X-ray photoemission spectroscopy (XPS). The SiO₂ film was grown at 850 °C by means of a mixed dry-steam process, followed by a 60 min, 950 °C furnace oxynitridation in N₂O gas. A depth profile analysis was carried out by a progressive chemical etching procedure, reaching a residual oxide thickness of about 1.2 nm. XPS analysis of the Si 2p and N 1s photoelectron peaks pointed out that the chemistry of the oxynitride layer is a rather complex one. Four different nitrogen bonding environments were envisaged. Both the overall nitrogen content, which rises up to 2.5%, and its bonding configurations are progressively changing while moving towards the silicon interface.     

用于高亮LED的Si键合研究

在Si和外延层之间使用一层薄金属层作为高效反射镜的所谓"镜面衬底",不但有助于提高芯片的出光效率,同时把键合温度降低到300℃以下。利用Au/In合金的方法,来实现用于高亮LED的Si片与AlGaInP四元外延片的键合。实验表明,在温度为250℃时,利用Au/In作为焊料,Si片与AlGaInP四元外延片可以实现比较好的键合,键合面可以达到60%。通过研磨减薄、X-ray测试和扫描电镜(SEM)测试得出键合面的界面特性,通过能谱分析得出键合面的物质分别为AuIn2和AuIn,实验测试得出此时Au的原子数占33.31%,In的原子数占36.64%。     

Thermal stability of Hfl'aON films prepared by physical vapor deposition

We investigate the thermal stability of HfTaON films prepared by physical vapor deposition using high resolution transmission electronic microscope (HRTEM) and X-ray photoelectron spectroscopy (XPS). The results indicate that the magnetron-sputtered HtTaON films on Si substrate are not stable during the post-deposition an-healing (PDA). HfTaON will react with Si and form the interfacial layer at the interface between HfTaON and Si substrate. Hf-N bonds are not stale at high temperature and easily replaced by oxygen, resulting in significant loss of nitrogen from the bulk film. SiO2 buffer layer introduction at the interface of HfTaON and Si substrate may effec-tively suppress their reaction and control the formation of thicker interfacial layer. But SiO2 is a low k gate dielectric and too thicker SiO2 buffer layer will increase the gate dielectric's equivalent oxide thickness. SiON prepared by oxidation of N-implanted Si substrate has thinner physical thickness than SiO2 and is helpful to reduce the gate dielectric's equivalent oxide thickness.