Device mismatch and tradeoffs in the design of analog circuits

Random device mismatch plays an important role in the design of accurate analog circuits. Models for the matching of MOS and bipolar devices from open literature show that matching improves with increasing device area. As a result, accuracy requirements impose a minimal device area and this paper explores the impact of this constraint on the performance of general analog circuits. It results in a fixed bandwidth-accuracy-power tradeoff which is set by technology constants. This tradeoff is independent of bias point for bipolar circuits whereas for MOS circuits some bias point optimizations are possible. The performance limitations imposed by matching are compared to the limits imposed by thermal noise. For MOS circuits the power constraints due to matching are several orders of magnitude higher than for thermal noise. For the bipolar case the constraints due to noise and matching are of comparable order of magnitude. The impact of technology scaling on the conclusions of this work are briefly explored.     

Comparing MOS and bipolar integrated circuits

In terms of speed and speed/power performance, bipolar integrated circuits are superior to metal-oxide-semiconductor integrated circuits. This superiority is based on the high transconductance inherent in bipolar transistors and is technology-independent. For the MOS case, transconductance is highly technology-dependent, and hence the performance difference will probably diminish in the future. Comparisons of the two technologies in their mid-1966 forms are made; the bipolar performance advantage in most cases is between 10 and 100. MOS integrated circuits have an area-per-function advantage ratio of about 5 for equivalent-function circuits, but a ratio of between 5 and 10 when circuits exploiting the unique MOS properties are considered. In addition, MOS processing is simpler than bipolar processing by approximately 40 percent.     

High-voltage technology offers new solutions for interface integrated circuits

A BIMOS IC technology improving the design of interface circuits that require either high-voltage (up to 120 V) of current (up to a few amperes per output) has been developed. Both bipolar and MOS complementary components are processed together on the same chip for low- and high-voltage applications. Various BIMOS power interface circuits are now in production, e.g., a motor driver, a high-voltage plasma display driver, and a printer head driver. This paper describes the BIMOS technology and the characteristics of its components. As applications, two circuits are presented: the UEB 4732 (plasma display driver) with complementary MOS push-pull output stages (120 V), and the UAA 2081 (stepper motor driver) with power bipolar transistors (1 A per output). Both circuits have a logical part designed with low-voltage CMOS (5-12 V).     

An overview of radiation effects on electronics in the space telecommunications environment

Trapped protons and electrons in the Earth’s radiation belts and cosmic rays present significant challenges for electronics that must operate reliably in the natural space environment. Single event effects (SEE) can lead to sudden device or system failure, and total dose effects can reduce the lifetime of a space-based telecommunications system. One of the greatest sources of uncertainty in developing radiation requirements for a space system is accounting for the small but finite probability that the system will be exposed to a massive solar particle event. Once specifications are decided, standard laboratory tests are available to predict the total dose response of MOS and bipolar components in space, but SEE testing of components can be more challenging. Prospects are discussed for device modeling, and for the use of commercial electronics in space. In addition, technology trends are discussed for the radiation response of microelectronics in space.     

MOS-bipolar monolithic integrated circuit technology

A technique for the fabrication of p-channel MOS transistors and bipolar transistors within monolithic integrated circuits is described. Total process compatibility has been achieved without compromising either the n-p-n bipolar or p-channel MOS characteristics. The technology developed is similar to that used for conventional integrated circuits until the channel oxidation step, A low temperature oxidation followed by a high temperature anneal process that produces negligible changes in preceding diffusion profiles was used to form this oxide. Bias temperature tests of MOS capacitors have shown the oxide to be reproducibly free of contamination. A high slew rate MOS bipolar operational amplifier has been designed and fabricated on 0.045- by 0.045-in chip using the new technology. Typical characteristics are slew rate =80 V/µs voltage gain = 70 dB. The MOS transistors are used as active loads and level shifters in this circuit and provide a much improved frequency response over conventional circuits using p-n-p lateral transistors.     

Generalized translinear circuit principle

It is shown that a generalized interpretation of the translinear (TL) principle leads quite naturally to an extension to MOS circuits. It is shown that two distinct classes of TL circuits exist, one suitable for bipolar and the other for MOS implementation. The MOS-translinear (MTL) circuit principle is derived and an initial classification of simple MTL circuits is proposed. Some examples are given of MTL circuits synthesizing nonlinear functions     

Limitations in microelectronics — II. Bipolar technology

The physical phenomena which will ultimately limit miniaturization of planar bipolar integrated circuits are examined. The maximum packing density is obtained by minimizing the supply voltage and the size of the devices. The minimum transistor size is determined by junction breakdown, punch through and doping fluctuations. For circuits that are fully active the maximum number of circuit functions per chip is determined by power dissipation. The packing density of read-only memories becomes limited by the area occupied by devices and interconnections. The limitations of MOS and bipolar technologies are compared. It is concluded that read-only memories will reach approximately the same performance and packing density with MOS and bipolar technologies, while fully active circuits will reach the highest levels of integration with dynamic MOS or complementary MOS technologies.     

BiCMOS tunable membership function circuits

An MOS transconductance amplifier and bipolar current gain cell structure were investigated. The large input voltage range of the MOS transconductance is preserved, while the gain in the bipolar cell is linearly current controlled. These features make the structure suitable for tunable membership function circuits (MFCs) in a fuzzy controller. Both current-output and voltage-output configurations are proposed.     

VLSI technology for telecommunication ICs

The majority of integrated circuits used in telecommunication applications involves a mix of analog and digital functions. Of the available silicon integrated circuit technologies NMOS, CMOS, and I/SUP 2/L/bipolar appear to be the most suitable for these applications since they can provide low power operation as well as high functional density analog and digital circuits on the same chip. The author reviews the requirements for telecommunications VLSI products, and discusses the choice of suitable IC technologies and the future status of these technologies.     

BiMOS transistors: merged bipolar/sidewall MOS transistors

The concept and feasibility of merged bipolar/sidewall MOS transistors (BiMOS transistors) are demonstrated by fabricating and characterizing the structures. The NMOS-input Darlington pair was merged into an NMOS-input BiMOS Darlington transistor which occupies 1.2 times the area of a single n-p-n bipolar transistor. It should be possible to form other BiCMOS subcircuit elements such as the PMOS-input BiMOS Darlington transistor and BiCMOS static memory cell. An initial analysis of the doping requirements for the base of the n-p-n bipolar transistor and the channel of the sidewall MOS transistors suggests that the requirements are compatible     

Compensation of bipolar monolithic circuits using the parasitic capacitance of diffused resistors

A method of compensating bipolar integrated circuits which uses the parasitic capacitance of diffused resistors is studied. The advantages over other methods are: compatibility with the standard bipolar fabrication process, ease of implementation, and the possibility of controlling the overall bandwidth of an amplifier through adjustment of the bias of a resistor (for variable bandwidth applications or for compensation of process variations). The main drawback is the large size required. The sensitivity to process-parameter variations of the resulting compensation is shown to be comparable to that achieved with a MOS or N/SUP +/P capacitor. The MOS compensation is more stable with temperature variations. The diffused resistor models are shown to yield accurate results as long as a sufficient number of lumped sections are used when large area resistors are considered.     

A 27-mW CMOS fractional-N synthesizer using digital compensationfor 2.5-Mb/s GFSK modulation

A digital compensation method and key circuits are presented that allow fractional-N synthesizers to be modulated at data rates greatly exceeding their bandwidth. Using this technique, a 1.8-GHz transmitter capable of digital frequency modulation at 2.5 Mb/s can be achieved with only two components: a frequency synthesizer and a digital transmit filter. A prototype transmitter was constructed to provide proof of concept of the method; its primary component is a custom fractional-N synthesizer fabricated in a 0.6-μm CMOS process that consumes 27 mW. Key circuits on the custom IC are an on-chip loop filter that requires no tuning or external components, a digital MASH Σ-Δ modulator that achieves low power operation through pipelining, and an asynchronous, 64-modulus divider (prescaler). Measurements from the prototype indicate that it meets performance requirements of the digital enhanced cordless telecommunications (DECT) standard     

Impact of new chip technologies on telecommunications

Microelectronics has revolutionized the architecture and design concepts of telecommunications products dramatically. Its strength is based on the combination of three different disciplines: technology, design automation and device architecture. The evolution in all these topics will be described and illustrated with several examples of telecommunications applications. At present vlsi circuits are used in three important business segments of the telecommunications market: switching, transmission and end-user systems. The technology requirements for these applications are followed by a brief discussion on reliability requirements and future technology trends.     

Design optimization of JCMOS structures

JCMOS structures are based on merging an MOS capacitance, a JFET, and a bipolar transistor in an area of a single MOS transistor. The structure performs the basic operations of temporary storage, writing, and sensing of the stored data. It is used in DRAM, serial dynamic memory, and dynamic logic applications. In addition to the advantages of small size and high speed of operation, the use of the JCMOS structure to implement dynamic logic gates overcomes the problem of charge redistribution associated with conventional and domino CMOS logic circuits. In this paper, the JCMOS structure implementation using a retrograde p-well CMOS process is presented. An analytical model relating terminal voltages and currents to device dimensions and doping levels is derived. Simulation results are presented for both reading and writing modes of operation. A test cell was successfully fabricated to verify the principle of operation, and experimental and theoretical results are compared. A simplified lumped component equivalent circuit, to be used in circuit simulators such as SPICE, is presented, and its validity is investigated. The structure design requirements and procedure are presented. The model is used to optimize the design of the structure.     

Very low-voltage class AB CMOS and bipolar precision currentrectifiers

Simple class-AB CMOS and bipolar precision rectifier circuits that operate from a single supply close to a transistor's threshold voltage are introduced. These circuits have output voltage swings comparable to the supply voltage. Results from simulations of MOS and bipolar precision rectifiers at 20 and 100 MHz, respectively, are presented. Experimental results of a test chip are presented that verify the proposed circuits. A full wave precision rectifier based on the proposed rectifier cells is discussed     

New ECL gate in BiFET process

An ECL gate is implemented as a combination of bipolar and MOS circuits in a BiFET process is presented. The resulting ECL gate exhibits an improved speed-power product over circuits presented in the past. Owing to its reduced power consumption this gate allows a higher level of integration for ECL. The process used is standard BiCMOS.<>     

Computer aided analysis and design of MOS translinear circuits operating in strong inversion

Recently, it was proposed to generalize the well-known translinear circuit principle in such a way that it also applies to MOS transistors operated in strong inversion. In this paper, the MOS translinear (MTL) principle will be briefly reviewed. A graphical analysis method for MTL-circuits is presented, which can also be applied to bipolar translinear circuits. This graphical method was implemented in a computer program, which is now used as an interactive design tool to implement nonlinear signal processing functions by MTL circuits.     

On the application of the Neuron MOS transistor principle formodern VLSI design

In this paper, the speed performance, power consumption, and layout area of Neuron MOS transistor circuits are monitored considering the requirements of modern VLSI design. The Neuron MOS transistor is a recently discovered device principle which has a number of input gates that couple capacitively to a floating gate. The floating gate potential controls the current of a transistor channel. This device can be used in logic circuits. A threshold current through the Neuron MOS transistor can be defined that causes a switching of the output of the logic circuits as soon as the channel current surmounts or falls below the specified value. We designed two different multiplier cells, one based on a Neuron MOS inverter, and the other on a Neuron MOS n-MOSFET which is used as one input device of a comparator circuit. Functionality of both cells is proven for data rates up to 50 MHz which represents the first high-speed measurement of a circuit based on this new design principle. A perspective for the upper speed limit found at more than 500 MHz is given by simulation. The new design principle has a layout area reduced by more than a factor of two compared to usual multiplier cells. Moreover, it is shown, that depending on the design chosen, high speed operation leads to considerable power savings. In view of those advantages it is concluded that the principle of threshold logic qualifies for a major breakthrough for packing density improvement of CMOS-based applications     

A Calibration Technique for Very Low Current and Compact Tunable Neuromorphic Cells: Application to 5-bit 20-nA DACs

Low current applications, like neuromorphic circuits, where operating currents can be as low as a few nanoamperes or less, suffer from huge transistor mismatches, resulting in around or less than 1-bit precisions. A neuromorphic programmable-kernel 2-D convolution chip has been reported where each pixel included two compact calibrated digital-to-analog converters (DACs) of 5-bit resolution, for currents down to picoamperes. Those DACs were based on MOS ladder structures, which although compact require 3N + 1 unit transistors (N is the number of calibration bits). Here, we present a new calibration approach not based on ladders, but on individually calibratable current sources made with MOS transistors of digitally adjustable length, which require only N-sized transistors. The scheme includes a translinear circuit-based tuning scheme, which allows us to expand the operating range of the calibrated circuits with graceful precision degradation, over four decades of operating currents. Experimental results are provided for 5-bit resolution DACs operating at 20 nA using two different translinear tuning schemes. Maximum measured precision is 5.05 and 7.15 b, respectively, for the two DAC schemes.