共查询到20条相似文献,搜索用时 447 毫秒
1.
Amandeep Singh Dinesh Kumar Saini Dinesh Agarwal Sajal Aggarwal Mamta Khosl Balwinder Raj 《半导体学报》2016,37(7):074001-6
The carbon nanotube field effect transistor (CNTFET) is modelled for circuit application. The model is based on the transport mechanism and it directly relates the transport mechanism with the chirality. Also, it does not consider self consistent equations and thus is used to develop the HSPICE compatible circuit model. For validation of the model, it is applied to the top gate CNTFET structure and the MATLAB simulation results are compared with the simulations of a similar structure created in NanoTCAD ViDES. For demonstrating the circuit compatibility of the model, two circuits viz. inverter and SRAM are designed and simulated in HSPICE. Finally, SRAM performance metrics are compared with those of device simulations from NanoTCAD ViDES. 相似文献
2.
This paper presents the design of a VCO-based phase-expanding converter (PEC) that converts a time residue to improve time resolution for the time-domain data converters. A voltage controlled oscillator, which has multiphase structure, is combined with the multi-layer delay chain to generate quadruple phases, and thus expands the overall resolution. Since the architecture of this converter is flexible for different designs, we propose a 6-bit, 250 MHz PEC using a 16-phase, 1 GHz VCO with quadruple phase expander in this paper. Simulations in a 0.18 μm the CMOS process indicate that the PEC has DNL less than ±0.2 LSB LSB, and INL less than ±0.3 LSB. Furthermore, with the frequency variation from 0.9 GHz to 1.1 GHz, the PEC still has DNL ±0.21 LSB, and INL ±0.29 LSB. Experiment results show that the DNL is 0.52–0.13 LSB and the INL is 0.21–0.66 LSB. 相似文献
3.
SET-based nano-circuit simulation and design method using HSPICE 总被引:2,自引:0,他引:2
Fengming Zhang Author Vitae Author Vitae Yong-Bin Kim Author Vitae 《Microelectronics Journal》2005,36(8):741-748
This paper presents a simulation and design method for complementary SET-based nano-circuits from a practical circuit design point of view. HSPICE behavioral implementation of modified Lientschnig's SET model based on the orthodox theory and the Birth-Death Markov chain is demonstrated and verified with Coulomb characteristics. It shows reduced CPU time, improvement of accuracy, and more compatibility with other SPICE softwares on both Windows and Unix platforms. The proposed design methodology presents how to build static CMOS-like SET circuits, and demonstrates that conventional CMOS circuit design methodologies are all applicable to SET circuit designs based on the methodology. HSPICE simulation results show that, for 1 MΩ junction resistance, the power consumption of a SET NAND2 gate is less than 0.3 pW, and the propagation delay for a SET XOR2 gate is 29.8 ns while driving a 10 aF load. 相似文献
4.
Sang-Min Yoo Jong-Bum Park Seung-Hoon Lee Un-Ku Moon 《Circuits and Systems II: Express Briefs, IEEE Transactions on》2004,51(5):269-275
This work describes a 10-b multibit-per-stage pipelined CMOS analog-to-digital converter (ADC) incorporating the merged-capacitor switching (MCS) technique. The proposed MCS technique improves the signal processing speed and resolution of the ADC by reducing the required number of unit capacitors by half in comparison to a conventional ADC. The ADC resolution based on the proposed MCS technique can be extended further by employing a commutated feedback-capacitor switching (CFCS) technique. The prototype ADC achieves better than 53-dB signal-to-noise-and-distortion ratio (SNDR) at 120 MSample/s and 54-dB SNDR and 68-dB spurious-free dynamic range (SFDR) for input frequencies up to Nyquist at 100 MSample/s. The measured differential and integral nonlinearities of the prototype are within /spl plusmn/0.40 LSB and /spl plusmn/0.48 LSB, respectively. The ADC fabricated in a 0.25-/spl mu/m CMOS occupies 3.6 mm/sup 2/ of active die area and consumes 208 mW under a 2.5-V power supply. 相似文献
5.
6.
Yang K. Gutierrez-Aitken A.L. Zhang X. Bhattacharya P. Haddad G.I. 《Electron Devices, IEEE Transactions on》1996,43(9):1470-1472
An HBT model for InP-based single HBTs (SHBTs) was developed based on the conventional Gummel-Poon large-signal BJT model available in HSPICE. Several typical characteristics observed from InP-based SHBTs, such as soft breakdown and collector transit-time delay effects, were modeled through a macro modeling approach. Excellent agreement has been achieved between the experimental and calculated results based on the model 相似文献
7.
This paper introduces a circuit technique to increase the operating speed of CMOS/ECL interface circuits. The technique is based on shifting the reference voltage dynamically to follow the ECL input signal. HSPICE simulation results based on a 0.8-μm BiCMOS technology show the advantages of DRV CMOS/ECL in terms of speed and noise margins. An analytical delay model which fits HSPICE simulation results is addressed. The error between the model and the circuit simulator is within 4% 相似文献
8.
为研究瞬态电磁脉冲故障注入对集成电路芯片的影响及其故障机理,基于Marx发生器原理和MOSFET开关特性,研制了一个全固态纳秒级电磁脉冲发生器.基于提出的HSPICE软件仿真等效模型,分析了发生器电路主要寄生参数对MOSFET开关特性的影响,并建立了相应的数学模型,为电磁脉冲发生器的研制提供了设计指南.实验结果表明:建立的数学模型精度为96.7%;基于二级Marx电路的电磁脉冲发生器可产生幅值可调(0~100 V)、脉宽可变(200~2 070 ns)、最快下降沿为32 ns的脉冲信号;在电磁探头下方5 mm处的测试线圈上可测得1 600 mV的感应电动势,并可利用该感应电动势来对芯片引入故障. 相似文献
9.
In this paper, application of adaptive neuro-fuzzy inference system (ANFIS) in modeling of CMOS logic gates as a tool in designing and simulation of CMOS logic circuits is presented. Structures of the ANFIS are developed and trained in MATLAB 7.0.4 program. We have used real hardware data for training the ANFIS network. A hybrid learning algorithm consists of back-propagation and least-squares estimation is used for training. Influence of the structure of the proposed ANFIS model on accuracy and network performance has been analyzed through some combinational circuits. For the comparison of the ANFIS simulation results, we have simulated the circuits in HSPICE environment with 0.35 μm process nominal parameters. The comparison between ANFIS, HSPICE, and real hardware shows the feasibility and accuracy of the proposed ANFIS modeling procedure. The results show the proposed ANFIS simulation has much higher speed and accuracy in comparison with HSPICE simulation and it can be simply used in software tools for designing and simulation of complex CMOS logic circuits. 相似文献
10.
A SPICE model for power plane simulation has been developed. It is based on the geometries and materials of the power planes and uses a unit cell composed of RLC elements, transmission line elements or the HSPICE W-element. Simulated resonances in the frequency domain and delays in the time domain are consistent with results calculated from physical dimensions. SPICE model simulations compare well with hardware measurements in both the frequency and time domains. The role of dielectric thickness, dielectric constant and parallel pairs of power planes is demonstrated through simulation. The spreading inductance of power planes is defined, discussed and measured. Power plane performance in terms of impedance, resonances, damping and spreading inductance is optimized by the use of a thin dielectric layer between conductive planes 相似文献
11.
Cheng-Chieh Chang Shen-Iuan Liu 《Electronics letters》2000,36(16):1335-1336
A current-mode pseudo-exponential circuit is presented based on Taylor's series expansion. It is composed of MOS transistors operating in saturation and its input range can be tuned by adjusting the biased current. The proposed circuit has been verified in 0.8 μm CMOS technology by HSPICE simulations. The simulation results confirm the feasibility of the proposed pseudo-exponential circuit 相似文献
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13.
To facilitate test vector generation for high-speed circuits, we present the design and circuit simulation of parallel pseudorandom number generators in GaAs technology. These PRNGs are based on hybrid cellular automata (CA) in which mixtures of local rules are employed in one dimensional arrays, with minimal delay due to having only local wiring between neighboring cells. HSPICE simulations of these circuits demonstrate that they operate at a clock frequency above 1 GHz. Delay simulations indicate that GaAs PRNGs based upon linear feedback shift registers, in contrast with hybrid CAs, exhibit a degradation in clock frequency due to the effects of global interconnects, and that this degradation increases with the register length.This work was supported by Micronet, by the Canadian Microelectronics Corporation, and by the Natural Sciences and Engineering Research Council of Canada. 相似文献
14.
Sergio Saponara Tommaso Baldetti Luca Fanucci Emilio Volpi Francesco D’Ascoli 《Analog Integrated Circuits and Signal Processing》2011,66(3):407-416
To obtain a high performance CMOS resistor string digital-to-analog converter (DAC), one of the key design issues is the mismatch
in the resistor ratio. This mismatch causes nonlinearity errors such as integral nonlinearity (INL) and differential nonlinearity
(DNL), degrading the performances of the converter. Usually these matching properties are taken into account during the design
phase by using time consuming and computational intensive transistor-level Monte Carlo simulations for the process technology
corner. Recent research aims at reducing the design time by exploiting high-level modeling of converters as a trade-off between
simulation time and modelling accuracy. In this work an analytical model for resistor mismatch in DACs is presented and implemented
in MATLABTM environment. The model utilizes geometrical size of resistors and statistical data of the technology process. Starting from
random process variations on geometries it was possible to estimate DNL and INL with very short time simulations. The proposed
model is valid both for single stage resistor string DACs or segmented ones. The model can be used to speed up the design
of resistor-string based DACs, or as a starting point to develop more accurate models by taking into account high-order effects.
The model was successfully used to design a 10bit resistor string DAC in a 0.18 μm BCD technology with DNL and INL lower than
1 LSB (in absolute value). Since the complexity of the DAC is dominated by the resistor string, its optimization since the
early design steps, enabled by the proposed high-level model, allowed to minimize area versus state of the art. 相似文献
15.
Deviation of threshold voltage and effective mobility due to random dopant fluctuation is proposed.An improved 65 nm average drain current MOS model calledαlaw is utilized after fitting HSPICE simulating data and extracting process parameters.Then,a current mismatch model of nanoscale MOSFETs induced by random dopant fluctuation is presented based on propagation of variation theory.In test conditions,the calculated standard deviation applying this model,compared to 100 times Monte-Carlo simulation data with HSPICE,indicates that the average relative error and relative standard deviation is 0.24%and 0.22%,respectively.The results show that this mismatch model is effective to illustrate the physical mechanism,as well as being simple and accurate. 相似文献
16.
本文设计了用于14bit逐次逼近型模数转换器(SAR ADC)的DAC电路。针对该DAC,介绍一种全差分分段电容阵列结构以缩小DAC的版图面积;高二位权电容采用热码控制,用以改善高位电容在转换时跳变的尖峰以及DAC的单调性;对电容阵列采用数字校准技术,减小电容阵列存在的失配,以提高SAR ADC精度。校准前,SAR ADC的INL达到10LSB,DNL达到4LSB;与校准前相比,校准后,INL〈0.5LSB,DNL〈0.6LSB。仿真结果表明,本DAC设计极大改善SAR ADC的性能,已达到设计要求。 相似文献
17.
Mostafa Parvizi 《International Journal of Electronics》2019,106(3):440-454
ABSTRACTIn this article, a new low-power multiple-input, single-output (MISO) multi-mode universal biquad operational transconductance amplifier-capacitor (OTA-C) filter with a minimum number of active and passive components is proposed. The proposed filter employs three OTAs, one inverter and two grounded capacitors. The proposed filter can realise all filter frequency responses including low-pass (LP), band-pass (BP), high-pass (HP), band-stop (BS) and all-pass (AP) in all operation modes including voltage, current, tranasresistance and transconductance modes using the same topology. Furthermore, sensitivity analysis is done which shows that the proposed filter has a low sensitivity to the values of the active and passive elements. The proposed filter is simulated in HSPICE using 0.18 µm CMOS technology. The HSPICE simulation results demonstrate that the proposed filter consumes only 35 μW at 2.5 MHz from a ±0.5 V supply voltage, while all of the transistors are biased in strong inversion region. Also, the simulation results are in a close agreement with the theoretical analysis which is done in MATLAB. Furthermore, the process, voltage and temperature variation simulations are done to study the effect of non-idealities on the performance of the proposed filter. It is shown that the simulation results justify a 4.8%, 0.8% and 20% variations of the centre frequency for process, voltage and temperature, respectively. Finally, Monte-Carlo, noise and transient simulations are done to justify the good performance of the proposed filter performance. 相似文献
18.
Hao-Chiao Hong 《Journal of Electronic Testing》2007,23(6):527-538
Evaluating the digital stimuli used in the design-for-digital-testability (DfDT) Σ-Δ modulator is a time-consuming task due
to its oversampling and non-linear nature. Although behavioral simulations can substantially improve the simulation speed,
conventional behavioral models fail to provide accurate enough signal-to-noise ratio (SNR) predictions for this particular
application. In this paper, a fully-settled linear behavior plus noise (FSLB+N) model for the DfDT Σ-Δ modulator is presented
to improve both the accuracy and the speed of the behavioral simulations. The model includes the following parameters: the
finite open-loop gains, the offsets, the finite output swings, the flicker noise of the operational amplifiers (OPAMPs), as
well as the thermal noises of the switched capacitors, the OPAMPs, and the reference supplies. With the proposed model, the
behavioral simulation results demonstrate a high correlation with the measurement data. On average, the SNR difference between
the simulation and the measurement is –1.1 dB with a maximum of 0.05 dB and a minimum of –2.2 dB. Comparing with the circuit-level
simulation using HSPICE, the behavioral simulation with the FSLB+N model is 1,190,000 times faster. The proposed model not
only can be used for evaluating the digital stimulus candidates, but also can be applied to system-level simulations of the
mixed-signal design with an embedded DfDT Σ-Δ modulator.
相似文献
Hao-Chiao HongEmail: |
19.
An accurate model for dynamic crosstalk analysis of CMOS gate driven on-chip interconnects using FDTD method 总被引:1,自引:0,他引:1
An accurate and time efficient model of CMOS gate driven coupled-multiple interconnects is presented in this paper for crosstalk induced propagation delay and peak voltage measurements. The proposed model is developed using the finite difference time domain (FDTD) technique for coupled RLC interconnects, whereas the alpha power law model is used to represent the transistors in a CMOS driver. As verified by the HSPICE simulation results, the transient response of the proposed model demonstrates high accuracy. Over the random number of test cases, crosstalk induced peak voltage and propagation delay show average errors of 1.1% and 4.3%, respectively, with respect to HSPICE results. 相似文献
20.
《Microelectronics Journal》2015,46(5):351-361
A system designer needs to estimate the behavior of a system interconnection based on different patterns of switching which happen around an interconnect. Two different scenarios are supposed to estimate the effect of interconnect issues on system performance. First, based on a normalization technique for decreasing the number of a transfer function variables, a definitive environment for one interconnect is considered and an optimized look-up-table for the wire time delay is generated. Using some sampling methods, fast accessible look-up-tables are proposed for CAD tools in very simple and small one. A 4×4×4 table for the wire delay is introduced which results in very fast estimation. The average and maximum error of this look-up-table is less than 1% and 7.7% respectively, compared to HSPICE results. Second, the statistical environment of a wire in a BUS configuration is studied for all possible different switching patterns happening for the wires. Estimating the BUS main problems, including power consumption, crosstalk, and propagation delay for a random environment, which a wire senses in wide BUS, is only possible with statistical parameters like mean and variance. All simulations are done considering both wire inductive and capacitive couplings in HSPICE. Also, the secondary effect of crosstalk on propagation delay and power consumption is considered. The simulation results show 3.81% of BUS input switching can lead to a wrong decision on its wire load due to the crosstalk induced voltages in 90 nm technology. The average induced crosstalk aware power consumption is 94 μW. Also, the average of maximum crosstalk on the load can be as high as 25% of the Vdd. 相似文献