基于ATPG的最大功耗估算改进算法

在大规模集成电路芯片的可靠性分析和性能评估中,功耗估算起着重要的作用,文中提出基于ＡＴＰＧ的最大功耗估算改进算法,通过对电路充放电节点分配信号翻转,使电路工作时的动态功耗最大化;研究了路径搜索空间与功耗估值的关系,减少了路径搜索的开销,加快了估算时间;同时将算法扩展到同步时序电路。     

基于信息论的时序电路演化设计

时序电路由于存在反馈连接,因此是数字型演化硬件研究中的难点问题。为此,对时序电路的演化设计方法进行改进,提出一种针对时序电路演化的虚拟可重构平台,阐述在此平台上演化时序电路的方法。基于信息论改进电路的适应度评估方法,以目标函数和电路实测输出之间的信息熵设计适应度评估函数。实验结果表明,该方法具有较好的稳定性和全局寻优能力。     

基于差错传播概率矩阵的时序电路软错误可靠性评估

在深亚微米及纳米级集成电路设计过程中,电路的可靠性评估是非常重要的一个环节.该文提出了一种基于差错传播概率矩阵(Error Propagation Probability Matrix,EPPM)的时序电路软错误可靠性评估方法,即先将逻辑门和触发器在当前时钟周期对差错的传播概率用4种EPPM表示,再利用自定义的矩阵并积运算计算多周期情况下的差错传播概率,最后结合二项分布的特点计算时序电路的可靠度.用ISCAS' 89基准电路为对象进行实验,结果表明所提方法是准确和有效的.     

一种基于迭代PTM模型的电路可靠性评估方法

纳米工艺的快速发展既给电路设计创造了新的机会,同时也带来了新的挑战,基于纳米器件的电路可靠性设计便是主要挑战之一,因此有必要研究在设计的早期阶段便能准确地评估电路可靠性的方法.考虑到经典的概率转移矩阵方法在电路可靠性计算中的优势与不足,文中提出了宏门的概念和以宏门为单位的迭代概率转移矩阵模型,并设计了相应的电路可靠性评估算法,可计算从原始输入到任意引线位置的电路可靠度,该算法的复杂性与宏门的数目成线性关系.理论分析与在74系列电路和ISCAS85基准电路上的实验结果证明了文中所提方法的准确性、有效性及潜在的应用价值.     

基于HDL仿真的同步时序电路演化方法

时序电路存在反馈环,不便于电路描述和软件仿真,很难进行演化。为此,以D触发器和逻辑门为基本单元,构建描述时序电路的全向连接电路网络模型。建立电路编码、电路拓扑与硬件描述语言(HDL)代码文件之间的映射关系,设计由电路编码获取相应HDL代码的方法,利用批处理技术实现电路评估过程的自动运行。四倍分频器电路演化实验结果验证了该方法的可行性与有效性。     

异步时序电路分析一种OBDD方法

对异步时序电路的分析和使用是一个比较困难的问题,所以,异步时序电路的实际应用范围远不如同步时序电路,通过改进JRBurch等提出的分析方法,使之适用于异步时序电路,该方法使用基于OBDD的布尔特征函数来表示电路的转移关系,并通过基于OBDD的布尔函数的运算涞确定异步时序电路的稳定状态,及当输入改变时电路的下一个稳定状态,由此可实现对电路特性的精确描述。     

基于敏感寄存器替换的电路软错误率与开销最优化

随着集成电路的发展,逻辑电路对放射性粒子引起的软错误越来越敏感.现有的电路加固技术通常会带来较大的面积开销.综合考虑电路的软错误率和面积开销,提出一种新的电路加固评估指标FAP,并提出基于贪婪算法的寄存器替换技术,通过将电路的部分敏感寄存器替换为冗余寄存器来免疫电路中的软错误.针对贪婪算法有时不能达到可靠性和开销整体最优的局限,进一步提出可靠性-开销最优的启发式替换算法.实验结果表明,基于贪婪算法的寄存器替换技术只需50%的面积开销就可降低90%的电路软错误率;而可靠性-开销最优的启发式替换算法只需45%左右的面积开销,电路软错误率就降低达90%以上.与其他已有技术相比,电路软错误免疫技术在可靠性和面积开销间达到了更好的折中.     

基于虚拟可重构平台的时序电路演化设计

目前,电路进化设计是演化硬件研究的主要方向之一。而时序电路由于存在反馈环不便于进行电路描述和软件仿真。文中对时序电路的演化设计方法进行了改进,提出了专门针对时序电路演化的虚拟可重构平台,建立起电路编码与HDL代码的映射关系。应用TEXTIO和MATLAB来辅助仿真测试过程,使测试向量数量巨大、难以处理的问题得到很好地解决。最后调用ModelSim完成了FSM的演化实验。实验结果验证了基于此平台演化时序电路的可行性和有效性。     

时序电路逻辑初始化问题研究

讨论同步时序电路初始化问题,提出了一种基于电路存储元件逻辑定级和可控性分析的同步时序电路逻辑初始化方法。同时也给出了针对ISCAS89电路的一些实验结果。     

基于概率转移矩阵的电路可靠性并行计算方法

随着电路集成度的提高,软差错已经成为影响可靠性的关键因素.概率转移矩阵是一种用于估计软差错对电路影响的有效方法,它通过对门级电路建立概率模型来计算电路的可靠性.本文基于概率转移矩阵研究计算电路可靠性的并行方法,提出了一种电路分割算法,在对电路进行划分后,并行地计算各个模块的概率转移矩阵,再合成对应于整个电路的概率转移矩阵.其中,引入了代数决策图压缩矩阵存储空间.初步的实验结果表明,该并行算法可以有效地减少21.46%的平均时间开销.     

组合逻辑电路的软错误率自动分析平台

为在设计阶段快速评估集成电路的软错误率,以指导高可靠集成电路的设计,提出一种适用于组合逻辑电路和时序逻辑电路组合逻辑部分的快速软错误率自动分析平台HSECT-ANLY.采用精确的屏蔽概率计算模型来分析软错误脉冲在电路中的传播;用向量传播和状态概率传播的方法来克服重汇聚路径的影响,以提高分析速度;使用LL(k)语法分析技术自动解析Verilog网表,使分析过程自动化,且使得本平台可分析时序电路的组合逻辑部分.开发工作针对综合后Verilog网表和通用的标准单元库完成,使得HSECT-ANLY的实用性更强.对ISCAS'85和ISCAS'89 Benchmark电路进行分析实验的结果表明:文中方法取得了与同类文献相似的结果,且速度更快,适用电路类型更多,可自动分析电路的软错误率并指导高可靠集成电路的设计.     

Microscopic verification of sensitive circuits of a quartz resonator applied in dew point recognition

This paper is aimed to carry out experimental verification of sensitive circuits of a quartz resonator applied in dew point recognition and it is proven at a microscopic level to be feasible in dew point recognition with great reliability and accuracy by using the high speed video. The sensor based on the sensitive circuits of a quartz resonator is composed of a quartz crystal and a Peltier module. Proactive approach is taken to produce condensation on the surface of the quartz crystal. The electrical parameters of the quartz crystal is changed due to dew condensation and then the resonant circuit stops oscillating. Initially, it needs to analyze the oscillation circuit and electrical characteristics of the quartz crystal, and then take photos of the surface of quartz electrodes with the high speed camera and microscope. Gray statistics is made for images of dew formation in its whole process. When the statistical results are analyzed in comparison to oscillation of the circuit, it shows that the time of the circuit oscillation stopping is roughly consistent with the time when moisture condensation occurs on the surface of the quartz electrode. And the time error of the two phenomena is less than 0.5 s, which is much less than response time of the platinum resistance sensor to the temperature. Furthermore, the results provide a strong theoretical basis for further measurement of the dew point temperature by this recognition method.     

形式验证中同步时序电路的VHDL描述到S2-FSM的转换

符号模型检查（ＳｙｍｂｏｌｉｃＭｏｄｅｌＣｈｅｃｋｉｎｇ,ＳＭＣ）是一种有效的形式验证方法．该方法主要有２个难点：一个是建模,即如何建立并用有限内存来表示电路的状态机模型;另一个是在此模型基础上的验证算法．由于验证时间和有限状态机模型的大小是直接相关的,因而模型的大小就成为ＳＭＣ中的关键问题．本文提出一种基于同步电路行为描述的新的有限状态机模型Ｓ２－ＦＳＭ,并给出从同步电路的ＶＨＤＬ描述建立这种模型的过程．由于该模型的状态转换函数是基于时钟周期的,消去了与时钟无关的大量中间变量,所以同Ｄｅｈａｒｂｅ提出的模型相比,它的状态数大大减少．若干电路的实验结果表明,该模型由于减少了状态规模,建模时间和可达性分析时间大大减少,效果十分显著．     

Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus

The reliability of FPGA based hardware designs has become an important field of research particularly for space computing. Traditionally, redundancy is utilized in FPGA based designs to achieve reliable or error-tolerant computing. However, the redundant designs vary according to the granularity level and the voter placement algorithms used for the hardware design. The resulting circuit configurations vary in area, latency and power as well as in the achieved reliability. While the evaluation of area, latency and power is done by the FPGA design tools, quantitative data for reliability are usually not derived. Consequently, there is a need for an automated reliability evaluation tool especially considering the huge design space of redundant circuit structures. In this paper, we combine the Boolean difference error calculator (BDEC), a probabilistic reliability model for hardware designs, with a reliability model for fault-tolerant circuit structures. As a result, we are able to study the reliability of fault-tolerant circuit structures at the logic layer. We focus on fault-tolerant circuits to be implemented in FPGAs and show how to extend our combined model from combinational to sequential circuits. For an automated analysis, we develop a MATLAB-based tool utilizing our extended BDEC model. With this tool, we conduct a case study on dynamic reliability management and show how quantitative reliability data obtained from this tool improves the four-dimensional Pareto optimization for area, latency, power and reliability.     

功耗限制下RTL数据通路非扫描BIST方法的延时分析

可测性设计（DFT）方法广泛应用于数字电路测试中．通过添加测试硬件,用来降低测试的复杂性。但添加测试硬件后,往往会引起电路的延时变大,从而降低电路的性能,甚至引起延时故障。针对寄存器传输级（RTL）数据通路,文献[1]提出了两种功耗限制下非扫描内建自测试（BIST）方法。跟以前的方法相比较,这两个方法取得较短的测试应用时间和较低的测试硬件开销。本文对这两个方法对电路延时的影响进行分析。实验结果表明,在保持同样的测试应用时间和测试硬件开销的前提下,电路的延时有稍微增加。     

Hitest: A Knowledge-Based Test Generation System

Efforts to develop computer-based automatic test generation for digital circuits have been generally unsuccessful, except in the case of combinational circuitry. Current ATPG methods for sequential circuits often require a considerable amount of computer time and generate unstructured test waveforms of limited value. Experienced human test programmers, on the other hand, appear to have little difficulty in generating high-quality tests for complex sequential circuits when they have a good understanding of how the circuit operates. This article considers the causes of failure in automatic test generation algorithms and describes a new system called Hitest. This system lets the computer use human understanding of circuit operations to generate more effective tests.     

Critical transistors nexus based circuit-level aging assessment and prediction

Accurate age modeling, and fast, yet robust reliability sign-off emerged as mandatory constraints in Integrated Circuits (ICs) design for advanced process technology nodes. In this paper we introduce a novel method to assess and predict the circuit reliability at design time as well as at run-time. The main goal of our proposal is to allow for: (i) design time reliability optimization; (ii) fine tuning of the run-time reliability assessment infrastructure, and (iii) run-time aging assessment. To this end, we propose to select a minimum-size kernel of critical transistors and based on them to assess and predict an IC End-Of-Life (EOL) via two methods: (i) as the sum of the critical transistors end-of-life values, weighted by fixed topology-dependent coefficients, and (ii) by a Markovian framework applied to the critical transistors, which takes into account the joint effects of process, environmental, and temporal variations. The former model exploits the aging dependence on the circuit topology to enable fast run-time reliability assessment with minimum aging sensors requirements. By allowing the performance boundary to vary in time such that both remnant and nonremnant variations are encompassed, and imposing a Markovian evolution, the probabilistic model can be better fitted to various real conditions, thus enabling at design-time appropriate guardbands selection and effective aging mitigation/compensation techniques. The proposed framework has been validated for different stress conditions, under process variations and aging effects, for the ISCAS-85 c499 circuit, in PTM 45 nm technology. From the total of 1526 transistors, we obtained a kernel of 15 critical transistors, for which the set of topology dependent weights were derived. Our simulation results for 15 critical transistors kernel indicate a small approximation error (i.e., mean smaller than 15% and standard deviation smaller than 6%) for the considered circuit estimated end-of-life (EOL), when comparing to the end-of-life values obtained from Cadence simulation, which quantitatively confirm the accuracy of the IC lifetime evaluation. Moreover, as the number of critical transistors determines the area overhead, we also investigated the implications of reducing their number on the reliability assessment accuracy. When only 5 transistors are included into the critical set instead of 15, which results in a 66% area overhead reduction, the EOL estimation accuracy diminished with 18%. This indicates that area vs. accuracy trade-offs are possible, while maintaining the aging prediction accuracy within reasonable bounds.     

Sequential approach to reliability analysis of multidisciplinary analysis systems

The goal of this study is to present an efficient strategy for reliability analysis of multidisciplinary analysis systems. Existing methods have performed the reliability analysis using nonlinear optimization techniques. This is mainly due to the fact that they directly apply multidisciplinary design optimization (MDO) frameworks to the reliability analysis formulation. Accordingly, the reliability analysis and the multidisciplinary analysis (MDA) are tightly coupled in a single optimizer, which hampers the use of recursive and function-approximation-based reliability analysis methods such as the first-order reliability method (FORM). In order to implement an efficient reliability analysis method for multidisciplinary analysis systems, we propose a new strategy named sequential approach to reliability analysis for multidisciplinary analysis systems (SARAM). In this approach, the reliability analysis and MDA are decomposed and arranged in a sequential manner, making a recursive loop. The key features are as follows. First, by the nature of the recursive loop, it can utilize the efficient advanced first-order reliability method (AFORM). It is known that AFORM converges fast in many cases and requires only the value and the gradient of the limit-state function. Second, the decomposed architecture makes it possible to execute concurrent subsystem analyses for both the reliability analysis and MDA. The concurrent subsystem analyses are conducted by using the global sensitivity equation (GSE). The efficiency of the SARAM method was verified using two illustrative examples taken from the literatures. Compared with existing methods, it showed the least number of subsystem analyses over the other methods while maintaining accuracy.     

Adaptive virtual support vector machine for reliability analysis of high-dimensional problems

In this paper, an efficient classification methodology is developed for reliability analysis while maintaining an accuracy level similar to or better than existing response surface methods. The sampling-based reliability analysis requires only the classification information—a success or a failure—but the response surface methods provide function values on the domain as their output, which requires more computational effort. The problem is even more challenging when dealing with high-dimensional problems due to the curse of dimensionality. In the newly proposed virtual support vector machine (VSVM), virtual samples are generated near the limit state function by using an approximation method. The function values are used for approximations of virtual samples to improve accuracy of the resulting VSVM decision function. By introducing the virtual samples, VSVM can overcome the deficiency in existing classification methods where only classification values are used as their input. The universal Kriging method is used to obtain virtual samples to improve the accuracy of the decision function for highly nonlinear problems. A sequential sampling strategy that chooses new samples near the limit state function is integrated with VSVM to improve the accuracy. Examples show the proposed adaptive VSVM yields better efficiency in terms of modeling and response evaluation time and the number of required samples while maintaining similar level or better accuracy, especially for high-dimensional problems.