Cross parity check convolutional codes

A class of convolutional codes called cross parity check (CPC) codes, which are useful for the protection of data stored on magnetic tape, is described and analyzed. CPC codes are first explained geometrically; their construction is described in terms of constraining data written onto a tape in such a way that when lines of varying slope are drawn across the tape, the bits falling on those lines sum to zero modulo two. This geometric interpretation is then formalized by the construction of canonical parity check matrices and systematic generator matrices for CPC codes and by computing their constraint lengths. The distance properties of CPC codes are analyzed, and it is shown that these codes are maximum distance separable convolutional codes. In addition, examples are given of both error and erasure decoding algorithms that take advantage of the geometric regularity of CPC codes. The technique of parity check matrix reduction, which is useful for reducing the inherent decoding delay of CPC codes, is described. The technique consists of dividing each term of the parity check matrix by some polynomial and retaining only the remainder. A class of polynomials that are particularly attractive for this purpose if identified     

FIR parity check codes

This paper describes a method for packet synchronization and error detection for use in a synchronous digital communications system. The method relies upon a class of linear block codes that have parity checks that are expressed in terms of a finite-impulse response (FIR) filter. This system is incorporated in the newly established ITU standard of digital cable television standard, J.83 appendix B, which is based on an MPEG 2 transport packet data stream. This technique is also the basis for cable modem downstream transmission defined in the IEEE 802.14 and MCNS standards. The parity check structure is based on a pseudonoise sequence generated by a (binary) primitive polynomial. This structure allows for a computationally efficient implementation of the parity check FIR filter, in a recursive manner, that is none the less self-synchronizing. The FIR parity check codes that are described are characterized as the dual of a CRC-type, shortened cyclic code. The theory and computational structure of these codes are presented here; the J.83R code is used as an example of the general theory     

Efficient burst-correcting cyclic codes

A class of single burst error-correcting cyclic codes is introduced. The binary version of these codes has block length n = 2m ? 1, number of parity check digits n ? k = 2m?1, and correct bursts of length b = 2m?2, where m is an integer. These codes achieve the upper bound b ?(n ? k)/2, and normally have more information digits than interleaved codes of the same burst-correcting power. The multilevel case is also treated in the letter.     

Design of Quasi‐Cyclic Low‐Density Parity Check Codes with Large Girth

In this paper we propose a graph‐theoretic method based on linear congruence for constructing low‐density parity check (LDPC) codes. In this method, we design a connection graph with three kinds of special paths to ensure that the Tanner graph of the parity check matrix mapped from the connection graph is without short cycles. The new construction method results in a class of (3, ρ)‐regular quasi‐cyclic LDPC codes with a girth of 12. Based on the structure of the parity check matrix, the lower bound on the minimum distance of the codes is found. The simulation studies of several proposed LDPC codes demonstrate powerful bit‐error‐rate performance with iterative decoding in additive white Gaussian noise channels.     

卷积码盲识别方法研究

提出了一种码率删除卷积码的盲识别算法.该算法基于卷积码的线性特性和校验性质,利用一种优化方法求解二元域线性方程组,估计出校验多项式矩阵,并建立删除卷积码的数学变换模型,由校验多项式矩阵估计出删除卷积码的源码生成多项式矩阵和删除模式.     

The single burst error detection performance of binary cyclic codes

Using a new statistical model for burst errors, the authors calculate the conditional probability of undetected error for CRC codes with generator polynomials of the form g(x)=(1+x)p(x), p(x) a primitive polynomial. They show that the choice of p(x) affects the performance of these codes     

Early detection of successful decoding for dual-diagonal block-based LDPC codes

Low-density parity-check (LDPC) codes [1] have attracted much attention in the last decade owing to their capacityapproaching performance. LDPC codes with a dual-diagonal blockbased structure can be encoded in linear time with lower encoder hardware complexity [2]. This class of LDPC codes is adopted by a number of standards such as wireless LAN (IEEE 802.11n) [3], wireless MAN (IEEE 802.16e, WiMAX) [4] and satellite TV (DVB-S2) [5]. LDPC codes are commonly decoded by the iterative belief-propagation (BP) algorithm. The decoder checks the parity-check equations to detect successful decoding at the end of the iteration. The Tanner graph of an irregular LDPC code consists of nodes with different degrees such that coded bits have unequal error protection [6]. Coded bits associated with higher degree nodes tend to converge to the correct answer more quickly. Hence, in order to give better protection to the transmitted data, data bits are always mapped to higher degree nodes whereas parity bits are mapped to lower degree nodes in the encoding process. The commonly used parity-check equations Hc t ? 0t will be satisfied after all the coded bits are correctly decoded. However, as discussed above, data bits converge to the correct answer much more quickly than parity bits, so some unnecessary iterations are wasted waiting for the parity bits to be decoded. In this Letter, a new set of low-complexity check equations are derived for dual-diagonal block-based LDPC codes. Early detection of successfully decoded data can be achieved by exploiting the structure and degree of distribution of the dual-diagonal parity check matrix. The decoder power, speed and complexity can be improved by adopting these equations. Simulation shows that the coding gain performance is little changed.     

一种高性能低复杂度的非规则LDPC码的构造方法

该文提出了一种基于置换矩阵(permutation matrix)的非规则低密度奇偶校验(LDPC)码构造方法。首先,提出了基于改进eIRA(IeIRA)算法的全局矩阵M;接着,通过对全局矩阵H进行矩阵置换,生成LDPC码的校验矩阵H;研究了校验矩H中短圈(short cycle)长度与置换矩阵循环移位系数的关系,通过选择循环移位系数,以达到改善误比特率性能的目的。仿真结果表明,该文提出的构造方法在保证线性编码复杂度的前提下,增大了码字的最小距离,减少了小停止集合(stopping set)的数量,降低了误比特率的差错平台(error floor)(达到10-9)。     

Semi‐random LDPC codes for CDMA communication over non‐linear band‐limited satellite channels

This paper considers the application of low‐density parity check (LDPC) error correcting codes to code division multiple access (CDMA) systems over satellite links. The adapted LDPC codes are selected from a special class of semi‐random (SR) constructions characterized by low encoder complexity, and their performance is optimized by removing short cycles from the code bipartite graphs. Relative performance comparisons with turbo product codes (TPC) for rate 1/2 and short‐to‐moderate block sizes show some advantage for SR‐LDPC, both in terms of bit error rate and complexity requirements. CDMA systems using these SR‐LDPC codes and operating over non‐linear, band‐limited satellite links are analysed and their performance is investigated for a number of signal models and codes parameters. The numerical results show that SR‐LDPC codes can offer good capacity improvements in terms of supportable number of users at a given bit error performance. Copyright © 2006 John Wiley & Sons, Ltd.     

Application of Error-Correcting Codes in Computer Reliability Studies

The use of error-correcting codes as one of the important techniques to increase computer system reliability is introduced. The different codes used in the central processing unit (CPU) are described. Since the CPU usually contains the data path, logic, and arithmetic units, the codes used in this area are error-detecting codes, such as parity check codes and residue codes. The codes used or suggested for the memory system are discussed, emphasis being placed on parity check codes, two-dimensional codes, Hamming codes and other recently developed codes. The various codes used in the input/output system are presented. The input/output area of the computer system is relatively unreliable as compared with CPU or memory; therefore, error-correcting codes used in this area usually are much more powerful than single parity check codes. These include codes for the magnetic tape, disk, and drum units. The error coding techniques are compared with other techniques for increasing computer system reliability. The future trend of using error-correcting codes in a computer system is also discussed.     

Correcting a specified set of likely error patterns

The main concern of this article is to find linear codes which will correct a set of arbitrary error patterns. Although linear codes which have been designed for correcting random error patterns and burst error patterns can be used, we would like to find codes which will correct a specified set of error patterns with the fewest possible redundant bits. Here, to reduce the complexity involved in finding the code with the smallest redundancy which can correct a specified set of error patterns, algebraic codes whose parity check matrix exhibits a particular structure are considered. If the number of redundant bits is T, the columns of the parity check matrix must be increasing powers of a field element in GF(2^T). Given a set of error patterns to be corrected, computations to determine the code rates possible for these type of codes and hence the redundancy for different codeword lengths are presented. Results for various sets of error patterns suggest that the redundancy of these algebraic codes is close to the minimum redundancy possible for the set of error patterns specified and for any codeword length     

Some efficient binary codes constructed using Srivastava codes (Corresp.)

In this correspondence, we construct a new class of binary codes by exploiting the symmetry properties of the parity check matrix of the Srivastava codes. The construction is a generalization of Goppa's construction [1]. A number of the binary codes constructed are proved equal, or superior, to the best codes previously known.     

Design of Encoder and Decoder for LDPC Codes Using Hybrid H‐Matrix

Low‐density parity‐check (LDPC) codes have recently emerged due to their excellent performance. However, the parity check (H) matrices of the previous works are not adequate for hardware implementation of encoders or decoders. This paper proposes a hybrid parity check matrix which is efficient in hardware implementation of both decoders and encoders. The hybrid H‐matrices are constructed so that both the semi‐random technique and the partly parallel structure can be applied to design encoders and decoders. Using the proposed methods, the implementation of encoders can become practical while keeping the hardware complexity of the partly parallel decoder structures. An encoder and a decoder are designed using Verilog‐HDL and are synthesized using a 0.35 µm CMOS standard cell library.     

Algebraic Coding and Digital Redundancy

The techniques of coding theory are used to improve the reliability of digital devices. Redundancy is added to the device by the addition of extra digits which are independently computed from the input digits. A decoding device examines the original outputs along with the redundant outputs. The decoder may correct any errors it detects, not correct but locate the defective logic gate or subsystem, or only issue a general error warning. Majority voting and parity bit checking are introduced, and computations are made for several binary addition circuits. A detailed summary of coding theory is presented. This includes a discussion of algebraic codes, binary group codes, nonbinary linear codes, and error locating codes.     

Single error correcting and double error detecting coding scheme

A new coding technique for single error correction and double error detection in computer memory systems is proposed. The number of 1s in the parity check matrix for the proposed coding is fewer than all currently available codes for this purpose, except in two cases when they are almost equal to that obtained by Hsiao code. This results in simplified encoding and decoding circuitry for error detection and correction.     

Performance of low density parity check coded continuous phase frequency shift keying (LDPCC‐CPFSK) over fading channels

In this paper, in order to improve bit error performance, bandwidth efficiency and reduction of complexity compared to related schemes such as turbo codes, we combine low density parity check (LDPC) codes and continuous phase frequency shift keying (CPFSK) modulation and introduce a new scheme, called ‘low density parity check coded‐continuous phase frequency shift keying (LDPCC‐CPFSK)’. Since LDPC codes have very large Euclidean distance and use iterative decoding algorithms, they have high error correcting capacity and have very close performances to Shannon limit. In all communication systems, phase discontinuities of modulated signals result extra bandwidth requirements. Continuous phase modulation (CPM) is a powerful solution for this problem. Beside CPM provides good bandwidth efficiency; it also improves bit error performance with its memory unit. In our proposed scheme, LDPC and CPFSK, which is a special type of CPM, are considered together to improve both error performance and bandwidth efficiencies. We also obtain error performance curves of LDPCC‐CPFSK via computer simulations for both regular and irregular LDPC code. Simulation results are drawn for 4‐ary CPFSK, 8‐ary CPFSK and 16‐ary CPFSK over AWGN, Rician and Rayleigh fading channels for maximum 100 iterations, while the frame size is chosen as 504. Copyright © 2006 John Wiley & Sons, Ltd.     

LDPC Decoding by Failed Check Nodes for Serial Concatenated Code

The use of serial concatenated codes is an effective technique for alleviating the error floor phenomenon of low‐density parity‐check (LDPC) codes. An enhanced sum–product algorithm (SPA) for LDPC codes, which is suitable for serial concatenated codes, is proposed in this paper. The proposed algorithm minimizes the number of errors by using the failed check nodes (FCNs) in LDPC decoding. Hence, the error‐correcting capability of the serial concatenated code can be improved. The number of FCNs is simply obtained by the syndrome test, which is performed during the SPA. Hence, the decoding procedure of the proposed algorithm is similar to that of the conventional algorithm. The error performance of the proposed algorithm is analyzed and compared with that of the conventional algorithm. As a result, a gain of 1.4 dB can be obtained by the proposed algorithm at a bit error rate of 10^?8. In addition, the error performance of the proposed algorithm with just 30 iterations is shown to be superior to that of the conventional algorithm with 100 iterations.     

一种可快速编码的QC-LDPC码构造新方法

为解决LDPC码的编码复杂度问题,使其更易于硬件实现,提出了一种可快速编码的准循环LDPC码构造方法。该方法以基于循环置换矩阵的准循环LDPC码为基础,通过适当的打孔和行置换操作,使构造码的校验矩阵具有准双对角线结构,可利用校验矩阵直接进行快速编码,有效降低了LDPC码的编码复杂度。仿真结果表明,与IEEE 802.16e中的LDPC码相比,新方法构造的LDPC码在低编码复杂度的基础上获得了更好的纠错性能。     

A Class of High Rate Codes for Byte-Oriented Information Systems

In this paper we introduce a class of linear codes especially designed to provide additional error protection for data consisting of bytes all having even (or odd) parity (e.g., ASCII characters). The technique consists in adding an overall parity byte computed as a linear function of the information bytes. The linear function is designed such that the resulting codes can correct all single errors and all double errors occurring in distinct information bytes. It is shown that any code which can correct these latter mentioned error patterns has an overall length of at most 37 bytes, and a specific code of length 29 bytes is described. A practical decoding algorithm for the new class of codes is described. Finally, the performance of the codes, when used on the binary symmetric channel, is compared with that of the row-column codes for which the additional parity byte is simply the modulo-2 sum of the information bytes.