A PCB-compatible 3-dB coupler using microstrip-to-CPW via-hole transitions

A 3-dB coupler by implementing microstrip-to-coplanar waveguide (CPW) via-hole transitions is proposed. The proposed coupler, with the advantages of wider coupled line widths and spacing without using any bonding wires, can eliminate the uncertain factors of conventional Lange couplers caused by the printed circuit board (PCB) manufacturing processes. The proposed coupler can be easily fabricated on a single-layer PCB substrate instead of using multilayer substrates. Good agreements between the simulation and the measurement in the frequency range from 0.45 to 5 GHz can be achieved. The measured results at the center frequency of 2.4 GHz have the return loss better than -15dB; the insertion loss of coupled and direct ports is about 3/spl plusmn/ 0.2dB and the relative phase difference of 89/spl plusmn/0.3/spl deg/. The dimension of the coupler is 3.1cm /spl times/ 1.8cm.     

A 3-dB Quadrature Coupler Using Broadside-Coupled Coplanar Waveguides

A 3-dB quadrature coupler which combines the advantages of broadside-coupling and coplanar waveguide structure suitable for a single-layer printed circuit board (PCB) circuit design is proposed. Compared to the recently published broadside-coupled structures, the proposed coupler can easily be realized in a single-layer substrate by using PCB manufacturing processes to eliminate the effects of uncertain factors from a multi-layer substrate. With the operation bandwidth ranging from 2.1 to 2.7 GHz, the measured return loss and isolation are all better than 19dB, and the insertion losses and relative phase difference between the direct and coupled ports are at 3.2 plusmn 0.1 dB and 90 plusmn 0.6deg, respectively. The dimension of the coupler is 2.1 cm times 1.9 cm.     

A Novel Planar Three-Way Power Divider

A novel planar three-way power divider is proposed. Based on the conventional planar microstrip coupled line technology, the proposed three-way power divider can modify a three-way Wilkinson power divider from a three-dimensional configuration into a two-dimensional one, meanwhile, to keep the length of the circuit to be$lambda/$4. The planar structure enables easy circuit design in printed circuit boards and monolithic microwave integrated circuits. The design concept and implementation are discussed. From the measured results, less than 4.8$pm $0.1dB of the three equivalent insertion losses, less than 19.5dB of the return loss, and better than 17.5dB of isolation at 2.4GHz can be achieved.     

Diplexer With Integrated Filters and Photodetector in Ge–Si Using $Gamma-{X}$ and $Gamma-{M}$ Directions in a Grating Coupler

We demonstrate a central-office-type diplexer in which the filter and photodetector are monolithically integrated on a silicon-on-insulator substrate. The photonic integrated circuit receives a 1577-nm signal from an external laser and sends it to the fiber link using a two-dimensional grating coupler. The same grating coupler receives a 1270-nm signal from the fiber link and sends it to a monolithically integrated germanium photodetector using a polarization-diversity scheme to achieve polarization independence. The grating coupler is novel in that both the $Gamma-{X}$ and $Gamma-{M}$ directions are employed. This allows the grating coupler to couple both the 1577- and 1270-nm wavelengths with a small fiber tilt angle and hence have low polarization-dependent loss.      

一种新型半模基片集成波导三孔定向耦合器

半模基片集成波导(HMSIW)是近年来出现的一种高性能平面导波结构,具有传输损耗小、功率容量大、易于集成等优点,已开始广泛应用于微波无源器件的设计中。文章基于HMSIW技术与PCB工艺技术设计制作了一种新颖的三孔定向耦合器,通过在耦合孔上金属面蚀刻"工"字形槽增加孔的耦合量。设计的HMSIW三孔定向耦合器不仅保持了集成基片波导(SIW)定向耦合器的所有优点,而且在面积上减小了近50﹪,工作带宽拓展到1GHz。实测数据与仿真结果基本吻合,验证了设计方法的正确性与可行性。     

A Low-Voltage Broadband Feedforward-Linearized BJT Mixer

A low-voltage, feedforward-linearized bipolar mixer realizes an input$hboxIP_3$of$+$14.3 dBm and an input$hboxIP_2$of$+$54.5 dBm at 2.4 GHz. Conversion (power) gain over the 1–6GHz RF input range is 12.4$,pm,$0.35 dB, while the input$hboxIP_3$is 13.6$,pm,$1.8dBm over the same frequency range. The broadband mixer's RF input impedance varies from 60.3-j7.1 at 2.4 GHz to 57.4-j16.6$~Omega$at 5.8GHz. Measured SSB (50$Omega$) noise figure is 18.6 dB at 2.4 GHz. No on-chip inductors are used in the design, and the 0.14$hbox mm^2$(active area) mixer dissipates 7.2 mW from a (minimum) 1.2 V supply.     

A 16–44 GHz Compact Doubly Balanced Monolithic Ring Mixer

A novel and compact 16–44 GHz ultra-broadband doubly balanced monolithic ring mixer for Ku- to Ka-band applications implemented with a 0.15-$mu$m pHEMT process is presented. The proposed mixer is composed of a C-band miniature spiral balun and a 180$^{circ}$ hybrid formed with an interdigital coupler, a low-pass $pi$-network, and a high-pass T-network. The 180$^{circ}$ hybrid eliminates the use of a cross-over structure for application in the balanced mixer, as well as provides an output port for the RF extraction of up-converter application. This proposed configuration leads to a die size of less than 0.8$,times,$ 0.8 mm$^{2}$ . From the measured results, the mixer exhibits an 11–14 dB conversion loss, a 27–50 dB high LO-to-IF isolation over 16–44 GHz RF/LO bandwidth, and a 1-dB compression power of 14 dBm for both down- and up-converter applications.      

70 GHz Folded Loop Dual-Mode Bandpass Filter Fabricated Using 0.18 $mu$ m Standard CMOS Technology

This letter presents the design and implementation of a 70 GHz millimeter-wave compact folded loop dual-mode on-chip bandpass filter (BPF) using a 0.18 $mu$m standard CMOS process. A compact BPF, consisting of such a planar ring resonator structure having dual transmission zeros was fabricated and designed. The size of the designed filter is 650$,times,$ 670 $mu$ m$^{2}$ . Calculated circuit model, EM simulated and measured results of the proposed filter operating at 70 GHz are shown in a good agreement and have good performance. The filter has a 3-dB bandwidth of about 18 GHz at the center frequency of 70 GHz. The measured insertion loss of the passband is about 3.6 dB and the return loss is better than 10 dB within the passband.      

Substrate Integrated Waveguide Filter With Improved Stopband Performance for Satellite Ground Terminal

In this paper, patent pending substrate integrated waveguide (SIW) bandpass filters with moderate fractional bandwidth and improved stopband performance are proposed and demonstrated for a $Ka$ -band satellite ground terminal. Nonphysical cross-coupling provided by higher order modes in the oversized SIW cavities is used to generate the finite transmission zeros far away from the passband for improved stopband performance. Different input/output topologies of the filter are discussed for wide stopband applications. Design considerations including the design approach, filter configuration, and tolerance analysis are addressed. Two fourth-order filters with a passband of 19.2–21.2 GHz are fabricated on a single-layer Rogers RT/Duroid 6002 substrate using linear arrays of metallized via-holes by a standard printed circuit board process. Measured results of the two filters agree very well with simulated results, showing the in-band insertion loss is 0.9 dB or better, and the stopband attenuation in the frequency band of 29.5–30 GHz is better than 50 dB. Measurements over a temperature range of $-{hbox{20}} ^{circ}$C to $+{hbox{40}} ^{circ}$C show the passband remains almost unchanged.      

140 GHz基于CPWG单平衡基波混频GaAs集成电路

通过在300 μm厚度的GaAs衬底条件下,利用共面波导传输线实现了基波混频集成电路设计。利用半导体分析仪测试I-U和C-U曲线,并成功提取了相应的肖特基二极管模型。结合建立的肖特基二极管模型,代入Lange耦合器、中频结构和匹配网络等实现了140 GHz零中频基波混频片上电路,并加入了地-信号-地(GSG)测试封装。最终仿真结果表明：在固定中频1 GHz的条件下,变频损耗最优为-7 dB,3 dB带宽大于40 GHz。     

A 30 GHz Variable Gain Amplifier With High Output Voltage Swing for Ultra-Wideband Radar

This paper reports on the analysis, design and characterization of a 30 GHz fully differential variable gain amplifier for ultra-wideband radar systems. The circuit consists of a variable gain differential stage, which is fed by two cascaded emitter followers. Capacitive degeneration and inductive peaking are used to enhance bandwidth. The maximum differential gain is 11.5 dB with ${pm}1.5$ dB gain flatness in the desired frequency range. The amplifier gain can be regulated from 0 dB up to 11.5 dB. The circuit exhibits an output 1 dB compression point of 12 dBm. The measured differential output voltage swing is 1.23 V$_{pp}$ . The 0.75 mm$^2$ broadband amplifier consumes 560 mW at a supply voltage of ${pm}3.3$ V. It is manufactured in a low-cost 0.25 $mu$ m SiGe BiCMOS technology with a cut-off frequency of 75 GHz. The experimental results agree very well with the simulated response. A figure of merit has been proposed for comparing the amplifier performance to previously reported works.      

A design of wideband 3-dB coupler with N-section microstrip tandem structure

New design equations and a 3-dB microstrip coupler example for N-section tandem connected structure with wide bandwidth are presented. The proposed four-port S-parameters and equations are obtained from a port reduction method. The designed microstrip 3-dB coupler not only does not need high impedance lines, but also uses tight coupling gaps differently from conventional couplers such as Lange couplers, parallel coupled line couplers, etc. The measured data agrees well with the expected data, which show a wide bandwidth of 42%, an amplitude imbalance of /spl plusmn/0.5 dB, a phase unbalance of 1.0/spl deg/, and isolation characteristics of 15 dB at the band of 3.6 to 5.5 GHz.     

Lumped-Element Quadrature Power Splitters Using Mixed Right/Left-Handed Transmission Lines

This paper presents the design of lumped quadrature power splitters (LQPSs) based on unit cells of right-handed (RH) and left-handed (LH) synthetic transmission lines (TLs). The LQPSs include a lumped Wilkinson splitter, with phase-adjusting RH/LH TLs at the outputs. Two topologies, considered to be advantageous with regards to size and electric characteristics, are studied in detail. For these two, closed-form design equations are derived and the performances are analyzed by circuit simulations. The theory and simulation results are experimentally validated by monolithic-microwave integrated-circuit prototypes designed for a center frequency of 2.5 GHz. Both prototypes have performance that agree well with theory and design simulations. Within the frequency range of 2–3 GHz, the maximum amplitude and phase errors are less than 0.3 dB and 3$^circ$, respectively. All reflections and the isolation are better than$-$10 dB. The effective areas of the two prototypes are 900$, times,$700$mu$m$^2$and 720$, times,$520$mu$m$^2$, respectively.     

A 120-MHz–1.8-GHz CMOS DLL-Based Clock Generator for Dynamic Frequency Scaling

A delay-locked loop (DLL)-based clock generator for dynamic frequency scaling has been developed in a 0.35-$muhbox m$CMOS technology. The proposed clock generator can generate clock signals ranging from 120 MHz to 1.8 GHz and change the frequency dynamically in a short time. If the clock generator scales its output frequency dynamically by programming with the same last bit, it takes only one clock cycle to lock. In addition, the clock generator inherits advantages of a DLL. The proposed DLL-based clock generator occupies 0.07$hbox mm^2$and has a peak-to-peak jitter of$pm $6.6 ps at 1.3 GHz.     

79 GHz Slot Antennas Based on Substrate Integrated Waveguides (SIW) in a Flexible Printed Circuit Board

The design, fabrication and characterization of 79 GHz slot antennas based on substrate integrated waveguides (SIW) are presented in this paper. All the prototypes are fabricated in a polyimide flex foil using printed circuit board (PCB) fabrication processes. A novel concept is used to minimize the leakage losses of the SIWs at millimeter wave frequencies. Different losses in the SIWs are analyzed. SIW-based single slot antenna, longitudinal and four-by-four slot array antennas are numerically and experimentally studied. Measurements of the antennas show approximately 4.7%, 5.4% and 10.7% impedance bandwidth (${rm S}_{11}=-10$ dB) with 2.8 dBi, 6.0 dBi and 11.0 dBi maximum antenna gain around 79 GHz, respectively. The measured results are in good agreement with the numerical simulations.      

A 40-GHz Low-Noise Amplifier With a Positive-Feedback Network in 0.18-$mu{hbox{m}}$ CMOS

A novel circuit topology for a CMOS millimeter-wave low-noise amplifier (LNA) is presented in this paper. By adopting a positive-feedback network at the common-gate transistor of the input cascode stage, the small-signal gain can be effectively boosted, facilitating circuit operations at the higher frequency bands. In addition, $LC$ ladders are utilized as the inter-stage matching for the cascaded amplifiers such that an enhanced bandwidth can be achieved. Using a standard 0.18-$mu{hbox{m}}$ CMOS process, the proposed LNA is implemented for demonstration. At the center frequency of 40 GHz, the fabricated circuit exhibits a gain of 15 dB and a noise figure of 7.5 dB, while the return losses are better than 10 dB within the 3-dB bandwidth of 4 GHz. Operated at a 1.8-V supply, the LNA consumes a dc power of 36 mW.      

C 波段LTCC 无通孔微型Lange 耦合器的研究

研究了一种C波段LTCC无通孔微型Lange耦合器,其结构紧凑,尺寸小。LTCC叠层技术是实现高性能、高可靠、微型化微波元件的主流技术之一,尤其是在提高电路集成度方面。Lange耦合器由于其特殊的结构使得其可以实现宽频带、高性能。设计、制作了一种中心频率为4GHz的宽带3dB Lange耦合器,尺寸仅为7.0mm×2.2mm×1.4mm。在2.0～6.0GHz频带内测试结果如下:插入损耗<0.3dB,反射损耗<21dB,隔离>27dB,相位平衡<90±3°,最大承受功率<40W(连续波)。测试与仿真结果较吻合,验证了研究结果的一致性。     

A 3–10 GHz CMOS UWB Low-Noise Amplifier With ESD Protection Circuits

A low-power fully integrated low-noise amplifier (LNA) with an on-chip electrostatic-static discharge (ESD) protection circuit for ultra-wide band (UWB) applications is presented. With the use of a common-gate scheme with a ${rm g}_{rm m}$ -boosted technique, a simple input matching network, low noise figure (NF), and low power consumption can be achieved. Through the combination of an input matching network, an ESD clamp circuit has been designed for the proposed LNA circuit to enhance system robustness. The measured results show that the fabricated LNA can be operated over the full UWB bandwidth of 3.0 to 10.35 GHz. The input return loss $({rm S}_{11})$ and output return loss $({rm S}_{22})$ are less than ${-}8.3$ dB and ${-}9$ dB, respectively. The measured power gain $({rm S}_{21})$ is $11 pm 1.5$ dB, and the measured minimum NF is 3.3 dB at 4 GHz. The dc power dissipation is 7.2 mW from a 1.2 V supply. The chip area, including testing pads, is 1.05 mm$,times,$ 0.73 mm.      

A Phase-Locked Loop With Injection-Locked Frequency Multiplier in 0.18-$mu{hbox{m}}$ CMOS for $V$ -Band Applications

In this paper, a novel CMOS phase-locked loop (PLL) integrated with an injection-locked frequency multiplier (ILFM) that generates the $V$-band output signal is proposed. Since the proposed ILFM can generate the fifth-order harmonic frequency of the voltage-controlled oscillator (VCO) output, the operational frequency of the VCO can be reduced to only one-fifth of the desired frequency. With the loop gain smaller than unity in the ILFM, the output frequency range of the proposed PLL is from 53.04 to 58.0 GHz. The PLL is designed and fabricated in 0.18-$mu{hbox{m}}$ CMOS technology. The measured phase noises at 1- and 10-MHz offset from the carrier are $-$ 85.2 and $-{hbox{90.9 dBc}}/{hbox{Hz}}$, respectively. The reference spur level of $-{hbox{40.16 dBc}}$ is measured. The dc power dissipation of the fabricated PLL is 35.7 mW under a 1.8-V supply. It can be seen that the advantages of lower power dissipation and similar phase noise can be achieved in the proposed PLL structure. It is suitable for low-power and high-performance $V$-band applications.      

A Wideband Low Noise Amplifier With 4 kV HBM ESD Protection in 65 nm RF CMOS

This study presents a wideband low noise amplifier (LNA) including electrostatic discharge (ESD) protection circuits using 65 nm CMOS with a gate oxide thickness of only ${sim}2$ nm. By co-designing the ESD blocks with the core circuit, the LNA shows almost no performance degradation compared to the reference design without ESD. Under a power consumption of only 6.8 mW, the silicon results show that the LNA can achieve a peak power gain of 13.8 dB. Within the 3 dB bandwidth from 2.6 GHz to 6.6 GHz, the noise figure (NF) is in a range of 4.0 dB to 6.5 dB and the input reflection coefficient $S_{11}$ is below ${-}13.0$ dB. Using the miniaturized Shallow-Trench-Isolation (STI) diode of ${sim}40$ fF capacitance and a robust gate-driven power clamp configuration, the proposed LNA demonstrates an excellent 4 kV human body mode (HBM) ESD performance, which has the highest voltage/capacitance ratio ( ${sim}100$ V/fF) among the published results for RF LNA applications.